OpenCores
URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [memoryCores/] [rom.vhd.bak] - Blame information for rev 46

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 46 rrred
-- megafunction wizard: %ROM: 1-PORT%
2
-- GENERATION: STANDARD
3
-- VERSION: WM1.0
4
-- MODULE: altsyncram
5
 
6
-- ============================================================
7
-- File Name: rom.vhd
8
-- Megafunction Name(s):
9
--                      altsyncram
10
--
11
-- Simulation Library Files(s):
12
--                      altera_mf
13
-- ============================================================
14
-- ************************************************************
15
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16
--
17
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
18
-- ************************************************************
19
 
20
 
21
--Copyright (C) 1991-2013 Altera Corporation
22
--Your use of Altera Corporation's design tools, logic functions
23
--and other software and tools, and its AMPP partner logic
24
--functions, and any output files from any of the foregoing
25
--(including device programming or simulation files), and any
26
--associated documentation or information are expressly subject
27
--to the terms and conditions of the Altera Program License
28
--Subscription Agreement, Altera MegaCore Function License
29
--Agreement, or other applicable license agreement, including,
30
--without limitation, that your use is for the sole purpose of
31
--programming logic devices manufactured by Altera and sold by
32
--Altera or its authorized distributors.  Please refer to the
33
--applicable agreement for further details.
34
 
35
 
36
LIBRARY ieee;
37
USE ieee.std_logic_1164.all;
38
 
39
LIBRARY altera_mf;
40
USE altera_mf.all;
41
 
42
ENTITY rom IS
43
        PORT
44
        (
45
                address         : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
46
                clock           : IN STD_LOGIC  := '1';
47
                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
48
        );
49
END rom;
50
 
51
 
52
ARCHITECTURE SYN OF rom IS
53
 
54
        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);
55
 
56
 
57
 
58
        COMPONENT altsyncram
59
        GENERIC (
60
                address_aclr_a          : STRING;
61
                clock_enable_input_a            : STRING;
62
                clock_enable_output_a           : STRING;
63
                init_file               : STRING;
64
                intended_device_family          : STRING;
65
                lpm_hint                : STRING;
66
                lpm_type                : STRING;
67
                numwords_a              : NATURAL;
68
                operation_mode          : STRING;
69
                outdata_aclr_a          : STRING;
70
                outdata_reg_a           : STRING;
71
                widthad_a               : NATURAL;
72
                width_a         : NATURAL;
73
                width_byteena_a         : NATURAL
74
        );
75
        PORT (
76
                        address_a       : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
77
                        clock0  : IN STD_LOGIC ;
78
                        q_a     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
79
        );
80
        END COMPONENT;
81
 
82
BEGIN
83
        q    <= sub_wire0(7 DOWNTO 0);
84
 
85
        altsyncram_component : altsyncram
86
        GENERIC MAP (
87
                address_aclr_a => "NONE",
88
                clock_enable_input_a => "BYPASS",
89
                clock_enable_output_a => "BYPASS",
90
                init_file => "./ROMdata/rom.hex",
91
                intended_device_family => "Cyclone IV E",
92
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
93
                lpm_type => "altsyncram",
94
                numwords_a => 16384,
95
                operation_mode => "ROM",
96
                outdata_aclr_a => "NONE",
97
                outdata_reg_a => "CLOCK0",
98
                widthad_a => 14,
99
                width_a => 8,
100
                width_byteena_a => 1
101
        )
102
        PORT MAP (
103
                address_a => address,
104
                clock0 => clock,
105
                q_a => sub_wire0
106
        );
107
 
108
 
109
 
110
END SYN;
111
 
112
-- ============================================================
113
-- CNX file retrieval info
114
-- ============================================================
115
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
116
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
117
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
118
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
119
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
120
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
121
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
122
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
123
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
124
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
125
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
126
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
127
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
128
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
129
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
130
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
131
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
132
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROMdata/rom.hex"
133
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
134
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
135
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
136
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
137
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
138
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
139
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
140
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
141
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
142
-- Retrieval info: PRIVATE: rden NUMERIC "0"
143
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
144
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
145
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
146
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
147
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROMdata/rom.hex"
148
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
149
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
150
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
151
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
152
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
153
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
154
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
155
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
156
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
157
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
158
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
159
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
160
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
161
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
162
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
163
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
164
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.vhd TRUE
165
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
166
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE
167
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
168
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.vhd FALSE
169
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_waveforms.html FALSE
170
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_wave*.jpg FALSE
171
-- Retrieval info: LIB_FILE: altera_mf

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.