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[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [memoryCores/] [vram.vhd.bak] - Blame information for rev 46

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1 46 rrred
-- megafunction wizard: %RAM: 2-PORT%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altsyncram
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-- ============================================================
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-- File Name: vram3200x8.vhd
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-- Megafunction Name(s):
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--                      altsyncram
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--
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-- Simulation Library Files(s):
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--                      altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2010 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors.  Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY vram3200 IS
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        PORT
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        (
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                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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                rdaddress               : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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                rdclock         : IN STD_LOGIC ;
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                wraddress               : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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                wrclock         : IN STD_LOGIC  := '1';
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                wren            : IN STD_LOGIC  := '0';
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                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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        );
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END vram3200;
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ARCHITECTURE SYN OF vram3200x8 IS
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        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);
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        COMPONENT altsyncram
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        GENERIC (
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                address_reg_b           : STRING;
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                clock_enable_input_a            : STRING;
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                clock_enable_input_b            : STRING;
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                clock_enable_output_a           : STRING;
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                clock_enable_output_b           : STRING;
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                intended_device_family          : STRING;
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                lpm_type                : STRING;
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                numwords_a              : NATURAL;
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                numwords_b              : NATURAL;
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                operation_mode          : STRING;
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                outdata_aclr_b          : STRING;
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                outdata_reg_b           : STRING;
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                power_up_uninitialized          : STRING;
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                widthad_a               : NATURAL;
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                widthad_b               : NATURAL;
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                width_a         : NATURAL;
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                width_b         : NATURAL;
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                width_byteena_a         : NATURAL
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        );
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        PORT (
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                        wren_a  : IN STD_LOGIC ;
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                        clock0  : IN STD_LOGIC ;
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                        clock1  : IN STD_LOGIC ;
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                        address_a       : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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                        address_b       : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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                        q_b     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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                        data_a  : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
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        );
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        END COMPONENT;
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BEGIN
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        q    <= sub_wire0(7 DOWNTO 0);
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        altsyncram_component : altsyncram
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        GENERIC MAP (
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                address_reg_b => "CLOCK1",
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                clock_enable_input_a => "BYPASS",
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                clock_enable_input_b => "BYPASS",
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                clock_enable_output_a => "BYPASS",
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                clock_enable_output_b => "BYPASS",
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                intended_device_family => "Cyclone II",
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                lpm_type => "altsyncram",
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                numwords_a => 6143,
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                numwords_b => 6143,
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                operation_mode => "DUAL_PORT",
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                outdata_aclr_b => "NONE",
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                outdata_reg_b => "UNREGISTERED",
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                power_up_uninitialized => "FALSE",
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                widthad_a => 13,
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                widthad_b => 13,
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                width_a => 8,
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                width_b => 8,
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                width_byteena_a => 1
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        )
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        PORT MAP (
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                wren_a => wren,
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                clock0 => wrclock,
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                clock1 => rdclock,
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                address_a => wraddress,
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                address_b => rdaddress,
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                data_a => data,
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                q_b => sub_wire0
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        );
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock NUMERIC "1"
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-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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-- Retrieval info: PRIVATE: ECC NUMERIC "0"
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-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
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-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
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-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "49144"
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-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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-- Retrieval info: PRIVATE: MIFfilename STRING ""
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-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
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-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
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-- Retrieval info: PRIVATE: REGq NUMERIC "0"
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-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
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-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
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-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
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-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
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-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
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-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
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-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
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-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: enable NUMERIC "0"
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-- Retrieval info: PRIVATE: rden NUMERIC "0"
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-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "6143"
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-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "6143"
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-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
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-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
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-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
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-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
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-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL rdaddress[12..0]
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-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
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-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL wraddress[12..0]
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-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC wrclock
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-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
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-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
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-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
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-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
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-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
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-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
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-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8.bsf TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8_inst.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8_waveforms.html TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL vram3200x8_wave*.jpg FALSE
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-- Retrieval info: LIB_FILE: altera_mf

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