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[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [vhdl/] [clk_div.vhd.bak] - Blame information for rev 46

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Line No. Rev Author Line
1 46 rrred
library IEEE;
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use  IEEE.STD_LOGIC_1164.all;
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use  IEEE.STD_LOGIC_ARITH.all;
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use  IEEE.STD_LOGIC_UNSIGNED.all;
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ENTITY clk_div IS
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        PORT
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        (
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           clock_in_50Mhz       : IN    STD_LOGIC;
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      clock_25MHz          : OUT   STD_LOGIC;
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                clock_10MHz          : OUT   STD_LOGIC;
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                clock_357Mhz         : OUT   STD_LOGIC;
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                clock_1MHz                              : OUT   STD_LOGIC;
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                clock_100KHz                    : OUT   STD_LOGIC;
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                clock_10KHz                             : OUT   STD_LOGIC;
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                clock_1KHz                              : OUT   STD_LOGIC;
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                clock_100Hz                             : OUT   STD_LOGIC;
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                clock_10Hz                              : OUT   STD_LOGIC;
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                clock_1Hz                               : OUT   STD_LOGIC);
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END clk_div;
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ARCHITECTURE a OF clk_div IS
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        SIGNAL  count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
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   SIGNAL   count_357Mhz: STD_LOGIC_VECTOR(3 DOWNTO 0);
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        SIGNAL  count_10Mhz: STD_LOGIC_VECTOR(2 DOWNTO 0);
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        SIGNAL  count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
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        SIGNAL  count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
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        SIGNAL   clock_25Mhz_int, clock_10Mhz_int, clock_357Mhz_int, clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
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        SIGNAL  clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
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BEGIN
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--  Generate 25Mhz Clock
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_in_50Mhz'EVENT and clock_in_50Mhz = '1';
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                        clock_25Mhz_int <= not clock_25Mhz_int;
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-- Ripple clocks are used in this code to save prescalar hardware
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-- Sync all clock prescalar outputs back to master clock signal
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                        clock_25MHz   <= clock_25Mhz_int;
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                        clock_10MHz   <= clock_10Mhz_int;
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                        clock_357MHz  <= clock_357Mhz_int;
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                        clock_1Mhz    <= clock_1Mhz_int;
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                        clock_100Khz  <= clock_100Khz_int;
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                        clock_10Khz   <= clock_10Khz_int;
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                        clock_1Khz    <= clock_1Khz_int;
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                        clock_100hz   <= clock_100hz_int;
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                        clock_10hz    <= clock_10hz_int;
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                        clock_1hz     <= clock_1hz_int;
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        END PROCESS;
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-- Generate Clock 10Mhz
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_in_50Mhz'EVENT and clock_in_50Mhz = '1';
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                        IF count_10Mhz = 5 THEN
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                                count_10Mhz <= "000";
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                                clock_10Mhz_int <= not clock_10Mhz_int;
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                        ELSE
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                                count_10Mhz <= count_10Mhz + 1;
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                        END IF;
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        END PROCESS;
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        -- Generate Clock 3.57Mhz
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_in_50Mhz'EVENT and clock_in_50Mhz = '1';
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                        IF count_357Mhz < "1110" THEN
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                                count_357Mhz <= count_357Mhz + 1;
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                        ELSE
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                                count_357Mhz <= "0000";
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                                clock_357Mhz_int <= not clock_357Mhz_int;
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                        END IF;
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        END PROCESS;
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--  Generate Clock 1Mhz
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_25Mhz_int'EVENT and clock_25Mhz_int = '1';
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                        IF count_1Mhz < 24 THEN
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                                count_1Mhz <= count_1Mhz + 1;
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                        ELSE
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                                count_1Mhz <= "00000";
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                        END IF;
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                        IF count_1Mhz < 12 THEN
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                                clock_1Mhz_int <= '0';
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                        ELSE
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                                clock_1Mhz_int <= '1';
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                        END IF;
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        END PROCESS;
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-- Divide by 10
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
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                        IF count_100Khz /= 4 THEN
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                                count_100Khz <= count_100Khz + 1;
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                        ELSE
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                                count_100khz <= "000";
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                                clock_100Khz_int <= NOT clock_100Khz_int;
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                        END IF;
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        END PROCESS;
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-- Divide by 10
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
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                        IF count_10Khz /= 4 THEN
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                                count_10Khz <= count_10Khz + 1;
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                        ELSE
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                                count_10khz <= "000";
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                                clock_10Khz_int <= NOT clock_10Khz_int;
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                        END IF;
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        END PROCESS;
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-- Divide by 10
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
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                        IF count_1Khz /= 4 THEN
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                                count_1Khz <= count_1Khz + 1;
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                        ELSE
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                                count_1khz <= "000";
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                                clock_1Khz_int <= NOT clock_1Khz_int;
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                        END IF;
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        END PROCESS;
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-- Divide by 10
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
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                        IF count_100hz /= 4 THEN
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                                count_100hz <= count_100hz + 1;
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                        ELSE
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                                count_100hz <= "000";
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                                clock_100hz_int <= NOT clock_100hz_int;
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                        END IF;
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        END PROCESS;
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-- Divide by 10
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
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                        IF count_10hz /= 4 THEN
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                                count_10hz <= count_10hz + 1;
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                        ELSE
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                                count_10hz <= "000";
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                                clock_10hz_int <= NOT clock_10hz_int;
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                        END IF;
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        END PROCESS;
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-- Divide by 10
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        PROCESS
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        BEGIN
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                WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
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                        IF count_1hz /= 4 THEN
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                                count_1hz <= count_1hz + 1;
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                        ELSE
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                                count_1hz <= "000";
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                                clock_1hz_int <= NOT clock_1hz_int;
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                        END IF;
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        END PROCESS;
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END a;
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