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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_predecode_compress.v] - Blame information for rev 51

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1 26 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
7
// -- This program is free software; you can redistribute it and/or           --
8
// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
11
// --                                                                         --
12
// -- This program is distributed in the hope that it will be useful,         --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
20
// -- 02110-1301, USA.                                                        --
21
// --                                                                         --
22
// -----------------------------------------------------------------------------
23
// --                                                                         -- 
24
// --  Implements a 16-bit instruction decoder. The 16-bit instruction set is --
25
// --  not logically organized so as to save on encoding and thus the functs  --
26
// --  seem a bit complex.                                                    --
27
// --                                                                         --
28
// -----------------------------------------------------------------------------
29
 
30
`default_nettype none
31
 
32
module zap_predecode_compress (
33
        // Clock and reset.
34
        input wire              i_clk,
35
 
36
        // Input from I-cache.
37
        // Instruction and valid qualifier.
38
        input wire [31:0]       i_instruction,
39
        input wire              i_instruction_valid,
40
 
41 38 Revanth
        // Offset input.
42
        input wire [11:0]       i_offset,
43
 
44 26 Revanth
        // Interrupts. Active high level sensitive signals.
45
        input wire              i_irq,
46
        input wire              i_fiq,
47
 
48
        // Ensure compressed mode is active (T bit).
49
        input wire              i_cpsr_ff_t,
50
 
51
        //
52
        // Outputs to the ARM decoder.
53
        // 
54
 
55
        // Instruction, valid, undefined by this decoder and force 32-bit
56
        // align signals (requires memory to keep lower 2 bits as 00).
57
        output reg [34:0]       o_instruction,
58
        output reg              o_instruction_valid,
59
        output reg              o_und,
60
        output reg              o_force32_align,
61
 
62
        // Interrupt status output.
63
        output reg              o_irq,
64
        output reg              o_fiq
65
);
66
 
67
///////////////////////////////////////////////////////////////////////////////
68
 
69
`include "zap_defines.vh"
70
`include "zap_localparams.vh"
71
`include "zap_functions.vh"
72
 
73
///////////////////////////////////////////////////////////////////////////////
74
 
75 38 Revanth
reg [11:0] offset_w;  // Previous offset.
76 26 Revanth
 
77
///////////////////////////////////////////////////////////////////////////////
78
 
79 38 Revanth
always @*
80
        offset_w = i_offset;
81 26 Revanth
 
82
///////////////////////////////////////////////////////////////////////////////
83
 
84
always @*
85
begin
86
        // If you are not in compressed mode, just pass stuff on.
87
        o_instruction_valid     = i_instruction_valid;
88
        o_und                   = 0;
89
        o_instruction           = i_instruction;
90
        o_irq                   = i_irq;
91
        o_fiq                   = i_fiq;
92
        o_force32_align         = 0;
93
 
94
        if ( i_cpsr_ff_t && i_instruction_valid ) // compressed mode enable
95
        begin
96
                casez ( i_instruction[15:0] )
97 38 Revanth
                        T_BLX1                  : decode_blx1;
98
                        T_BLX2                  : decode_blx2;
99 26 Revanth
                        T_ADD_SUB_LO            : decode_add_sub_lo;
100
                        T_SWI                   : decode_swi;
101
                        T_BRANCH_COND           : decode_conditional_branch;
102
                        T_BRANCH_NOCOND         : decode_unconditional_branch;
103
                        T_BL                    : decode_bl;
104
                        T_BX                    : decode_bx;
105
                        T_SHIFT                 : decode_shift;
106
                        T_MCAS_IMM              : decode_mcas_imm;    // MOV,CMP,ADD,SUB IMM.
107
                        T_ALU_LO                : decode_alu_lo;
108
                        T_ALU_HI                : decode_alu_hi;
109
                        T_PC_REL_LOAD           : decode_pc_rel_load; // LDR Rd, [PC, {#imm8,0,0}] 
110
                        T_LDR_STR_5BIT_OFF      : decode_ldr_str_5bit_off;
111
                        T_LDRH_STRH_5BIT_OFF    : decode_ldrh_strh_5bit_off;
112
                        T_LDRH_STRH_REG         : decode_ldrh_strh_reg; // Complex. 
113
                        T_SP_REL_LDR_STR        : decode_sp_rel_ldr_str;
114
                        T_LDMIA_STMIA           : decode_ldmia_stmia;
115
                        T_POP_PUSH              : decode_pop_push;
116
                        T_GET_ADDR              : decode_get_addr;
117
                        T_MOD_SP                : decode_mod_sp;
118
                        default:
119
                        begin
120
                                o_und = 1; // Will take UND trap.
121
                        end
122
                endcase
123
        end
124
end
125
 
126
///////////////////////////////////////////////////////////////////////////////
127
 
128
task decode_get_addr;
129
begin: dcdGetAddr
130
        reg [11:0] imm;
131
        reg [3:0] rd;
132
 
133
        rd              = i_instruction[10:8];
134
        imm[7:0]        = i_instruction[7:0];
135
        imm[11:8]       = 4'd15; // To achieve a left shift of 2 i.e., *4
136
 
137
        o_instruction = 0;
138
 
139
        // ADD Rd, PC, imm
140
        o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd0, 4'd15, rd, imm};
141
 
142
        // ADD Rd, SP, imm
143
        if ( i_instruction[11] ) // SP
144
        begin
145
            o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd0, 4'd13, rd, imm};
146
        end
147
end
148
endtask
149
 
150
///////////////////////////////////////////////////////////////////////////////
151
 
152
task decode_mod_sp;
153
begin: dcdModSp
154
        reg [11:0] imm;
155
 
156
        imm[7:0]        = i_instruction[6:0];
157
        imm[11:8]       = 4'd15; // To achieve a left shift of 2 i.e., *4
158
 
159
        o_instruction = 0;
160
 
161
        o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd0, 4'd13, 4'd13, imm};
162
 
163
        // SUB/ADD R13, R13, imm
164
        if ( i_instruction[7] != 0 ) // SUB
165
        begin
166
         o_instruction[31:0] = {AL, 2'b00, 1'b1, SUB, 1'd0, 4'd13, 4'd13, imm};
167
        end
168
end
169
endtask
170
 
171
///////////////////////////////////////////////////////////////////////////////
172
 
173
task decode_pop_push;
174
begin: decodePopPush
175
        //
176
        // Uses an FD stack. Thus it is DA type i.e., post index down by 4. 
177
        // Writeback is implicit so make W = 0.
178
        //
179
 
180
        reg [3:0] base;
181
        reg [15:0] reglist;
182
 
183
        o_instruction = 0;
184
        base = 13;
185
 
186
        reglist = i_instruction[7:0];
187
 
188
        if ( i_instruction[8] == 1 && i_instruction[11] ) // Pop.
189
        begin
190
                reglist[15] = 1'd1;
191
        end
192
        else if ( i_instruction[8] == 1 && !i_instruction[11] ) // Push.
193
        begin
194
                reglist[14] = 1'd1;
195
        end
196
 
197
        o_instruction = {AL, 3'b100, 1'd0, 1'd0, 1'd0, 1'd1, i_instruction[11],
198
                                                        base, reglist};
199
end
200
endtask
201
 
202
///////////////////////////////////////////////////////////////////////////////
203
 
204
task decode_ldmia_stmia;
205
begin: dcdLdmiaStmia
206
        // Implicit IA type i.e., post index up by 4. Make WB = 1.
207
 
208
        reg [3:0] base;
209
        reg [15:0] reglist;
210
 
211
        base = i_instruction[10:8];
212
        reglist = i_instruction[7:0];
213
 
214
        o_instruction = 0;
215
        o_instruction = {AL, 3'b100, 1'd0, 1'd1, 1'd0, 1'd1, i_instruction[11],
216
                                base, reglist};
217
end
218
endtask
219
 
220
///////////////////////////////////////////////////////////////////////////////
221
 
222
task decode_sp_rel_ldr_str;
223
begin: dcdLdrRelStr
224
        reg [3:0] srcdest;
225
        reg [3:0] base;
226
        reg [11:0] imm;
227
 
228
        srcdest = i_instruction[10:8];
229
        base    = ARCH_SP;
230
        imm    = i_instruction[7:0] << 2;
231
 
232
        o_instruction = 0;
233
        o_instruction = {AL, 3'b010, 1'd1, 1'd0, 1'd0, 1'd0, i_instruction[11],
234
                        base, srcdest, imm};
235
end
236
endtask
237
 
238
///////////////////////////////////////////////////////////////////////////////
239
 
240
task decode_ldrh_strh_reg;
241
begin: dcdLdrhStrh
242
        // Use different load store format, instead of 3'b010, use 3'b011
243
 
244
        reg X,S,H;
245
        reg [3:0] srcdest, base;
246
        reg [11:0] offset;
247
 
248
        X = i_instruction[9];
249
        S = i_instruction[10];
250
        H = i_instruction[11];
251
        srcdest = i_instruction[2:0];
252
        base    = i_instruction[5:3];
253
        offset = i_instruction[8:6];
254
 
255
        o_instruction = 0;
256
 
257
        if ( X == 0 )
258
        begin
259
          case({H,S})
260
          0: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd0, 1'd0, 1'd0, base, srcdest, offset};// STR
261
          1: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd1, 1'd0, 1'd0, base, srcdest, offset};// STRB
262
          2: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, offset};// LDR
263
          3: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd1, 1'd0, 1'd1, base, srcdest, offset};// LDRB
264
          endcase
265
        end
266
        else
267
        begin
268
         case({S,H})
269
         0: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd0, base, srcdest, 4'd0, 2'b01,offset[3:0]};// STRH
270
         1: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, 4'd0, 2'b01,offset[3:0]};// LDRH
271
         2: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, 4'd0, 2'b10,offset[3:0]};// LDSB
272
         3: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, 4'd0, 2'b11,offset[3:0]};// LDSH
273
         endcase
274
        end
275
end
276
endtask
277
 
278
///////////////////////////////////////////////////////////////////////////////
279
 
280
task decode_ldrh_strh_5bit_off;
281
begin: dcdLdrhStrh5BitOff
282
 
283
        reg [3:0] rn;
284
        reg [3:0] rd;
285
        reg [7:0] imm;
286
 
287
        o_instruction = 0;
288
 
289
        rn = i_instruction[5:3];
290
        rd = i_instruction[2:0];
291
        imm[7:0] = i_instruction[10:6] << 1;
292
 
293
        // Unsigned halfword transfer
294
        o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd1, 1'd0, i_instruction[11],
295
                                        rn, rd, imm[7:4], 2'b01,imm[3:0]};
296
end
297
endtask
298
 
299
///////////////////////////////////////////////////////////////////////////////
300
 
301
task decode_ldr_str_5bit_off;
302
begin: dcLdrStr5BitOff
303
        reg [3:0] rn;
304
        reg [3:0] rd;
305
        reg [11:0] imm;
306
 
307
        o_instruction = 0;
308
 
309
        rn = i_instruction[5:3];
310
        rd = i_instruction[2:0];
311
 
312
        if ( i_instruction[12] == 1'd0 )
313
                imm[11:0] = i_instruction[10:6] << 2;
314
        else
315
                imm[11:0] = i_instruction[10:6];
316
 
317
        o_instruction = {AL, 3'b010, 1'd1, 1'd0, i_instruction[12], 1'd0,
318
                                               i_instruction[11], rn, rd, imm};
319
end
320
endtask
321
 
322
///////////////////////////////////////////////////////////////////////////////
323
 
324
task decode_pc_rel_load;
325
begin: dcPcRelLoad
326
        reg [3:0] rd;
327
        reg [11:0] imm;
328
 
329
        rd = i_instruction[10:8];
330
        imm = i_instruction[7:0] << 2;
331
 
332
        o_force32_align = 1'd1;
333
        o_instruction = 0;
334
        o_instruction = {AL, 3'b010, 1'd1, 1'd0, 1'd0, 1'd0,
335
                                        1'd1, 4'b1111, rd, imm};
336
end
337
endtask
338
 
339
///////////////////////////////////////////////////////////////////////////////
340
 
341
task decode_alu_hi;
342
begin:dcAluHi
343
        // Performs operations on HI registers (atleast some of them). 
344
        reg [1:0] op;
345
        reg [3:0] rd;
346
        reg [3:0] rs;
347
 
348
        o_instruction = 0;
349
 
350
        op = i_instruction[9:8];
351
        rd = {i_instruction[7], i_instruction[2:0]};
352
        rs = {i_instruction[6], i_instruction[5:3]};
353
 
354
        case(op)
355
        0: o_instruction[31:0] = {AL, 2'b00, 1'b0, ADD, 1'b0, rd, rd, 8'd0, rs}; // ADD Rd, Rd, Rs 
356
        1: o_instruction[31:0] = {AL, 2'b00, 1'b0, CMP, 1'b1, rd, rd, 8'd0, rs}; // CMP Rd, Rs
357
        2: o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'b0, rd, rd, 8'd0, rs}; // MOV Rd, Rs
358
        3:
359
        begin
360 51 Revanth
                $display($time, "%m: Error: This should never happen, should be taken by BX...!");
361 26 Revanth
                $finish;
362
        end
363
        endcase
364
end
365
endtask
366
 
367
///////////////////////////////////////////////////////////////////////////////
368
 
369
task decode_alu_lo;
370
begin: tskDecAluLo
371
        reg [3:0] op;
372
        reg [3:0] rs, rd;
373
        reg [3:0] rn;
374
 
375
        op = i_instruction[9:6];
376
        rs = i_instruction[5:3];
377
        rd = i_instruction[2:0];
378
 
379
        o_instruction = 0;
380
 
381
        case(op)
382
        0:      o_instruction[31:0] = {AL, 2'b00, 1'b0, AND, 1'd1, rd, rd, 8'd0, rs};                   // ANDS Rd, Rd, Rs
383
        1:      o_instruction[31:0] = {AL, 2'b00, 1'b0, EOR, 1'd1, rd, rd, 8'd0, rs};                   // EORS Rd, Rd, Rs
384
        2:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, LSL, 1'd1, rd};    // MOVS Rd, Rd, LSL Rs
385
        3:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, LSR, 1'd1, rd};    // MOVS Rd, Rd, LSR Rs
386
        4:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, ASR, 1'd1, rd};    // MOVS Rd, Rd, ASR Rs
387
        5:      o_instruction[31:0] = {AL, 2'b00, 1'b0, ADC, 1'd1, rd, rd, 8'd0, rs};                   // ADCS Rd, Rd, Rs
388
        6:      o_instruction[31:0] = {AL, 2'b00, 1'b0, SBC, 1'd1, rd, rd, 8'd0, rs};                   // SBCS Rd, Rs, Rs        
389
        7:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, ROR, 1'd1, rd};    // MOVS Rd, Rd, ROR Rs.
390
        8:      o_instruction[31:0] = {AL, 2'b00, 1'b0, TST, 1'd1, rd, rd, 8'd0, rs};                   // TST Rd, Rs
391
        9:      o_instruction[31:0] = {AL, 2'b00, 1'b1, RSB, 1'd1, rs, rd, 12'd0};                      // Rd = 0 - Rs
392
        10:     o_instruction[31:0] = {AL, 2'b00, 1'b1, CMP, 1'd1, rd, rd, 8'd0, rs};                   // CMP Rd, Rs
393
        11:     o_instruction[31:0] = {AL, 2'b00, 1'b1, CMN, 1'd1, rd, rd, 8'd0, rs};                   // CMN Rd, Rs
394
        12:     o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd1, rd, rd, 8'd0, rs};                   // ORRS Rd, Rd, rs 
395
        13:     o_instruction[31:0] = {AL, 4'b0000, 3'b000, 1'd1, rd, 4'd0, rd, 4'b1001, rs};           // MULS Rd, Rs, Rd
396
        14:     o_instruction[31:0] = {AL, 2'b00, 1'b1, BIC, 1'd1, rd, rd, 8'd0, rs};                   // BICS rd, rd, rs 
397
        15:     o_instruction[31:0] = {AL, 2'b00, 1'b1, MVN, 1'd1, rd, rd, 8'd0, rs};                   // MVNS rd, rd, rs
398
        endcase
399
end
400
endtask
401
 
402
///////////////////////////////////////////////////////////////////////////////
403
 
404
task decode_mcas_imm;
405
begin: tskDecodeMcasImm
406
        reg [1:0]  op;
407
        reg [3:0]  rd;
408
        reg [11:0] imm;
409
 
410
        o_instruction = 0;
411
 
412
        op = i_instruction[12:11];
413
        rd = i_instruction[10:8];
414
        imm =i_instruction[7:0];
415
 
416
        case (op)
417
                0:
418
                begin
419
                        // MOV Rd, Offset8
420
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, MOV, 1'd1, rd, rd, imm};
421
                end
422
                1:
423
                begin
424
                        // CMP Rd, Offset8
425
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, CMP, 1'd1, rd, rd, imm};
426
                end
427
                2:
428
                begin
429
                        // ADDS Rd, Rd, Offset8
430
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd1, rd, rd, imm};
431
                end
432
                3:
433
                begin
434
                        // SUBS Rd, Rd, Offset8
435
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, SUB, 1'd1, rd, rd, imm};
436
                end
437
        endcase
438
end
439
endtask
440
 
441
///////////////////////////////////////////////////////////////////////////////
442
 
443
task decode_add_sub_lo;
444
begin: tskDecodeAddSubLo
445
        reg [3:0] rn, rd, rs;
446
        reg [11:0] imm;
447
 
448
        o_instruction = 0;
449
 
450
        rn = i_instruction[8:6];
451
        rd = i_instruction[2:0];
452
        rs = i_instruction[5:3];
453
        imm = rn;
454
 
455
        case({i_instruction[9], i_instruction[10]})
456
        0:
457
        begin
458
                // Add Rd, Rs, Rn - Instr spec shift.
459
                o_instruction[31:0] = {AL, 2'b00, 1'b0, ADD, 1'd1, rs, rd, 8'd0, rn};
460
        end
461
        1:
462
        begin
463
                // Adds Rd, Rs, #Offset3 - Immediate.
464
                o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd1, rn, rd, imm};
465
        end
466
        2:
467
        begin
468
                // SUBS Rd, Rs, Rn - Instr spec shift.
469
                o_instruction[31:0] = {AL, 2'b00, 1'b0, SUB, 1'd1, rs, rd, 8'd0, rn};
470
        end
471
        3:
472
        begin
473
                // SUBS Rd, Rs, #Offset3 - Immediate.
474
                o_instruction[31:0] = {AL, 2'b00, 1'b1, SUB, 1'd1, rn, rd, imm};
475
        end
476
        endcase
477
end
478
endtask
479
 
480
///////////////////////////////////////////////////////////////////////////////
481
 
482
task decode_conditional_branch;
483
begin
484
        // An MSB of 1 indicates a left shift of 1.
485
        o_instruction           = {1'd1, 2'b0, i_instruction[11:8], 3'b101, 1'b0, 24'd0};
486
        o_instruction[23:0]     = $signed(i_instruction[7:0]);
487
end
488
endtask
489
 
490
///////////////////////////////////////////////////////////////////////////////
491
 
492
task decode_unconditional_branch;
493
begin
494
        // An MSB of 1 indicates a left shift of 1.
495
        o_instruction           = {1'd1, 2'b0, AL, 3'b101, 1'b0, 24'd0};
496
        o_instruction[23:0]     = $signed(i_instruction[10:0]);
497
end
498
endtask
499
 
500
///////////////////////////////////////////////////////////////////////////////
501
 
502 38 Revanth
task decode_blx1;
503
begin
504
        o_instruction = 0; // Default value.
505
 
506
        // Generate a BLX1.
507
        o_instruction[31:25] =  7'b1111_101;    // BLX1 identifier.   
508
        o_instruction[24]    =  1'd0;           // H - bit.
509
        o_instruction[23:0]  =  ($signed(offset_w) << 12) | (i_instruction[10:0] << 1);  // Corrected.
510
        o_irq                = 1'd0;
511
        o_fiq                = 1'd0;
512
end
513
endtask
514
 
515
////////////////////////////////////////////////////////////////////////////////
516
 
517
task decode_blx2;
518
begin
519
        o_instruction = {4'b1110,4'b0001,4'b0010,4'b1111,4'b1111,4'b1111,4'b0011, i_instruction[6:3]};
520
        o_irq         = 1'd0;
521
        o_fiq         = 1'd0;
522
end
523
endtask
524
 
525
///////////////////////////////////////////////////////////////////////////////
526
 
527 26 Revanth
task decode_bl;
528
begin
529
        case ( i_instruction[11] )
530
                1'd0:
531
                begin
532 38 Revanth
                        // Send out a dummy instruction. Preserve lower
533
                        // 12-bits though to serve as offset. Set condition
534
                        // code to NV.
535
                        o_instruction        = i_instruction[11:0];
536
                        o_instruction[31:28] = 4'b1111;
537
                        o_irq                = 1'd0;
538
                        o_fiq                = 1'd0;
539 26 Revanth
                end
540
                1'd1:
541
                begin
542
                        // Generate a full jump.
543
                        o_instruction = {1'd1, 2'b0, AL, 3'b101, 1'b1, 24'd0};
544 38 Revanth
                        o_instruction[23:0] = ($signed(offset_w) << 12) | (i_instruction[10:0] << 1);  // Corrected.
545 26 Revanth
                        o_irq           = 1'd0;
546
                        o_fiq           = 1'd0;
547
                end
548
        endcase
549
end
550
endtask
551
 
552
///////////////////////////////////////////////////////////////////////////////
553
 
554
task decode_bx;
555
begin
556
        // Generate a BX Rm.
557
        o_instruction = 32'b0000_0001_0010_1111_1111_1111_0001_0000;
558
        o_instruction[31:28] = AL;
559
        o_instruction[3:0]   = i_instruction[6:3];
560
end
561
endtask
562
 
563
///////////////////////////////////////////////////////////////////////////////
564
 
565
task decode_swi;
566
begin
567
        // Generate a SWI.
568
        o_instruction = 32'b0000_1111_0000_0000_0000_0000_0000_0000;
569
        o_instruction[31:28] = AL;
570
        o_instruction[7:0]   = i_instruction[7:0];
571
end
572
endtask
573
 
574
///////////////////////////////////////////////////////////////////////////////
575
 
576
task decode_shift;
577
begin
578
        // Compressed shift instructions. Decompress to ARM with instruction specified shift.
579
        o_instruction           = 32'd0;                // Extension -> 0.
580
        o_instruction[31:28]    = AL;                   // Always execute.
581
        o_instruction[27:26]    = 2'b00;                // Data processing.
582
        o_instruction[25]       = 1'd0;                 // Immediate is ZERO.
583
        o_instruction[24:21]    = MOV;                  // Operation is MOV.
584
        o_instruction[20]       = 1'd1;                 // Do update flags.
585
        o_instruction[19:16]    = 4'd0;                 // ALU source. Doesn't matter.
586
        o_instruction[15:12]    = i_instruction[2:0] ;  // Destination. 
587
        o_instruction[11:7]     = i_instruction[10:6];  // Shamt.
588
        o_instruction[6:5]      = i_instruction[12:11]; // Shtype.
589
        o_instruction[3:0]      = i_instruction[5:3];   // Shifter source.
590
end
591
endtask
592
 
593
///////////////////////////////////////////////////////////////////////////////
594
 
595
endmodule
596
`default_nettype wire

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