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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_ram_simple.v] - Blame information for rev 51

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// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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// --                                                                         -- 
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// --  Synthesizes to standard 1R + 1W block RAM. The read and write addresses--
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// --  may be specified separately. Only for FPGA.                            --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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module zap_ram_simple #(
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        parameter WIDTH = 32,
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        parameter DEPTH = 32
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)
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(
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        input wire                          i_clk,
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        // Write and read enable.
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        input wire                          i_wr_en,
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        input wire                          i_rd_en,
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        // Write data and address.
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        input wire [WIDTH-1:0]              i_wr_data,
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        input wire[$clog2(DEPTH)-1:0]       i_wr_addr,
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        // Read address and data.
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        input wire [$clog2(DEPTH)-1:0]      i_rd_addr,
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        output reg [WIDTH-1:0]              o_rd_data
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);
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// Memory array.
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reg [WIDTH-1:0] mem [DEPTH-1:0];
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// Initialize block RAM to 0.
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initial
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begin: blk1
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        integer i;
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        for(i=0;i<DEPTH;i=i+1)
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                mem[i] = {WIDTH{1'd0}};
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end
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// Read logic.
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always @ (posedge i_clk)
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begin
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        if ( i_rd_en )
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                o_rd_data <= mem [ i_rd_addr ];
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end
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// Write logic.
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always @ (posedge i_clk)
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begin
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        if ( i_wr_en )
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                mem [ i_wr_addr ] <= i_wr_data;
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end
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endmodule // ram_simple.v
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`default_nettype wire
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// ----------------------------------------------------------------------------
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// EOF
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// ----------------------------------------------------------------------------

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