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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_register_file.v] - Blame information for rev 43

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1 26 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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// --                                                                         -- 
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// --  ZAP register file implemented using flip-flops which makes sense for an--
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// --  FPGA implementation where flip-flops are plentiful.                    --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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module zap_register_file
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(
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        input wire              i_clk,
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        input wire              i_reset,
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        input wire              i_wen,
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        input wire  [5:0]       i_wr_addr_a,
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                                i_wr_addr_b,       // 2 write addresses.
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        input wire  [31:0]      i_wr_data_a,
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                                i_wr_data_b,       // 2 write data.
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        input wire  [5:0]       i_rd_addr_a,
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                                i_rd_addr_b,
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                                i_rd_addr_c,
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                                i_rd_addr_d,
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        output reg  [31:0]      o_rd_data_a,
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                                o_rd_data_b,
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                                o_rd_data_c,
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                                o_rd_data_d
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);
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// Dual distributed RAM setup.
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reg [31:0] mem [39:0];
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reg [31:0] MEM [39:0];
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initial
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begin: blk1
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        integer i;
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        for(i=0;i<40;i=i+1)
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        begin
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                mem[i] = 0;
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                MEM[i] = 0;
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        end
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end
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reg [39:0] sel;
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73 43 Revanth
// assertions_start
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        wire [31:0] r0;  assign r0 =  sel[0]  ? MEM[0] : mem[0];
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        wire [31:0] r1;  assign r1 =  sel[1]  ? MEM[1] : mem[1];
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        wire [31:0] r2;  assign r2 =  sel[2]  ? MEM[2] : mem[2];
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        wire [31:0] r3;  assign r3 =  sel[3]  ? MEM[3] : mem[3];
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        wire [31:0] r4;  assign r4 =  sel[4]  ? MEM[4] : mem[4];
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        wire [31:0] r5;  assign r5 =  sel[5]  ? MEM[5] : mem[5];
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        wire [31:0] r6;  assign r6 =  sel[6]  ? MEM[6] : mem[6];
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        wire [31:0] r7;  assign r7 =  sel[7]  ? MEM[7] : mem[7];
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        wire [31:0] r8;  assign r8 =  sel[8]  ? MEM[8] : mem[8];
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        wire [31:0] r9;  assign r9 =  sel[9]  ? MEM[9] : mem[9];
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        wire [31:0] r10; assign r10 = sel[10] ? MEM[10] : mem[10];
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        wire [31:0] r11; assign r11 = sel[11] ? MEM[11] : mem[11];
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        wire [31:0] r12; assign r12 = sel[12] ? MEM[12] : mem[12];
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        wire [31:0] r13; assign r13 = sel[13] ? MEM[13] : mem[13];
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        wire [31:0] r14; assign r14 = sel[14] ? MEM[14] : mem[14];
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        wire [31:0] r15; assign r15 = sel[15] ? MEM[15] : mem[15];
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        wire [31:0] r16; assign r16 = sel[16] ? MEM[16] : mem[16];
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        wire [31:0] r17; assign r17 = sel[17] ? MEM[17] : mem[17];
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        wire [31:0] r18; assign r18 = sel[18] ? MEM[18] : mem[18];
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        wire [31:0] r19; assign r19 = sel[19] ? MEM[19] : mem[19];
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        wire [31:0] r20; assign r20 = sel[20] ? MEM[20] : mem[20];
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        wire [31:0] r21; assign r21 = sel[21] ? MEM[21] : mem[21];
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        wire [31:0] r22; assign r22 = sel[22] ? MEM[22] : mem[22];
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        wire [31:0] r23; assign r23 = sel[23] ? MEM[23] : mem[23];
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        wire [31:0] r24; assign r24 = sel[24] ? MEM[24] : mem[24];
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        wire [31:0] r25; assign r25 = sel[25] ? MEM[25] : mem[25];
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        wire [31:0] r26; assign r26 = sel[26] ? MEM[26] : mem[26];
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        wire [31:0] r27; assign r27 = sel[27] ? MEM[27] : mem[27];
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        wire [31:0] r28; assign r28 = sel[28] ? MEM[28] : mem[28];
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        wire [31:0] r29; assign r29 = sel[29] ? MEM[29] : mem[29];
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        wire [31:0] r30; assign r30 = sel[30] ? MEM[30] : mem[30];
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        wire [31:0] r31; assign r31 = sel[31] ? MEM[31] : mem[31];
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        wire [31:0] r32; assign r32 = sel[32] ? MEM[32] : mem[32];
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        wire [31:0] r33; assign r33 = sel[33] ? MEM[33] : mem[33];
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        wire [31:0] r34; assign r34 = sel[34] ? MEM[34] : mem[34];
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        wire [31:0] r35; assign r35 = sel[35] ? MEM[35] : mem[35];
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        wire [31:0] r36; assign r36 = sel[36] ? MEM[36] : mem[36];
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        wire [31:0] r37; assign r37 = sel[37] ? MEM[37] : mem[37];
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        wire [31:0] r38; assign r38 = sel[38] ? MEM[38] : mem[38];
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        wire [31:0] r39; assign r39 = sel[39] ? MEM[39] : mem[39];
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// assertions_end
115 26 Revanth
 
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always @ (posedge i_clk)
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begin
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        if ( i_reset )
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        begin
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                sel <= 40'd0;
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        end
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        else
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        begin
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                sel [ i_wr_addr_a ] <= 1'd0;
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                sel [ i_wr_addr_b ] <= 1'd1;
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        end
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end
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always @ (posedge i_clk)
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begin
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        if ( i_wen )
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        begin
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                mem [ i_wr_addr_a ] <= i_wr_data_a;
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                MEM [ i_wr_addr_b ] <= i_wr_data_b;
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        end
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end
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always @*
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begin
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        o_rd_data_a = sel[i_rd_addr_a] ? MEM [ i_rd_addr_a ] : mem [ i_rd_addr_a ];
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        o_rd_data_b = sel[i_rd_addr_b] ? MEM [ i_rd_addr_b ] : mem [ i_rd_addr_b ];
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        o_rd_data_c = sel[i_rd_addr_c] ? MEM [ i_rd_addr_c ] : mem [ i_rd_addr_c ];
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        o_rd_data_d = sel[i_rd_addr_d] ? MEM [ i_rd_addr_d ] : mem [ i_rd_addr_d ];
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end
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endmodule // bram_wrapper.v
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`default_nettype wire

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