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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_shift_shifter.v] - Blame information for rev 51

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1 26 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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module zap_shift_shifter
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#(
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        parameter SHIFT_OPS = 5
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)
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(
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        // Source value.
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        input  wire [31:0]                      i_source,
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        // Shift amount.
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        input  wire [7:0]                       i_amount,
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        // Carry in.
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        input  wire                             i_carry,
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        // Shift type.
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        input  wire [$clog2(SHIFT_OPS)-1:0]     i_shift_type,
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        // Output result and output carry.
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        output reg [31:0]                       o_result,
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        output reg                              o_carry
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);
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`include "zap_defines.vh"
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`include "zap_localparams.vh"
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`include "zap_functions.vh"
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///////////////////////////////////////////////////////////////////////////////
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always @*
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begin
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        // Prevent latch inference.
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        o_result        = i_source;
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        o_carry         = 0;
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        case ( i_shift_type )
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                // Logical shift left, logical shift right and 
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                // arithmetic shift right.
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                LSL:    {o_carry, o_result} = {i_carry, i_source} << i_amount;
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                LSR:    {o_result, o_carry} = {i_source, i_carry} >> i_amount;
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                ASR:
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                begin:blk1111
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                        reg signed [32:0] res, res1;
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                        res = {i_source, i_carry};
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                        res1 = $signed(res) >>> i_amount;
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                        {o_result, o_carry} = res1;
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                end
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                ROR: // Rotate right.
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                begin
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                        o_result = ( i_source >> i_amount[4:0] )  |
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                                   ( i_source << (32 - i_amount[4:0] ) );
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                        o_carry  = ( i_amount[7:0] == 0) ?
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                                     i_carry  : ( (i_amount[4:0] == 0) ?
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                                     i_source[31] : o_result[31] );
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                end
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                RORI, ROR_1:
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                begin
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                        // ROR #n (ROR_1)
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                        o_result = ( i_source >> i_amount[4:0] )  |
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                                   (i_source << (32 - i_amount[4:0] ) );
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                        o_carry  = i_amount ? o_result[31] : i_carry;
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                end
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                // ROR #0 becomes this.
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                RRC:    {o_result, o_carry}        = {i_carry, i_source};
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                default: // For lint.
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                begin
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                end
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        endcase
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end
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///////////////////////////////////////////////////////////////////////////////
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endmodule // zap_shift_shifter.v
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104 26 Revanth
`default_nettype wire
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// ----------------------------------------------------------------------------
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// EOF
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// ----------------------------------------------------------------------------

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