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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_sync_fifo.v] - Blame information for rev 51

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// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         --
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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// -- This is a simple synchronous FIFO.                                      --
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// -----------------------------------------------------------------------------
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`default_nettype none
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// FWFT means "First Word Fall Through".
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module zap_sync_fifo #(
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        parameter WIDTH            = 32,
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        parameter DEPTH            = 32,
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        parameter FWFT             = 1,
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        parameter PROVIDE_NXT_DATA = 0
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)
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(
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        // Clock and reset
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        input   wire             i_clk,
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        input   wire             i_reset,
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        // Flow control
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        input   wire             i_ack,
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        input   wire             i_wr_en,
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        // Data busses
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        input   wire [WIDTH-1:0] i_data,
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        output  reg [WIDTH-1:0]  o_data,
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        output  reg [WIDTH-1:0]  o_data_nxt,
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        // Flags
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        output wire              o_empty,
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        output wire              o_full,
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        output wire              o_empty_n,
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        output wire              o_full_n,
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        output wire              o_full_n_nxt
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);
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// Xilinx ISE does not allow $CLOG2 in localparams.
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parameter PTR_WDT = $clog2(DEPTH) + 32'd1;
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parameter [PTR_WDT-1:0] DEFAULT = {PTR_WDT{1'd0}};
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// Variables
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reg [PTR_WDT-1:0] rptr_ff;
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reg [PTR_WDT-1:0] rptr_nxt;
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reg [PTR_WDT-1:0] wptr_ff;
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reg               empty, nempty;
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reg               full, nfull;
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reg [PTR_WDT-1:0] wptr_nxt;
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reg [WIDTH-1:0]   mem [DEPTH-1:0];
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wire [WIDTH-1:0]  dt;
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reg [WIDTH-1:0]   dt1;
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reg               sel_ff;
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reg [WIDTH-1:0]   bram_ff;
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reg [WIDTH-1:0]   dt_ff;
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// Assigns
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assign o_empty = empty;
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assign o_full  = full;
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assign o_empty_n = nempty;
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assign o_full_n = nfull;
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assign o_full_n_nxt = i_reset ? 1 :
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                      !( ( wptr_nxt[PTR_WDT-2:0] == rptr_nxt[PTR_WDT-2:0] ) &&
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                       ( wptr_nxt != rptr_nxt ) );
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// FIFO write logic.
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always @ (posedge i_clk)
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        if ( i_wr_en && !o_full )
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                mem[wptr_ff[PTR_WDT-2:0]] <= i_data;
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// FIFO read logic
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generate
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begin:gb1
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        if ( FWFT == 1 )
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        begin:f1
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                // Retimed output data compared to normal FIFO.
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                always @ (posedge i_clk)
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                begin
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                         dt_ff <= i_data;
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                        sel_ff <= ( i_wr_en && (wptr_ff == rptr_nxt) );
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                       bram_ff <= mem[rptr_nxt[PTR_WDT-2:0]];
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                end
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                // Output signal steering MUX.
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                always @*
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                begin
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                        o_data = sel_ff ? dt_ff : bram_ff;
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                        o_data_nxt = 0; // Tied off.
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                end
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        end
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        else
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        begin:f0
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                always @ (posedge i_clk)
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                begin
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                        if ( i_ack && nempty ) // Read request and not empty.
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                        begin
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                                o_data <= mem [ rptr_ff[PTR_WDT-2:0] ];
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                        end
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                end
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                if ( PROVIDE_NXT_DATA )
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                begin: f11
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                        always @ (*)
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                        begin
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                                if ( i_ack && nempty )
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                                        o_data_nxt = mem [ rptr_ff[PTR_WDT-2:0] ];
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                                else
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                                        o_data_nxt = o_data;
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                        end
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                end
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                else
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                begin: f22
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                        always @* o_data_nxt = 0;
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                end
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        end
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end
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endgenerate
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// Flip-flop update.
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always @ (posedge i_clk)
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begin
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        dt1     <= i_reset ? 0 : i_data;
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        rptr_ff <= i_reset ? 0 : rptr_nxt;
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        wptr_ff <= i_reset ? 0 : wptr_nxt;
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        empty   <= i_reset ? 1 : ( wptr_nxt == rptr_nxt );
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        nempty  <= i_reset ? 0 : ( wptr_nxt != rptr_nxt );
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        nfull   <= o_full_n_nxt;
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        full    <= !o_full_n_nxt;
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end
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// Pointer updates.
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always @*
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begin
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        wptr_nxt = wptr_ff + (i_wr_en && !o_full);
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        rptr_nxt = rptr_ff + (i_ack && !o_empty);
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end
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endmodule // zap_sync_fifo
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`default_nettype wire
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// ----------------------------------------------------------------------------
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// EOF
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// ----------------------------------------------------------------------------

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