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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_thumb_decoder.v] - Blame information for rev 51

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1 26 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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// --                                                                         --
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// --  Implements a 16-bit instruction decoder. The 16-bit instruction set is --
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// --  not logically organized so as to save on encoding and thus the code    -- 
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// --  seem a bit complex.                                                    --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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module zap_thumb_decoder (
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        // Clock and reset.
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        input wire              i_clk,
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        input wire              i_reset,
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        // Code stall.
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        input wire              i_clear_from_writeback,
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        input wire              i_data_stall,
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        input wire              i_clear_from_alu,
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        input wire              i_stall_from_shifter,
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        input wire              i_stall_from_issue,
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        input wire              i_stall_from_decode,
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        input wire              i_clear_from_decode,
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        // Predictor status.
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        input wire  [1:0]       i_taken,
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        // Input from I-cache.
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        // Instruction and valid qualifier.
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        input wire [31:0]       i_instruction,
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        input wire              i_instruction_valid,
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        // Interrupts. Active high level sensitive signals.
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        input wire              i_irq,
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        input wire              i_fiq,
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        // Aborts.
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        input wire              i_iabort,
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        output reg              o_iabort,
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        // Ensure compressed mode is active (T bit).
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        input wire              i_cpsr_ff_t,
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        // Program counter.
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        input wire      [31:0]  i_pc_ff,
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        input wire      [31:0]  i_pc_plus_8_ff,
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        //
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        // Outputs to the ARM decoder.
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        // 
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        // Instruction, valid, undefined by this decoder and force 32-bit
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        // align signals (requires memory to keep lower 2 bits as 00).
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        output reg [34:0]       o_instruction,
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        output reg              o_instruction_valid,
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        output reg              o_und,
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        output reg              o_force32_align,
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        // PCs.
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        output  reg [31:0]      o_pc_ff,
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        output  reg [31:0]      o_pc_plus_8_ff,
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        // Interrupt status output.
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        output reg              o_irq,
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        output reg              o_fiq,
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        // Taken
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        output reg      [1:0]   o_taken_ff
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);
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`include "zap_defines.vh"
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`include "zap_localparams.vh"
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`include "zap_functions.vh"
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wire [34:0] instruction_nxt;
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wire instruction_valid_nxt;
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wire und_nxt;
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wire force32_nxt;
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wire irq_nxt;
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wire fiq_nxt;
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reg  [1:0] taken_nxt;
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zap_predecode_compress u_zap_predecode_compress (
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        .i_clk(i_clk),
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        .i_instruction(i_instruction),
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        .i_instruction_valid(i_instruction_valid),
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        .i_irq(i_irq),
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        .i_fiq(i_fiq),
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        .i_offset(o_instruction[11:0]),
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        .i_cpsr_ff_t(i_cpsr_ff_t),
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        .o_instruction(instruction_nxt),
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        .o_instruction_valid(instruction_valid_nxt),
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        .o_und(und_nxt),
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        .o_force32_align(force32_nxt),
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        .o_irq(irq_nxt),
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        .o_fiq(fiq_nxt)
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);
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always @ (posedge i_clk)
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begin
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        if ( i_reset )
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        begin
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                o_instruction_valid <= 1'd0;
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                o_irq <= 0;
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                o_fiq <= 0;
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                o_und <= 0;
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                o_iabort <= 0;
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        end
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        else if ( i_clear_from_writeback )
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        begin
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                o_instruction_valid <= 1'd0;
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                o_irq <= 0;
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                o_fiq <= 0;
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                o_und <= 0;
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                o_iabort <= 0;
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        end
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        else if ( i_data_stall )
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        begin
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        end
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        else if ( i_clear_from_alu )
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        begin
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                o_instruction_valid <= 1'd0;
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                o_irq <= 0;
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                o_fiq <= 0;
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                o_und <= 0;
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                o_iabort <= 0;
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        end
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        else if ( i_stall_from_shifter ) begin end
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        else if ( i_stall_from_issue )   begin end
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        else if ( i_stall_from_decode )  begin end
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        else if ( i_clear_from_decode )
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        begin
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                o_instruction_valid <= 1'd0;
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                o_irq <= 0;
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                o_fiq <= 0;
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                o_und <= 0;
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                o_iabort <= 0;
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        end
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        else // BUG FIX.
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        begin
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                o_iabort                <= i_iabort;
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                o_instruction_valid     <= instruction_valid_nxt;
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                o_instruction           <= instruction_nxt;
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                o_und                   <= und_nxt;
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                o_force32_align         <= force32_nxt;
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                o_pc_ff                 <= i_pc_ff;
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                o_pc_plus_8_ff          <= i_pc_plus_8_ff;
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                o_irq                   <= irq_nxt;
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                o_fiq                   <= fiq_nxt;
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                o_taken_ff              <= i_taken;
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        end
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end
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// Helpful for debug.
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zap_decompile u_zap_decompile (
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        .i_instruction  ({1'd0, o_instruction}),
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        .i_dav          (o_instruction_valid),
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        .o_decompile    ()
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);
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183 43 Revanth
endmodule // zap_thumb_decoder
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185 26 Revanth
`default_nettype wire
186 51 Revanth
 
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// ----------------------------------------------------------------------------
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// EOF
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// ----------------------------------------------------------------------------

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