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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_top.v] - Blame information for rev 43

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1 26 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
20
// -- 02110-1301, USA.                                                        --
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// --                                                                         --
22
// -----------------------------------------------------------------------------
23
// --                                                                        -- 
24
// --  This is the top module of the ZAP processor. It contains instances of --
25
// --  processor core and the memory management units. I and D WB busses     --
26
// --  are provided.                                                         --
27
// --                                                                        --
28
// ----------------------------------------------------------------------------
29
 
30
`default_nettype none
31
 
32
module zap_top #(
33
 
34 43 Revanth
// -----------------------------------
35
// BP entries, FIFO depths
36
// -----------------------------------
37
 
38 26 Revanth
parameter               BP_ENTRIES              = 1024, // Predictor depth.
39
parameter               FIFO_DEPTH              = 4,    // FIFO depth.
40
parameter               STORE_BUFFER_DEPTH      = 16,   // Depth of the store buffer.
41
 
42
// ----------------------------------
43
// Data MMU/Cache configuration.
44
// ----------------------------------
45
parameter [31:0] DATA_SECTION_TLB_ENTRIES =  32'd4,    // Section TLB entries.
46
parameter [31:0] DATA_LPAGE_TLB_ENTRIES   =  32'd8,    // Large page TLB entries.
47
parameter [31:0] DATA_SPAGE_TLB_ENTRIES   =  32'd16,   // Small page TLB entries.
48
parameter [31:0] DATA_CACHE_SIZE          =  32'd1024, // Cache size in bytes.
49
 
50
// ----------------------------------
51
// Code MMU/Cache configuration.
52
// ----------------------------------
53
parameter [31:0] CODE_SECTION_TLB_ENTRIES =  32'd4,    // Section TLB entries.
54
parameter [31:0] CODE_LPAGE_TLB_ENTRIES   =  32'd8,    // Large page TLB entries.
55
parameter [31:0] CODE_SPAGE_TLB_ENTRIES   =  32'd16,   // Small page TLB entries.
56
parameter [31:0] CODE_CACHE_SIZE          =  32'd1024  // Cache size in bytes.
57
 
58
)(
59 43 Revanth
        // --------------------------------------
60
        // Clock and reset
61
        // --------------------------------------
62
 
63 26 Revanth
        input   wire            i_clk,
64
        input   wire            i_reset,
65
 
66 43 Revanth
        // ---------------------------------------
67 26 Revanth
        // Interrupts. 
68 43 Revanth
        // Both of them are active high and level 
69
        // trigerred.
70
        // ---------------------------------------
71
 
72 26 Revanth
        input   wire            i_irq,
73
        input   wire            i_fiq,
74
 
75
        // ---------------------
76
        // Wishbone interface.
77
        // ---------------------
78 43 Revanth
 
79 26 Revanth
        output  wire            o_wb_cyc,
80
        output  wire            o_wb_stb,
81 43 Revanth
        output  wire            o_wb_stb_nxt,
82
        output  wire            o_wb_cyc_nxt,
83
        output wire  [31:0]     o_wb_adr_nxt,
84 26 Revanth
        output  wire [31:0]     o_wb_adr,
85
        output  wire            o_wb_we,
86
        output wire  [31:0]     o_wb_dat,
87
        output  wire [3:0]      o_wb_sel,
88
        output wire [2:0]       o_wb_cti,
89 29 Revanth
        output wire [1:0]       o_wb_bte,
90 26 Revanth
        input   wire            i_wb_ack,
91
        input   wire [31:0]     i_wb_dat
92
);
93
 
94 29 Revanth
assign o_wb_bte = 2'b00; // Linear Burst.
95
 
96 26 Revanth
localparam COMPRESSED_EN = 1'd1;
97
 
98
`include "zap_defines.vh"
99
`include "zap_localparams.vh"
100
`include "zap_functions.vh"
101
 
102 43 Revanth
wire            wb_cyc, wb_stb, wb_we;
103
wire [3:0]      wb_sel;
104
wire [31:0]     wb_dat, wb_idat;
105
wire [31:0]     wb_adr;
106
wire [2:0]      wb_cti;
107
wire            wb_ack;
108
reg             reset;
109 26 Revanth
 
110 43 Revanth
// Synchronous reset signal flopped.
111 26 Revanth
always @ (posedge i_clk)
112
        reset    <= i_reset;
113
 
114 43 Revanth
wire            cpu_mmu_en;
115
wire [31:0]     cpu_cpsr;
116
wire            cpu_mem_translate;
117 26 Revanth
 
118 43 Revanth
wire [31:0]     cpu_daddr, cpu_daddr_nxt;
119
wire [31:0]     cpu_iaddr, cpu_iaddr_nxt;
120 26 Revanth
 
121 43 Revanth
wire [7:0]      dc_fsr;
122
wire [31:0]     dc_far;
123 26 Revanth
 
124 43 Revanth
wire            cpu_dc_en, cpu_ic_en;
125 26 Revanth
 
126 43 Revanth
wire [1:0]      cpu_sr;
127
wire [7:0]      cpu_pid;
128
wire [31:0]     cpu_baddr, cpu_dac_reg;
129 26 Revanth
 
130 43 Revanth
wire            cpu_dc_inv, cpu_ic_inv;
131
wire            cpu_dc_clean, cpu_ic_clean;
132 26 Revanth
 
133 43 Revanth
wire            dc_inv_done, ic_inv_done, dc_clean_done, ic_clean_done;
134 26 Revanth
 
135 43 Revanth
wire            cpu_dtlb_inv, cpu_itlb_inv;
136 26 Revanth
 
137 43 Revanth
wire            data_ack, data_err, instr_ack, instr_err;
138 26 Revanth
 
139 43 Revanth
wire [31:0]     ic_data, dc_data, cpu_dc_dat;
140
wire            cpu_instr_stb;
141
wire            cpu_dc_we, cpu_dc_stb;
142
wire [3:0]      cpu_dc_sel;
143 26 Revanth
 
144
wire            c_wb_stb;
145
wire            c_wb_cyc;
146
wire            c_wb_wen;
147
wire [3:0]      c_wb_sel;
148
wire [31:0]     c_wb_dat;
149
wire [31:0]     c_wb_adr;
150
wire [2:0]      c_wb_cti;
151
wire            c_wb_ack;
152
 
153
wire            d_wb_stb;
154
wire            d_wb_cyc;
155
wire            d_wb_wen;
156
wire [3:0]      d_wb_sel;
157
wire [31:0]     d_wb_dat;
158
wire [31:0]     d_wb_adr;
159
wire [2:0]      d_wb_cti;
160
wire            d_wb_ack;
161
 
162
zap_core #(
163
        .BP_ENTRIES(BP_ENTRIES),
164
        .FIFO_DEPTH(FIFO_DEPTH)
165
) u_zap_core
166
(
167
// Clock and reset.
168
.i_clk                  (i_clk),
169
.i_reset                (reset),
170
 
171
// Code related.
172
.o_instr_wb_adr         (cpu_iaddr),
173
.o_instr_wb_cyc         (),
174
.o_instr_wb_stb         (cpu_instr_stb),
175
.o_instr_wb_we          (),
176
.o_instr_wb_sel         (),
177
 
178
// Code related.
179
.i_instr_wb_dat         (ic_data),
180
 
181
.i_instr_wb_ack         (instr_ack),
182
.i_instr_wb_err         (instr_err),
183
 
184
// Data related.
185
.o_data_wb_we           (cpu_dc_we),
186
.o_data_wb_adr          (cpu_daddr),
187
.o_data_wb_sel          (cpu_dc_sel),
188
.o_data_wb_dat          (cpu_dc_dat),
189
.o_data_wb_cyc          (),
190
.o_data_wb_stb          (cpu_dc_stb),
191
 
192
// Data related.
193
.i_data_wb_ack          (data_ack),
194
.i_data_wb_err          (data_err),
195
.i_data_wb_dat          (dc_data),
196
 
197
// Interrupts.
198
.i_fiq                  (i_fiq),
199
.i_irq                  (i_irq),
200
 
201
// MMU/cache is present.
202
.o_mem_translate        (cpu_mem_translate),
203
.i_fsr                  ({24'd0,dc_fsr}),
204
.i_far                  (dc_far),
205
.o_dac                  (cpu_dac_reg),
206
.o_baddr                (cpu_baddr),
207
.o_mmu_en               (cpu_mmu_en),
208
.o_sr                   (cpu_sr),
209 43 Revanth
.o_pid                  (cpu_pid),
210 26 Revanth
.o_dcache_inv           (cpu_dc_inv),
211
.o_icache_inv           (cpu_ic_inv),
212
.o_dcache_clean         (cpu_dc_clean),
213
.o_icache_clean         (cpu_ic_clean),
214
.o_dtlb_inv             (cpu_dtlb_inv),
215
.o_itlb_inv             (cpu_itlb_inv),
216
.i_dcache_inv_done      (dc_inv_done),
217
.i_icache_inv_done      (ic_inv_done),
218
.i_dcache_clean_done    (dc_clean_done),
219
.i_icache_clean_done    (ic_clean_done),
220
.o_dcache_en            (cpu_dc_en),
221
.o_icache_en            (cpu_ic_en),
222
 
223
// Data IF nxt.
224 43 Revanth
.o_data_wb_adr_nxt      (cpu_daddr_nxt), // Data addr nxt. Used to drive address of data tag RAM.
225 26 Revanth
.o_data_wb_we_nxt       (),
226
.o_data_wb_cyc_nxt      (),
227
.o_data_wb_stb_nxt      (),
228
.o_data_wb_dat_nxt      (),
229
.o_data_wb_sel_nxt      (),
230
 
231
// Code access prpr.
232
.o_instr_wb_adr_nxt     (cpu_iaddr_nxt), // PC addr nxt. Drives read address of code tag RAM.
233
.o_instr_wb_stb_nxt     (),
234
 
235
.o_cpsr                 (cpu_cpsr)
236
 
237
);
238
 
239 43 Revanth
zap_cache #(
240
        .CACHE_SIZE(DATA_CACHE_SIZE),
241
        .SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
242
        .LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
243
        .SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES))
244 26 Revanth
u_data_cache (
245 43 Revanth
.i_clk                  (i_clk),
246
.i_reset                (reset),
247
.i_address              (cpu_daddr + (cpu_pid << 25)),
248
.i_address_nxt          (cpu_daddr_nxt + (cpu_pid << 25)),
249 26 Revanth
 
250 43 Revanth
.i_rd                   (!cpu_dc_we && cpu_dc_stb),
251
.i_wr                   (cpu_dc_we),
252
.i_ben                  (cpu_dc_sel),
253
.i_dat                  (cpu_dc_dat),
254
.o_dat                  (dc_data),
255
.o_ack                  (data_ack),
256
.o_err                  (data_err),
257 26 Revanth
 
258 43 Revanth
.o_fsr                  (dc_fsr),
259
.o_far                  (dc_far),
260
.i_mmu_en               (cpu_mmu_en),
261
.i_cache_en             (cpu_dc_en),
262 26 Revanth
.i_cache_inv_req        (cpu_dc_inv),
263
.i_cache_clean_req      (cpu_dc_clean),
264
.o_cache_inv_done       (dc_inv_done),
265
.o_cache_clean_done     (dc_clean_done),
266 43 Revanth
.i_cpsr                 (cpu_mem_translate ? USR : cpu_cpsr),
267
.i_sr                   (cpu_sr),
268
.i_baddr                (cpu_baddr),
269
.i_dac_reg              (cpu_dac_reg),
270
.i_tlb_inv              (cpu_dtlb_inv),
271 26 Revanth
 
272 43 Revanth
.o_wb_stb               (),
273
.o_wb_cyc               (),
274
.o_wb_wen               (),
275
.o_wb_sel               (),
276
.o_wb_dat               (),
277
.o_wb_adr               (),
278
.o_wb_cti               (),
279 26 Revanth
 
280 43 Revanth
.i_wb_dat               (wb_dat),
281
.i_wb_ack               (d_wb_ack),
282 26 Revanth
 
283 43 Revanth
.o_wb_stb_nxt           (d_wb_stb),
284
.o_wb_cyc_nxt           (d_wb_cyc),
285
.o_wb_wen_nxt           (d_wb_wen),
286
.o_wb_sel_nxt           (d_wb_sel),
287
.o_wb_dat_nxt           (d_wb_dat),
288
.o_wb_adr_nxt           (d_wb_adr),
289
.o_wb_cti_nxt           (d_wb_cti)
290 26 Revanth
);
291
 
292
zap_cache #(
293
.CACHE_SIZE(CODE_CACHE_SIZE),
294
.SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES),
295
.LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
296
.SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES))
297
u_code_cache (
298
.i_clk              (i_clk),
299
.i_reset            (reset),
300 43 Revanth
.i_address          ((cpu_iaddr     & 32'hFFFF_FFFC) + (cpu_pid << 25)), // Cut off lower 2 bits.
301
.i_address_nxt      ((cpu_iaddr_nxt & 32'hFFFF_FFFC) + (cpu_pid << 25)), // Cut off lower 2 bits.
302 26 Revanth
 
303
.i_rd              (cpu_instr_stb),
304
.i_wr              (1'd0),
305
.i_ben             (4'b1111),
306
.i_dat             (32'd0),
307
.o_dat             (ic_data),
308
.o_ack             (instr_ack),
309
.o_err             (instr_err),
310
 
311 43 Revanth
.o_fsr             (),
312
.o_far             (),
313 26 Revanth
.i_mmu_en          (cpu_mmu_en),
314
.i_cache_en        (cpu_ic_en),
315
.i_cache_inv_req   (cpu_ic_inv),
316
.i_cache_clean_req (cpu_ic_clean),
317
.o_cache_inv_done  (ic_inv_done),
318
.o_cache_clean_done(ic_clean_done),
319
.i_cpsr         (cpu_mem_translate ? USR : cpu_cpsr),
320
.i_sr           (cpu_sr),
321
.i_baddr        (cpu_baddr),
322
.i_dac_reg      (cpu_dac_reg),
323
.i_tlb_inv      (cpu_itlb_inv),
324
 
325
.o_wb_stb       (),
326
.o_wb_cyc       (),
327
.o_wb_wen       (),
328
.o_wb_sel       (),
329
.o_wb_dat       (),
330
.o_wb_adr       (),
331
.o_wb_cti       (),
332
 
333
.i_wb_dat       (wb_dat),
334
.i_wb_ack       (c_wb_ack),
335
 
336
.o_wb_stb_nxt   (c_wb_stb),
337
.o_wb_cyc_nxt   (c_wb_cyc),
338
.o_wb_wen_nxt   (c_wb_wen),
339
.o_wb_sel_nxt   (c_wb_sel),
340
.o_wb_dat_nxt   (c_wb_dat),
341
.o_wb_adr_nxt   (c_wb_adr),
342
.o_wb_cti_nxt   (c_wb_cti)
343
);
344
 
345
zap_wb_merger u_zap_wb_merger (
346
 
347
.i_clk(i_clk),
348
.i_reset(i_reset),
349
 
350
.i_c_wb_stb(c_wb_stb),
351
.i_c_wb_cyc(c_wb_cyc),
352
.i_c_wb_wen(c_wb_wen),
353
.i_c_wb_sel(c_wb_sel),
354
.i_c_wb_dat(c_wb_dat),
355
.i_c_wb_adr(c_wb_adr),
356
.i_c_wb_cti(c_wb_cti),
357
.o_c_wb_ack(c_wb_ack),
358
 
359
.i_d_wb_stb(d_wb_stb),
360
.i_d_wb_cyc(d_wb_cyc),
361
.i_d_wb_wen(d_wb_wen),
362
.i_d_wb_sel(d_wb_sel),
363
.i_d_wb_dat(d_wb_dat),
364
.i_d_wb_adr(d_wb_adr),
365
.i_d_wb_cti(d_wb_cti),
366
.o_d_wb_ack(d_wb_ack),
367
 
368
.o_wb_cyc(wb_cyc),
369
.o_wb_stb(wb_stb),
370
.o_wb_wen(wb_we),
371
.o_wb_sel(wb_sel),
372
.o_wb_dat(wb_idat),
373
.o_wb_adr(wb_adr),
374
.o_wb_cti(wb_cti),
375
.i_wb_ack(wb_ack)
376
 
377
);
378
 
379
zap_wb_adapter #(.DEPTH(STORE_BUFFER_DEPTH)) u_zap_wb_adapter (
380
.i_clk(i_clk),
381
.i_reset(i_reset),
382
 
383
.I_WB_CYC(wb_cyc),
384
.I_WB_STB(wb_stb),
385
.I_WB_WE(wb_we),
386
.I_WB_DAT(wb_idat),
387
.I_WB_SEL(wb_sel),
388
.I_WB_CTI(wb_cti),
389
.O_WB_ACK(wb_ack),
390
.O_WB_DAT(wb_dat),
391
.I_WB_ADR(wb_adr),
392
 
393
.o_wb_cyc(o_wb_cyc),
394
.o_wb_stb(o_wb_stb),
395
.o_wb_we(o_wb_we),
396
.o_wb_sel(o_wb_sel),
397
.o_wb_dat(o_wb_dat),
398
.o_wb_adr(o_wb_adr),
399
.o_wb_cti(o_wb_cti),
400
.i_wb_dat(i_wb_dat),
401 43 Revanth
.i_wb_ack(i_wb_ack),
402
 
403
// CYC and STB nxt.
404
.o_wb_stb_nxt (o_wb_stb_nxt),
405
.o_wb_cyc_nxt (o_wb_cyc_nxt),
406
.o_wb_adr_nxt (o_wb_adr_nxt),
407
.o_wb_sel_nxt (),
408
.o_wb_dat_nxt (),
409
.o_wb_we_nxt  ()
410 26 Revanth
);
411
 
412
endmodule // zap_top.v
413 43 Revanth
 
414 26 Revanth
`default_nettype wire

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