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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_wb_adapter.v] - Blame information for rev 51

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1 26 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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// --                                                                         --
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// --  Implements store FIFO. Serves as a bridge between the processor core & --
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// --  the memory interface.                                                  --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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module zap_wb_adapter #(parameter DEPTH = 32) (
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// Clock.
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input wire                   i_clk,
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input wire                   i_reset,
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// Processor Wishbone interface. These come from the Wishbone registered
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// interface.
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input wire                   I_WB_CYC,
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input wire                   I_WB_STB,
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input wire [3:0]             I_WB_SEL,
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input wire [2:0]             I_WB_CTI,
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input wire [31:0]            I_WB_ADR,
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input wire [31:0]            I_WB_DAT,
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input wire                   I_WB_WE,
46 29 Revanth
output reg [31:0]            O_WB_DAT,
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output reg                   O_WB_ACK,
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// Wishbone interface.
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output reg                   o_wb_cyc,
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output reg                   o_wb_stb,
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output wire     [31:0]       o_wb_dat,
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output wire     [31:0]       o_wb_adr,
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output wire     [3:0]        o_wb_sel,
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output wire     [2:0]        o_wb_cti,
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output wire                  o_wb_we,
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input wire      [31:0]       i_wb_dat,
58 43 Revanth
input wire                   i_wb_ack,
59 26 Revanth
 
60 43 Revanth
output reg                   o_wb_stb_nxt,
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output reg                   o_wb_cyc_nxt,
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output wire     [3:0]        o_wb_sel_nxt,
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output wire     [31:0]       o_wb_dat_nxt,
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output wire     [31:0]       o_wb_adr_nxt,
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output wire                  o_wb_we_nxt
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67 26 Revanth
);
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`include "zap_defines.vh"
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`include "zap_localparams.vh"
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reg  fsm_write_en;
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reg  [69:0] fsm_write_data;
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wire w_eob;
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wire w_full;
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wire w_eob_nxt;
77 26 Revanth
 
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assign    o_wb_cti = {w_eob, 1'd1, w_eob};
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wire w_emp;
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// {SEL, DATA, ADDR, EOB, WEN} = 4 + 64 + 1 + 1 = 70 bit.
83 43 Revanth
zap_sync_fifo #(.WIDTH(70), .DEPTH(DEPTH), .FWFT(1'd0), .PROVIDE_NXT_DATA(1)) U_STORE_FIFO (
84 26 Revanth
.i_clk          (i_clk),
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.i_reset        (i_reset),
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.i_ack          ((i_wb_ack && o_wb_stb) || emp_ff),
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.i_wr_en        (fsm_write_en),
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.i_data         (fsm_write_data),
89 43 Revanth
.o_data         ({o_wb_sel,     o_wb_dat,     o_wb_adr,     w_eob,     o_wb_we}),
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.o_data_nxt     ({o_wb_sel_nxt, o_wb_dat_nxt, o_wb_adr_nxt, w_eob_nxt, o_wb_we_nxt}),
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.o_empty        (w_emp),
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.o_full         (w_full),
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.o_empty_n      (),
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.o_full_n       (),
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.o_full_n_nxt   ()
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);
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98 43 Revanth
reg emp_nxt;
99 26 Revanth
reg emp_ff;
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reg [31:0] ctr_nxt, ctr_ff;
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reg [31:0] dff, dnxt;
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reg ack;        // ACK write channel.
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reg ack_ff;     // Read channel.
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localparam IDLE = 0;
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localparam PRPR_RD_SINGLE = 1;
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localparam PRPR_RD_BURST = 2;
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localparam WRITE = 3;
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localparam WAIT1 = 5;
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localparam WAIT2 = 6;
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localparam NUMBER_OF_STATES = 7;
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reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
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115 43 Revanth
// FIFO pipeline register and nxt state logic.
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always @ (*)
117 26 Revanth
begin
118 43 Revanth
        emp_nxt      = emp_ff;
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        o_wb_stb_nxt = o_wb_stb;
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        o_wb_cyc_nxt = o_wb_cyc;
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        if ( i_reset )
123 26 Revanth
        begin
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                emp_nxt      = 1'd1;
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                o_wb_stb_nxt = 1'd0;
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                o_wb_cyc_nxt = 1'd0;
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        end
128 43 Revanth
        else if ( emp_ff || (i_wb_ack && o_wb_stb) )
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        begin
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                emp_nxt      = w_emp;
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                o_wb_stb_nxt = !w_emp;
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                o_wb_cyc_nxt = !w_emp;
133 26 Revanth
        end
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end
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136 43 Revanth
always @ (posedge i_clk)
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begin
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        emp_ff   <= emp_nxt;
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        o_wb_stb <= o_wb_stb_nxt;
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        o_wb_cyc <= o_wb_cyc_nxt;
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end
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143 26 Revanth
// Flip flop clocking block.
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always @ (posedge i_clk)
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begin
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        if ( i_reset )
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        begin
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                state_ff <= IDLE;
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                ctr_ff   <= 0;
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                dff      <= 0;
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        end
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        else
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        begin
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                state_ff <= state_nxt;
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                ctr_ff   <= ctr_nxt;
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                dff      <= dnxt;
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        end
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end
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// Reads from the Wishbone bus are flopped.
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always @ (posedge i_clk)
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begin
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        if ( i_reset )
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        begin
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                ack_ff  <= 1'd0;
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        end
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        else if ( !o_wb_we && o_wb_cyc && o_wb_stb && i_wb_ack )
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        begin
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                ack_ff   <= 1'd1;
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                O_WB_DAT <= i_wb_dat;
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        end
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        else
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        begin
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                ack_ff <= 1'd0;
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        end
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end
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localparam BURST_LEN = 4;
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// OR from flop and mealy FSM output.
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always @* O_WB_ACK = ack_ff | ack;
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// State machine.
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always @*
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begin
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        state_nxt = state_ff;
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        ctr_nxt = ctr_ff;
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        ack = 0;
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        dnxt = dff;
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        fsm_write_en = 0;
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        fsm_write_data = 0;
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        case(state_ff)
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        IDLE:
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        begin
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                ctr_nxt = 0;
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                dnxt = 0;
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                if ( I_WB_STB && I_WB_WE && !o_wb_stb ) // Wishbone write request 
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                begin
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                        // Simply buffer stores into the FIFO.
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                        state_nxt = WRITE;
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                end
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                else if ( I_WB_STB && !I_WB_WE && !o_wb_stb ) // Wishbone read request
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                begin
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                        // Write a set of reads into the FIFO.
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                        if ( I_WB_CTI == CTI_BURST ) // Burst of 4 words. Each word is 4 byte.
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                        begin
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                                state_nxt = PRPR_RD_BURST;
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                        end
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                        else // Single.
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                        begin
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                                state_nxt = PRPR_RD_SINGLE;
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                        end
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                end
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        end
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        PRPR_RD_SINGLE: // Write a single read token into the FIFO.
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        begin
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                if ( !w_full )
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                begin
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                        state_nxt = WAIT1;
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                        fsm_write_en = 1'd1;
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                        fsm_write_data = {      I_WB_SEL,
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                                                I_WB_DAT,
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                                                I_WB_ADR,
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                                                I_WB_CTI != CTI_BURST ? 1'd1 : 1'd0,
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                                                1'd0};
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                end
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        end
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        PRPR_RD_BURST: // Write burst read requests into the FIFO.
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        begin
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                if ( O_WB_ACK )
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                begin
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                        dnxt = dff + 1'd1;
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                end
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                if ( ctr_ff == BURST_LEN * 4 )
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                begin
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                        ctr_nxt = 0;
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                        state_nxt = WAIT2; // FIFO prep done.
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                end
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                else if ( !w_full )
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                begin: blk1
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                        reg [31:0] adr;
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                        adr = {I_WB_ADR[31:4], 4'd0} + ctr_ff; // Ignore lower 4-bits.
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                        fsm_write_en = 1'd1;
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                        fsm_write_data = {      I_WB_SEL,
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                                                I_WB_DAT,
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                                                adr,
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                                                ctr_ff == 12 ? 1'd1 : 1'd0,
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                                                1'd0 };
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                        ctr_nxt = ctr_ff + 4;
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                end
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        end
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        WRITE:
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        begin
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                // As long as requests exist, write them out to the FIFO.
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                if ( I_WB_STB && I_WB_WE )
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                begin
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                        if ( !w_full )
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                        begin
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                                fsm_write_en    = 1'd1;
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                                fsm_write_data  =  {I_WB_SEL, I_WB_DAT, I_WB_ADR, I_WB_CTI != CTI_BURST ? 1'd1 : 1'd0, 1'd1};
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                                ack = 1'd1;
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                        end
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                end
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                else // Writes done!
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                begin
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                        state_nxt = IDLE;
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                end
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        end
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        WAIT1: // Wait for single read to complete.
278
        begin
279
                if ( O_WB_ACK )
280
                begin
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                        state_nxt = IDLE;
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                end
283
        end
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        WAIT2: // Wait for burst reads to complete.
286
        begin
287
                if ( O_WB_ACK )
288
                begin
289
                        dnxt = dff + 1;
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                end
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292
                if ( dff == BURST_LEN && !o_wb_stb )
293
                begin
294
                        state_nxt = IDLE;
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                end
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        end
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298
        endcase
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end
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endmodule
302 51 Revanth
 
303 26 Revanth
`default_nettype wire
304 51 Revanth
 
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// ----------------------------------------------------------------------------
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// EOF
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// ----------------------------------------------------------------------------

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