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1 43 Revanth
Note: This Changes file is being maintained since 25.5.2001.
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29.07.2002
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~~~~~~~~~~
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Reverted to have uart_defines.v file to be included in the verilog
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files. It seems that it's been a bad idea in the first place.
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22.07.2002
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~~~~~~~~~~
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Notice that this file hasn't been updated for a while so not all changed are present.
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Bug Fixes:
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 * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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  Problem reported by Kenny.Tung.
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 * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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Improvements:
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 * Made FIFO's as general inferrable memory where possible.
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 So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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 This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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 * Added optional baudrate output (baud_o).
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 This is identical to BAUDOUT* signal on 16550 chip.
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 It outputs 16xbit_clock_rate - the divided clock.
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 It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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Note:
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 The uart_defines.v file is no longer included in the source files.
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 So keep this in mind when doing simulation. Add it manually.
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 I've done this, so that you could you your own define files for
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 different configurations. I need this for the IrDA core I develop.
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 You can just uncomment the `includes if you want the old behaviour.
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 The uart_fifo.v file is no longer used. Intead uart_rfifo.v and uart_tfifo.v
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 file are now present. Also raminfr.v in the new inferred ram module.
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 Check the new core and I hope you'll like it.
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10.08.2001
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~~~~~~~~~~
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* Modified naming of top signals and defines to be unique and easy to integrate
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* Changed the directory structure of the core to new structure as described in OpenCores
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  coding guidelines. !!!
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* Fixed (I hope) the detection of break condition
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* Added top level parameters for data width and address line width
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23.06.2001
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* With the help of Bob Kirstein another two bugs were fixed:
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   1. Trasmitter was sending stop bit two 16xclock cycle slonger than needed.
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   2. Receiver was losing 1 16xclock cycle on each character and went out of sync.
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* Major change:
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    I have modified the divisor latch register to be 16-bit long instead of 32 as I thought was
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    necessary for higher speed systems. Thanks to Rick Wright for pointing this out.
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    So now, DL3 and DL4 register bytes are not used.
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    Documentation is updated to follow this change.
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* Note that more than 1 stop bit in a byte i snot implemented.
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2.05.2001
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~~~~~~~~~
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* Fixed transmitter and receiver - the start and the stop bits were sent and received complemented.
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  Big thanks go to Bob Kirstein for pointing this out to me.
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31.05.2001
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~~~~~~~~~~
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* Minor changes in register reading code
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* Changed FCR to be 2 bits wide (reset bits are not needed) and instead enabled the rx_reset and tx_reset
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   signals which I forgot to implement.
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* Changed defines for FCR.
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* Cleaned ports that were not connected in top-level.
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* Changed the code to have only one FIFO module instead of two to overcome versioning problem on the cost of
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   some additional gate count. UART_RX_FIFO was modified a little and renamed to UART_FIFO.
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* UART_RX_FIFO.v and UART_TX_FIFO.v files removed from the project.
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* Changes to receiver and transmitter modules concerning FIFO handling.
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* Commented out `include "UART_defines" in all files but UART_top.v and test bench.
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* Modified test bench a little for a little better check.
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29.05.2001
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~~~~~~~~~~
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* Fixed: Line Control Register block didn't have wb_rst_i in its sensitivity list
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* Fixed: Modem Status Register block didn't have wb_rst_i in its sensitivity list and didn't set reset value
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* Fixed rf_pop, lsr_mask, msi_reset and threi_clear not being synthesizable in release 1.7. (Thanks
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        to Pavel Korenski for pointing this to me)
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27.05.2001
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~~~~~~~~~~
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Thanks to Rick Wright for pointing me many of my bugs.
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* Fixed the rf_pop and lsr_mask flags not being deasserted.
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* Fixed Time-Out interrupt not being masked by bit 0 in IER
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* Fixed interrupt logic not being masked by IER
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* Fixed bit 0 (interrupt pending) of IIR being set incorrectly
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* Fixed Modem Status Register bits 3:0 handling (didn't work as should have)
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* Fixed modem status interrupt to be related to bits [3:0] (deltas) instead of the bits 7:4 of MSR.
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   This way the interrupt is cleared upon reading from the MSR.
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* Fixed THRE interrupt not being reset by reading IIR
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* Changed Receiver and Transmitter FIFO, so that they do not use the FIFO_inc.v file because of problems
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  with #include command.
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* Removed FIFO_inc.v from CVS tree.
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* Updated specifications .pdf file
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