OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [raminfr.v] - Blame information for rev 43

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 43 Revanth
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  raminfr.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the "UART 16550 compatible" project    ////
7
////  http://www.opencores.org/cores/uart16550/                   ////
8
////                                                              ////
9
////  Documentation related to this project:                      ////
10
////  - http://www.opencores.org/cores/uart16550/                 ////
11
////                                                              ////
12
////  Projects compatibility:                                     ////
13
////  - WISHBONE                                                  ////
14
////  RS232 Protocol                                              ////
15
////  16550D uart (mostly supported)                              ////
16
////                                                              ////
17
////  Overview (main Features):                                   ////
18
////  Inferrable Distributed RAM for FIFOs                        ////
19
////                                                              ////
20
////  Known problems (limits):                                    ////
21
////  None                .                                       ////
22
////                                                              ////
23
////  To Do:                                                      ////
24
////  Nothing so far.                                             ////
25
////                                                              ////
26
////  Author(s):                                                  ////
27
////      - gorban@opencores.org                                  ////
28
////      - Jacob Gorban                                          ////
29
////                                                              ////
30
////  Created:        2002/07/22                                  ////
31
////  Last Updated:   2002/07/22                                  ////
32
////                  (See log for the revision history)          ////
33
////                                                              ////
34
//// Modified for use in the ZAP project by Revanth Kamaraj       ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
////                                                              ////
38
//// Copyright (C) 2000, 2001 Authors                             ////
39
////                                                              ////
40
//// This source file may be used and distributed without         ////
41
//// restriction provided that this copyright statement is not    ////
42
//// removed from the file and that any derivative work contains  ////
43
//// the original copyright notice and the associated disclaimer. ////
44
////                                                              ////
45
//// This source file is free software; you can redistribute it   ////
46
//// and/or modify it under the terms of the GNU Lesser General   ////
47
//// Public License as published by the Free Software Foundation; ////
48
//// either version 2.1 of the License, or (at your option) any   ////
49
//// later version.                                               ////
50
////                                                              ////
51
//// This source is distributed in the hope that it will be       ////
52
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55
//// details.                                                     ////
56
////                                                              ////
57
//// You should have received a copy of the GNU Lesser General    ////
58
//// Public License along with this source; if not, download it   ////
59
//// from http://www.opencores.org/lgpl.shtml                     ////
60
////                                                              ////
61
//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65
// $Log: not supported by cvs2svn $
66
// Revision 1.1  2002/07/22 23:02:23  gorban
67
// Bug Fixes:
68
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
69
//   Problem reported by Kenny.Tung.
70
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
71
//
72
// Improvements:
73
//  * Made FIFO's as general inferrable memory where possible.
74
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
75
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
76
//
77
//  * Added optional baudrate output (baud_o).
78
//  This is identical to BAUDOUT* signal on 16550 chip.
79
//  It outputs 16xbit_clock_rate - the divided clock.
80
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
81
//
82
 
83
//Following is the Verilog code for a dual-port RAM with asynchronous read. 
84
module raminfr
85
        (clk, we, a, dpra, di, dpo);
86
 
87
parameter addr_width = 4;
88
parameter data_width = 8;
89
parameter depth = 16;
90
 
91
input clk;
92
input we;
93
input  [addr_width-1:0] a;
94
input  [addr_width-1:0] dpra;
95
input  [data_width-1:0] di;
96
//output [data_width-1:0] spo;   
97
output [data_width-1:0] dpo;
98
reg    [data_width-1:0] ram [depth-1:0];
99
 
100
wire [data_width-1:0] dpo;
101
wire  [data_width-1:0] di;
102
wire  [addr_width-1:0] a;
103
wire  [addr_width-1:0] dpra;
104
 
105
  always @(posedge clk) begin
106
    if (we)
107
      ram[a] <= di;
108
  end
109
//  assign spo = ram[a];   
110
  assign dpo = ram[dpra];
111
endmodule
112
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.