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[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [uart_defines.v] - Blame information for rev 43

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1 43 Revanth
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  uart_defines.v                                              ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  Defines of the Core                                         ////
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////                                                              ////
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////  Known problems (limits):                                    ////
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////  None                                                        ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Nothing.                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////      - Igor Mohor (igorm@opencores.org)                      ////
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////                                                              ////
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////  Created:        2001/05/12                                  ////
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////  Last Updated:   2001/05/17                                  ////
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////                  (See log for the revision history)          ////
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///// Modified for use in the ZAP project by Revanth Kamaraj      ////
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///                                                               ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.13  2003/06/11 16:37:47  gorban
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// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
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//
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// Revision 1.12  2002/07/22 23:02:23  gorban
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// Bug Fixes:
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//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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//   Problem reported by Kenny.Tung.
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//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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//  * Made FIFO's as general inferrable memory where possible.
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//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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//  * Added optional baudrate output (baud_o).
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//  This is identical to BAUDOUT* signal on 16550 chip.
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//  It outputs 16xbit_clock_rate - the divided clock.
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//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.10  2001/12/11 08:55:40  mohor
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// Scratch register define added.
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//
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// Revision 1.9  2001/12/03 21:44:29  gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.8  2001/11/26 21:38:54  gorban
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// Lots of fixes:
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// Break condition wasn't handled correctly at all.
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// LSR bits could lose their values.
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// LSR value after reset was wrong.
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// Timing of THRE interrupt signal corrected.
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// LSR bit 0 timing corrected.
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//
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// Revision 1.7  2001/08/24 21:01:12  mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.6  2001/08/23 16:05:05  mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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// Revision 1.5  2001/05/31 20:08:01  gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.4  2001/05/21 19:12:02  gorban
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// Corrected some Linter messages.
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//
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// Revision 1.3  2001/05/17 18:34:18  gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0  2001-05-17 21:27:11+02  jacob
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// Initial revision
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//
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//
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// remove comments to restore to use the new version with 8 data bit interface
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// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
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// also, in 8-bit version there'll be no debugging features included
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// CAUTION: doesn't work with current version of OR1200
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//`define DATA_BUS_WIDTH_8
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`ifdef DATA_BUS_WIDTH_8
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 `define UART_ADDR_WIDTH 3
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 `define UART_DATA_WIDTH 8
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`else
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 `define UART_ADDR_WIDTH 5
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 `define UART_DATA_WIDTH 32
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`endif
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// Uncomment this if you want your UART to have
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// 16xBaudrate output port.
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// If defined, the enable signal will be used to drive baudrate_o signal
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// It's frequency is 16xbaudrate
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// `define UART_HAS_BAUDRATE_OUTPUT
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// Register addresses
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`define UART_REG_RB     `UART_ADDR_WIDTH'd0     // receiver buffer
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`define UART_REG_TR  `UART_ADDR_WIDTH'd0        // transmitter
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`define UART_REG_IE     `UART_ADDR_WIDTH'd1     // Interrupt enable
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`define UART_REG_II  `UART_ADDR_WIDTH'd2        // Interrupt identification
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`define UART_REG_FC  `UART_ADDR_WIDTH'd2        // FIFO control
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`define UART_REG_LC     `UART_ADDR_WIDTH'd3     // Line Control
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`define UART_REG_MC     `UART_ADDR_WIDTH'd4     // Modem control
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`define UART_REG_LS  `UART_ADDR_WIDTH'd5        // Line status
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`define UART_REG_MS  `UART_ADDR_WIDTH'd6        // Modem status
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`define UART_REG_SR  `UART_ADDR_WIDTH'd7        // Scratch register
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`define UART_REG_DL1    `UART_ADDR_WIDTH'd0     // Divisor latch bytes (1-2)
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`define UART_REG_DL2    `UART_ADDR_WIDTH'd1
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// Interrupt Enable register bits
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`define UART_IE_RDA     0        // Received Data available interrupt
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`define UART_IE_THRE    1       // Transmitter Holding Register empty interrupt
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`define UART_IE_RLS     2       // Receiver Line Status Interrupt
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`define UART_IE_MS      3       // Modem Status Interrupt
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// Interrupt Identification register bits
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`define UART_II_IP      0        // Interrupt pending when 0
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`define UART_II_II      3:1     // Interrupt identification
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// Interrupt identification values for bits 3:1
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`define UART_II_RLS     3'b011  // Receiver Line Status
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`define UART_II_RDA     3'b010  // Receiver Data available
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`define UART_II_TI      3'b110  // Timeout Indication
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`define UART_II_THRE    3'b001  // Transmitter Holding Register empty
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`define UART_II_MS      3'b000  // Modem Status
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// FIFO Control Register bits
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`define UART_FC_TL      1:0      // Trigger level
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// FIFO trigger level values
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`define UART_FC_1               2'b00
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`define UART_FC_4               2'b01
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`define UART_FC_8               2'b10
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`define UART_FC_14      2'b11
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// Line Control register bits
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`define UART_LC_BITS    1:0      // bits in character
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`define UART_LC_SB      2       // stop bits
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`define UART_LC_PE      3       // parity enable
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`define UART_LC_EP      4       // even parity
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`define UART_LC_SP      5       // stick parity
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`define UART_LC_BC      6       // Break control
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`define UART_LC_DL      7       // Divisor Latch access bit
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// Modem Control register bits
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`define UART_MC_DTR     0
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`define UART_MC_RTS     1
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`define UART_MC_OUT1    2
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`define UART_MC_OUT2    3
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`define UART_MC_LB      4       // Loopback mode
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// Line Status Register bits
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`define UART_LS_DR      0        // Data ready
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`define UART_LS_OE      1       // Overrun Error
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`define UART_LS_PE      2       // Parity Error
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`define UART_LS_FE      3       // Framing Error
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`define UART_LS_BI      4       // Break interrupt
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`define UART_LS_TFE     5       // Transmit FIFO is empty
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`define UART_LS_TE      6       // Transmitter Empty indicator
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`define UART_LS_EI      7       // Error indicator
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// Modem Status Register bits
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`define UART_MS_DCTS    0        // Delta signals
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`define UART_MS_DDSR    1
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`define UART_MS_TERI    2
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`define UART_MS_DDCD    3
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`define UART_MS_CCTS    4       // Complement signals
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`define UART_MS_CDSR    5
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`define UART_MS_CRI     6
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`define UART_MS_CDCD    7
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// FIFO parameter defines
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_POINTER_W     4
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`define UART_FIFO_COUNTER_W     5
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// receiver fifo has width 11 because it has break, parity and framing error bits
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`define UART_FIFO_REC_WIDTH  11
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`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
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`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
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`define FAST_TEST   1           // 64/1024 packets are sent
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// Added by Revanth to support LITTLE_ENDIAN mode of operation.
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`define LITLE_ENDIAN
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