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[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [uart_receiver.v] - Blame information for rev 43

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1 43 Revanth
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  uart_receiver.v                                             ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the "UART 16550 compatible" project    ////
7
////  http://www.opencores.org/cores/uart16550/                   ////
8
////                                                              ////
9
////  Documentation related to this project:                      ////
10
////  - http://www.opencores.org/cores/uart16550/                 ////
11
////                                                              ////
12
////  Projects compatibility:                                     ////
13
////  - WISHBONE                                                  ////
14
////  RS232 Protocol                                              ////
15
////  16550D uart (mostly supported)                              ////
16
////                                                              ////
17
////  Overview (main Features):                                   ////
18
////  UART core receiver logic                                    ////
19
////                                                              ////
20
////  Known problems (limits):                                    ////
21
////  None known                                                  ////
22
////                                                              ////
23
////  To Do:                                                      ////
24
////  Thourough testing.                                          ////
25
////                                                              ////
26
////  Author(s):                                                  ////
27
////      - gorban@opencores.org                                  ////
28
////      - Jacob Gorban                                          ////
29
////      - Igor Mohor (igorm@opencores.org)                      ////
30
////                                                              ////
31
////  Created:        2001/05/12                                  ////
32
////  Last Updated:   2001/05/17                                  ////
33
////                  (See log for the revision history)          ////
34
////                                                              ////
35
//// Modified for use in the ZAP project by Revanth Kamaraj       ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
////                                                              ////
39
//// Copyright (C) 2000, 2001 Authors                             ////
40
////                                                              ////
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//// This source file may be used and distributed without         ////
42
//// restriction provided that this copyright statement is not    ////
43
//// removed from the file and that any derivative work contains  ////
44
//// the original copyright notice and the associated disclaimer. ////
45
////                                                              ////
46
//// This source file is free software; you can redistribute it   ////
47
//// and/or modify it under the terms of the GNU Lesser General   ////
48
//// Public License as published by the Free Software Foundation; ////
49
//// either version 2.1 of the License, or (at your option) any   ////
50
//// later version.                                               ////
51
////                                                              ////
52
//// This source is distributed in the hope that it will be       ////
53
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
54
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
55
//// PURPOSE.  See the GNU Lesser General Public License for more ////
56
//// details.                                                     ////
57
////                                                              ////
58
//// You should have received a copy of the GNU Lesser General    ////
59
//// Public License along with this source; if not, download it   ////
60
//// from http://www.opencores.org/lgpl.shtml                     ////
61
////                                                              ////
62
//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66
// $Log: not supported by cvs2svn $
67
// Revision 1.29  2002/07/29 21:16:18  gorban
68
// The uart_defines.v file is included again in sources.
69
//
70
// Revision 1.28  2002/07/22 23:02:23  gorban
71
// Bug Fixes:
72
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
73
//   Problem reported by Kenny.Tung.
74
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
75
//
76
// Improvements:
77
//  * Made FIFO's as general inferrable memory where possible.
78
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
79
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
80
//
81
//  * Added optional baudrate output (baud_o).
82
//  This is identical to BAUDOUT* signal on 16550 chip.
83
//  It outputs 16xbit_clock_rate - the divided clock.
84
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
85
//
86
// Revision 1.27  2001/12/30 20:39:13  mohor
87
// More than one character was stored in case of break. End of the break
88
// was not detected correctly.
89
//
90
// Revision 1.26  2001/12/20 13:28:27  mohor
91
// Missing declaration of rf_push_q fixed.
92
//
93
// Revision 1.25  2001/12/20 13:25:46  mohor
94
// rx push changed to be only one cycle wide.
95
//
96
// Revision 1.24  2001/12/19 08:03:34  mohor
97
// Warnings cleared.
98
//
99
// Revision 1.23  2001/12/19 07:33:54  mohor
100
// Synplicity was having troubles with the comment.
101
//
102
// Revision 1.22  2001/12/17 14:46:48  mohor
103
// overrun signal was moved to separate block because many sequential lsr
104
// reads were preventing data from being written to rx fifo.
105
// underrun signal was not used and was removed from the project.
106
//
107
// Revision 1.21  2001/12/13 10:31:16  mohor
108
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
109
// timeout counter).
110
//
111
// Revision 1.20  2001/12/10 19:52:05  gorban
112
// Igor fixed break condition bugs
113
//
114
// Revision 1.19  2001/12/06 14:51:04  gorban
115
// Bug in LSR[0] is fixed.
116
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
117
//
118
// Revision 1.18  2001/12/03 21:44:29  gorban
119
// Updated specification documentation.
120
// Added full 32-bit data bus interface, now as default.
121
// Address is 5-bit wide in 32-bit data bus mode.
122
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
123
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
124
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
125
// My small test bench is modified to work with 32-bit mode.
126
//
127
// Revision 1.17  2001/11/28 19:36:39  gorban
128
// Fixed: timeout and break didn't pay attention to current data format when counting time
129
//
130
// Revision 1.16  2001/11/27 22:17:09  gorban
131
// Fixed bug that prevented synthesis in uart_receiver.v
132
//
133
// Revision 1.15  2001/11/26 21:38:54  gorban
134
// Lots of fixes:
135
// Break condition wasn't handled correctly at all.
136
// LSR bits could lose their values.
137
// LSR value after reset was wrong.
138
// Timing of THRE interrupt signal corrected.
139
// LSR bit 0 timing corrected.
140
//
141
// Revision 1.14  2001/11/10 12:43:21  gorban
142
// Logic Synthesis bugs fixed. Some other minor changes
143
//
144
// Revision 1.13  2001/11/08 14:54:23  mohor
145
// Comments in Slovene language deleted, few small fixes for better work of
146
// old tools. IRQs need to be fix.
147
//
148
// Revision 1.12  2001/11/07 17:51:52  gorban
149
// Heavily rewritten interrupt and LSR subsystems.
150
// Many bugs hopefully squashed.
151
//
152
// Revision 1.11  2001/10/31 15:19:22  gorban
153
// Fixes to break and timeout conditions
154
//
155
// Revision 1.10  2001/10/20 09:58:40  gorban
156
// Small synopsis fixes
157
//
158
// Revision 1.9  2001/08/24 21:01:12  mohor
159
// Things connected to parity changed.
160
// Clock devider changed.
161
//
162
// Revision 1.8  2001/08/23 16:05:05  mohor
163
// Stop bit bug fixed.
164
// Parity bug fixed.
165
// WISHBONE read cycle bug fixed,
166
// OE indicator (Overrun Error) bug fixed.
167
// PE indicator (Parity Error) bug fixed.
168
// Register read bug fixed.
169
//
170
// Revision 1.6  2001/06/23 11:21:48  gorban
171
// DL made 16-bit long. Fixed transmission/reception bugs.
172
//
173
// Revision 1.5  2001/06/02 14:28:14  gorban
174
// Fixed receiver and transmitter. Major bug fixed.
175
//
176
// Revision 1.4  2001/05/31 20:08:01  gorban
177
// FIFO changes and other corrections.
178
//
179
// Revision 1.3  2001/05/27 17:37:49  gorban
180
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
181
//
182
// Revision 1.2  2001/05/21 19:12:02  gorban
183
// Corrected some Linter messages.
184
//
185
// Revision 1.1  2001/05/17 18:34:18  gorban
186
// First 'stable' release. Should be sythesizable now. Also added new header.
187
//
188
// Revision 1.0  2001-05-17 21:27:11+02  jacob
189
// Initial revision
190
//
191
//
192
//// Modified for use in the ZAP project by Revanth Kamaraj       ////
193
 
194
 
195
`include "uart_defines.v"
196
 
197
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
198
        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
199
 
200
input                           clk;
201
input                           wb_rst_i;
202
input   [7:0]    lcr;
203
input                           rf_pop;
204
input                           srx_pad_i;
205
input                           enable;
206
input                           rx_reset;
207
input       lsr_mask;
208
 
209
output  [9:0]                    counter_t;
210
output  [`UART_FIFO_COUNTER_W-1:0]       rf_count;
211
output  [`UART_FIFO_REC_WIDTH-1:0]       rf_data_out;
212
output                          rf_overrun;
213
output                          rf_error_bit;
214
output [3:0]             rstate;
215
output                          rf_push_pulse;
216
 
217
reg     [3:0]    rstate;
218
reg     [3:0]    rcounter16;
219
reg     [2:0]    rbit_counter;
220
reg     [7:0]    rshift;                 // receiver shift register
221
reg             rparity;                // received parity
222
reg             rparity_error;
223
reg             rframing_error;         // framing error flag
224
reg             rbit_in;
225
reg             rparity_xor;
226
reg     [7:0]    counter_b;      // counts the 0 (low) signals
227
reg   rf_push_q;
228
 
229
// RX FIFO signals
230
reg     [`UART_FIFO_REC_WIDTH-1:0]       rf_data_in;
231
wire    [`UART_FIFO_REC_WIDTH-1:0]       rf_data_out;
232
wire      rf_push_pulse;
233
reg                             rf_push;
234
wire                            rf_pop;
235
wire                            rf_overrun;
236
wire    [`UART_FIFO_COUNTER_W-1:0]       rf_count;
237
wire                            rf_error_bit; // an error (parity or framing) is inside the fifo
238
wire                            break_error = (counter_b == 0);
239
 
240
// RX FIFO instance
241
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
242
        .clk(           clk             ),
243
        .wb_rst_i(      wb_rst_i        ),
244
        .data_in(       rf_data_in      ),
245
        .data_out(      rf_data_out     ),
246
        .push(          rf_push_pulse           ),
247
        .pop(           rf_pop          ),
248
        .overrun(       rf_overrun      ),
249
        .count(         rf_count        ),
250
        .error_bit(     rf_error_bit    ),
251
        .fifo_reset(    rx_reset        ),
252
        .reset_status(lsr_mask)
253
);
254
 
255
wire            rcounter16_eq_7 = (rcounter16 == 4'd7);
256
wire            rcounter16_eq_0 = (rcounter16 == 4'd0);
257
wire            rcounter16_eq_1 = (rcounter16 == 4'd1);
258
 
259
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
260
 
261
parameter  sr_idle                                      = 4'd0;
262
parameter  sr_rec_start                         = 4'd1;
263
parameter  sr_rec_bit                           = 4'd2;
264
parameter  sr_rec_parity                        = 4'd3;
265
parameter  sr_rec_stop                          = 4'd4;
266
parameter  sr_check_parity              = 4'd5;
267
parameter  sr_rec_prepare                       = 4'd6;
268
parameter  sr_end_bit                           = 4'd7;
269
parameter  sr_ca_lc_parity            = 4'd8;
270
parameter  sr_wait1                                     = 4'd9;
271
parameter  sr_push                                      = 4'd10;
272
 
273
 
274
always @(posedge clk or posedge wb_rst_i)
275
begin
276
  if (wb_rst_i)
277
  begin
278
     rstate                     <= sr_idle;
279
          rbit_in                               <= 1'b0;
280
          rcounter16                    <= 0;
281
          rbit_counter          <= 0;
282
          rparity_xor           <= 1'b0;
283
          rframing_error        <= 1'b0;
284
          rparity_error                 <= 1'b0;
285
          rparity                               <= 1'b0;
286
          rshift                                <= 0;
287
          rf_push                               <= 1'b0;
288
          rf_data_in                    <= 0;
289
  end
290
  else
291
  if (enable)
292
  begin
293
        case (rstate)
294
        sr_idle : begin
295
                        rf_push                           <= 1'b0;
296
                        rf_data_in        <= 0;
297
                        rcounter16        <= 4'b1110;
298
                        if (srx_pad_i==1'b0 & ~break_error)   // detected a pulse (start bit?)
299
                        begin
300
                                rstate            <= sr_rec_start;
301
                        end
302
                end
303
        sr_rec_start :  begin
304
                        rf_push                           <= 1'b0;
305
                                if (rcounter16_eq_7)    // check the pulse
306
                                        if (srx_pad_i==1'b1)   // no start bit
307
                                                rstate <= sr_idle;
308
                                        else            // start bit detected
309
                                                rstate <= sr_rec_prepare;
310
                                rcounter16 <= rcounter16_minus_1;
311
                        end
312
        sr_rec_prepare:begin
313
                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
314
                                2'b00 : rbit_counter <= 3'b100;
315
                                2'b01 : rbit_counter <= 3'b101;
316
                                2'b10 : rbit_counter <= 3'b110;
317
                                2'b11 : rbit_counter <= 3'b111;
318
                                endcase
319
                                if (rcounter16_eq_0)
320
                                begin
321
                                        rstate          <= sr_rec_bit;
322
                                        rcounter16      <= 4'b1110;
323
                                        rshift          <= 0;
324
                                end
325
                                else
326
                                        rstate <= sr_rec_prepare;
327
                                rcounter16 <= rcounter16_minus_1;
328
                        end
329
        sr_rec_bit :    begin
330
                                if (rcounter16_eq_0)
331
                                        rstate <= sr_end_bit;
332
                                if (rcounter16_eq_7) // read the bit
333
                                        case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
334
                                        2'b00 : rshift[4:0]  <= {srx_pad_i, rshift[4:1]};
335
                                        2'b01 : rshift[5:0]  <= {srx_pad_i, rshift[5:1]};
336
                                        2'b10 : rshift[6:0]  <= {srx_pad_i, rshift[6:1]};
337
                                        2'b11 : rshift[7:0]  <= {srx_pad_i, rshift[7:1]};
338
                                        endcase
339
                                rcounter16 <= rcounter16_minus_1;
340
                        end
341
        sr_end_bit :   begin
342
                                if (rbit_counter==3'b0) // no more bits in word
343
                                        if (lcr[`UART_LC_PE]) // choose state based on parity
344
                                                rstate <= sr_rec_parity;
345
                                        else
346
                                        begin
347
                                                rstate <= sr_rec_stop;
348
                                                rparity_error <= 1'b0;  // no parity - no error :)
349
                                        end
350
                                else            // else we have more bits to read
351
                                begin
352
                                        rstate <= sr_rec_bit;
353
                                        rbit_counter <= rbit_counter - 1'b1;
354
                                end
355
                                rcounter16 <= 4'b1110;
356
                        end
357
        sr_rec_parity: begin
358
                                if (rcounter16_eq_7)    // read the parity
359
                                begin
360
                                        rparity <= srx_pad_i;
361
                                        rstate <= sr_ca_lc_parity;
362
                                end
363
                                rcounter16 <= rcounter16_minus_1;
364
                        end
365
        sr_ca_lc_parity : begin    // rcounter equals 6
366
                                rcounter16  <= rcounter16_minus_1;
367
                                rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data
368
                                rstate      <= sr_check_parity;
369
                          end
370
        sr_check_parity: begin    // rcounter equals 5
371
                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
372
                                        2'b00: rparity_error <=  rparity_xor == 0;  // no error if parity 1
373
                                        2'b01: rparity_error <= ~rparity;      // parity should sticked to 1
374
                                        2'b10: rparity_error <=  rparity_xor == 1;   // error if parity is odd
375
                                        2'b11: rparity_error <=  rparity;         // parity should be sticked to 0
376
                                endcase
377
                                rcounter16 <= rcounter16_minus_1;
378
                                rstate <= sr_wait1;
379
                          end
380
        sr_wait1 :      if (rcounter16_eq_0)
381
                        begin
382
                                rstate <= sr_rec_stop;
383
                                rcounter16 <= 4'b1110;
384
                        end
385
                        else
386
                                rcounter16 <= rcounter16_minus_1;
387
        sr_rec_stop :   begin
388
                                if (rcounter16_eq_7)    // read the parity
389
                                begin
390
                                        rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit)
391
                                        rstate <= sr_push;
392
                                end
393
                                rcounter16 <= rcounter16_minus_1;
394
                        end
395
        sr_push :       begin
396
///////////////////////////////////////
397
//                              $display($time, ": received: %b", rf_data_in);
398
        if(srx_pad_i | break_error)
399
          begin
400
            if(break_error)
401
                          rf_data_in    <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
402
            else
403
                                rf_data_in  <= {rshift, 1'b0, rparity_error, rframing_error};
404
                  rf_push                 <= 1'b1;
405
                                rstate        <= sr_idle;
406
          end
407
        else if(~rframing_error)  // There's always a framing before break_error -> wait for break or srx_pad_i
408
          begin
409
                        rf_data_in  <= {rshift, 1'b0, rparity_error, rframing_error};
410
                  rf_push                 <= 1'b1;
411
                        rcounter16        <= 4'b1110;
412
                                rstate            <= sr_rec_start;
413
          end
414
 
415
                        end
416
        default : rstate <= sr_idle;
417
        endcase
418
  end  // if (enable)
419
end // always of receiver
420
 
421
always @ (posedge clk or posedge wb_rst_i)
422
begin
423
  if(wb_rst_i)
424
    rf_push_q <= 0;
425
  else
426
    rf_push_q <= rf_push;
427
end
428
 
429
assign rf_push_pulse = rf_push & ~rf_push_q;
430
 
431
 
432
//
433
// Break condition detection.
434
// Works in conjuction with the receiver state machine
435
 
436
reg     [9:0]    toc_value; // value to be set to timeout counter
437
 
438
always @(lcr)
439
        case (lcr[3:0])
440
                4'b0000                                                                         : toc_value = 447; // 7 bits
441
                4'b0100                                                                         : toc_value = 479; // 7.5 bits
442
                4'b0001,        4'b1000                                                 : toc_value = 511; // 8 bits
443
                4'b1100                                                                         : toc_value = 543; // 8.5 bits
444
                4'b0010, 4'b0101, 4'b1001                               : toc_value = 575; // 9 bits
445
                4'b0011, 4'b0110, 4'b1010, 4'b1101      : toc_value = 639; // 10 bits
446
                4'b0111, 4'b1011, 4'b1110                               : toc_value = 703; // 11 bits
447
                4'b1111                                                                         : toc_value = 767; // 12 bits
448
        endcase // case(lcr[3:0])
449
 
450
wire [7:0]       brc_value; // value to be set to break counter
451
assign          brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
452
 
453
always @(posedge clk or posedge wb_rst_i)
454
begin
455
        if (wb_rst_i)
456
                counter_b <= 8'd159;
457
        else
458
        if (srx_pad_i)
459
                counter_b <= brc_value; // character time length - 1
460
        else
461
        if(enable & counter_b != 8'b0)            // only work on enable times  break not reached.
462
                counter_b <= counter_b - 1;  // decrement break counter
463
end // always of break condition detection
464
 
465
///
466
/// Timeout condition detection
467
reg     [9:0]    counter_t;      // counts the timeout condition clocks
468
 
469
always @(posedge clk or posedge wb_rst_i)
470
begin
471
        if (wb_rst_i)
472
                counter_t <= 10'd639; // 10 bits for the default 8N1
473
        else
474
                if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
475
                        counter_t <= toc_value;
476
                else
477
                if (enable && counter_t != 10'b0)  // we don't want to underflow
478
                        counter_t <= counter_t - 1;
479
end
480
 
481
endmodule

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