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[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [uart_rfifo.v] - Blame information for rev 43

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1 43 Revanth
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  uart_rfifo.v (Modified from uart_fifo.v)                    ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  UART core receiver FIFO                                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Nothing.                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////      - Igor Mohor (igorm@opencores.org)                      ////
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////                                                              ////
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////  Created:        2001/05/12                                  ////
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////  Last Updated:   2002/07/22                                  ////
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////                  (See log for the revision history)          ////
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////                                                              ////
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//// Modified for use in the ZAP project by Revanth Kamaraj       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3  2003/06/11 16:37:47  gorban
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// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
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//
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// Revision 1.2  2002/07/29 21:16:18  gorban
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// The uart_defines.v file is included again in sources.
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//
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// Revision 1.1  2002/07/22 23:02:23  gorban
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// Bug Fixes:
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//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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//   Problem reported by Kenny.Tung.
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//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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//  * Made FIFO's as general inferrable memory where possible.
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//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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//  * Added optional baudrate output (baud_o).
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//  This is identical to BAUDOUT* signal on 16550 chip.
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//  It outputs 16xbit_clock_rate - the divided clock.
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//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.16  2001/12/20 13:25:46  mohor
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// rx push changed to be only one cycle wide.
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//
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// Revision 1.15  2001/12/18 09:01:07  mohor
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// Bug that was entered in the last update fixed (rx state machine).
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//
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// Revision 1.14  2001/12/17 14:46:48  mohor
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// overrun signal was moved to separate block because many sequential lsr
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// reads were preventing data from being written to rx fifo.
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// underrun signal was not used and was removed from the project.
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//
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// Revision 1.13  2001/11/26 21:38:54  gorban
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// Lots of fixes:
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// Break condition wasn't handled correctly at all.
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// LSR bits could lose their values.
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// LSR value after reset was wrong.
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// Timing of THRE interrupt signal corrected.
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// LSR bit 0 timing corrected.
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//
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// Revision 1.12  2001/11/08 14:54:23  mohor
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// Comments in Slovene language deleted, few small fixes for better work of
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// old tools. IRQs need to be fix.
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//
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// Revision 1.11  2001/11/07 17:51:52  gorban
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// Heavily rewritten interrupt and LSR subsystems.
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// Many bugs hopefully squashed.
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//
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// Revision 1.10  2001/10/20 09:58:40  gorban
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// Small synopsis fixes
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//
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// Revision 1.9  2001/08/24 21:01:12  mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.8  2001/08/24 08:48:10  mohor
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// FIFO was not cleared after the data was read bug fixed.
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//
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// Revision 1.7  2001/08/23 16:05:05  mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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// Revision 1.3  2001/05/31 20:08:01  gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.3  2001/05/27 17:37:48  gorban
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// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
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//
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// Revision 1.2  2001/05/17 18:34:18  gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0  2001-05-17 21:27:12+02  jacob
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// Initial revision
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//
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//
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`include "uart_defines.v"
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module uart_rfifo (clk,
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        wb_rst_i, data_in, data_out,
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// Control signals
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        push, // push strobe, active high
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        pop,   // pop strobe, active high
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// status signals
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        overrun,
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        count,
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        error_bit,
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        fifo_reset,
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        reset_status
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        );
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// FIFO parameters
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parameter fifo_width = `UART_FIFO_WIDTH;
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parameter fifo_depth = `UART_FIFO_DEPTH;
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parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
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parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
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input                           clk;
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input                           wb_rst_i;
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input                           push;
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input                           pop;
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input   [fifo_width-1:0] data_in;
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input                           fifo_reset;
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input       reset_status;
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output  [fifo_width-1:0] data_out;
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output                          overrun;
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output  [fifo_counter_w-1:0]     count;
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output                          error_bit;
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wire    [fifo_width-1:0] data_out;
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wire [7:0] data8_out;
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// flags FIFO
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reg     [2:0]    fifo[fifo_depth-1:0];
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// FIFO pointers
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reg     [fifo_pointer_w-1:0]     top;
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reg     [fifo_pointer_w-1:0]     bottom;
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reg     [fifo_counter_w-1:0]     count;
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reg                             overrun;
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wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
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raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
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        (.clk(clk),
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                        .we(push),
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                        .a(top),
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                        .dpra(bottom),
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                        .di(data_in[fifo_width-1:fifo_width-8]),
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                        .dpo(data8_out)
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                );
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always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
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begin
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        if (wb_rst_i)
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        begin
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                top             <= 0;
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                bottom          <= 1'b0;
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                count           <= 0;
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                fifo[0] <= 0;
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                fifo[1] <= 0;
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                fifo[2] <= 0;
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                fifo[3] <= 0;
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                fifo[4] <= 0;
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                fifo[5] <= 0;
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                fifo[6] <= 0;
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                fifo[7] <= 0;
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                fifo[8] <= 0;
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                fifo[9] <= 0;
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                fifo[10] <= 0;
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                fifo[11] <= 0;
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                fifo[12] <= 0;
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                fifo[13] <= 0;
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                fifo[14] <= 0;
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                fifo[15] <= 0;
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        end
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        else
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        if (fifo_reset) begin
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                top             <= 0;
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                bottom          <= 1'b0;
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                count           <= 0;
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                fifo[0] <= 0;
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                fifo[1] <= 0;
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                fifo[2] <= 0;
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                fifo[3] <= 0;
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                fifo[4] <= 0;
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                fifo[5] <= 0;
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                fifo[6] <= 0;
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                fifo[7] <= 0;
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                fifo[8] <= 0;
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                fifo[9] <= 0;
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                fifo[10] <= 0;
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                fifo[11] <= 0;
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                fifo[12] <= 0;
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                fifo[13] <= 0;
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                fifo[14] <= 0;
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                fifo[15] <= 0;
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        end
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  else
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        begin
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                case ({push, pop})
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                2'b10 : if (count<fifo_depth)  // overrun condition
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                        begin
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                                top       <= top_plus_1;
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                                fifo[top] <= data_in[2:0];
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                                count     <= count + 1'b1;
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                        end
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                2'b01 : if(count>0)
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                        begin
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        fifo[bottom] <= 0;
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                                bottom   <= bottom + 1'b1;
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                                count    <= count - 1'b1;
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                        end
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                2'b11 : begin
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                                bottom   <= bottom + 1'b1;
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                                top       <= top_plus_1;
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                                fifo[top] <= data_in[2:0];
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                        end
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    default: ;
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                endcase
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        end
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end   // always
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always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
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begin
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  if (wb_rst_i)
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    overrun   <= 1'b0;
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  else
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  if(fifo_reset | reset_status)
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    overrun   <= 1'b0;
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  else
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  if(push & ~pop & (count==fifo_depth))
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    overrun   <= 1'b1;
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end   // always
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// please note though that data_out is only valid one clock after pop signal
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assign data_out = {data8_out,fifo[bottom]};
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// Additional logic for detection of error conditions (parity and framing) inside the FIFO
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// for the Line Status Register bit 7
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wire    [2:0]    word0 = fifo[0];
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wire    [2:0]    word1 = fifo[1];
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wire    [2:0]    word2 = fifo[2];
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wire    [2:0]    word3 = fifo[3];
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wire    [2:0]    word4 = fifo[4];
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wire    [2:0]    word5 = fifo[5];
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wire    [2:0]    word6 = fifo[6];
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wire    [2:0]    word7 = fifo[7];
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wire    [2:0]    word8 = fifo[8];
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wire    [2:0]    word9 = fifo[9];
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wire    [2:0]    word10 = fifo[10];
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wire    [2:0]    word11 = fifo[11];
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wire    [2:0]    word12 = fifo[12];
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wire    [2:0]    word13 = fifo[13];
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wire    [2:0]    word14 = fifo[14];
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wire    [2:0]    word15 = fifo[15];
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// a 1 is returned if any of the error bits in the fifo is 1
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assign  error_bit = |(word0[2:0]  | word1[2:0]  | word2[2:0]  | word3[2:0]  |
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                              word4[2:0]  | word5[2:0]  | word6[2:0]  | word7[2:0]  |
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                              word8[2:0]  | word9[2:0]  | word10[2:0] | word11[2:0] |
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                              word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
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endmodule

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