OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [uart_sync_flops.v] - Blame information for rev 43

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 43 Revanth
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  uart_sync_flops.v                                             ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the "UART 16550 compatible" project    ////
7
////  http://www.opencores.org/cores/uart16550/                   ////
8
////                                                              ////
9
////  Documentation related to this project:                      ////
10
////  - http://www.opencores.org/cores/uart16550/                 ////
11
////                                                              ////
12
////  Projects compatibility:                                     ////
13
////  - WISHBONE                                                  ////
14
////  RS232 Protocol                                              ////
15
////  16550D uart (mostly supported)                              ////
16
////                                                              ////
17
////  Overview (main Features):                                   ////
18
////  UART core receiver logic                                    ////
19
////                                                              ////
20
////  Known problems (limits):                                    ////
21
////  None known                                                  ////
22
////                                                              ////
23
////  To Do:                                                      ////
24
////  Thourough testing.                                          ////
25
////                                                              ////
26
////  Author(s):                                                  ////
27
////      - Andrej Erzen (andreje@flextronics.si)                 ////
28
////      - Tadej Markovic (tadejm@flextronics.si)                ////
29
////                                                              ////
30
////  Created:        2004/05/20                                  ////
31
////  Last Updated:   2004/05/20                                  ////
32
////                  (See log for the revision history)          ////
33
//// Modified for use in the ZAP project by Revanth Kamaraj       ////
34
////                                                              ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
////                                                              ////
38
//// Copyright (C) 2000, 2001 Authors                             ////
39
////                                                              ////
40
//// This source file may be used and distributed without         ////
41
//// restriction provided that this copyright statement is not    ////
42
//// removed from the file and that any derivative work contains  ////
43
//// the original copyright notice and the associated disclaimer. ////
44
////                                                              ////
45
//// This source file is free software; you can redistribute it   ////
46
//// and/or modify it under the terms of the GNU Lesser General   ////
47
//// Public License as published by the Free Software Foundation; ////
48
//// either version 2.1 of the License, or (at your option) any   ////
49
//// later version.                                               ////
50
////                                                              ////
51
//// This source is distributed in the hope that it will be       ////
52
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55
//// details.                                                     ////
56
////                                                              ////
57
//// You should have received a copy of the GNU Lesser General    ////
58
//// Public License along with this source; if not, download it   ////
59
//// from http://www.opencores.org/lgpl.shtml                     ////
60
////                                                              ////
61
//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65
// $Log: not supported by cvs2svn $
66
//
67
 
68
 
69
 
70
 
71
module uart_sync_flops
72
(
73
  // internal signals
74
  rst_i,
75
  clk_i,
76
  stage1_rst_i,
77
  stage1_clk_en_i,
78
  async_dat_i,
79
  sync_dat_o
80
);
81
 
82
parameter Tp            = 1;
83
parameter width         = 1;
84
parameter init_value    = 1'b0;
85
 
86
input                           rst_i;                  // reset input
87
input                           clk_i;                  // clock input
88
input                           stage1_rst_i;           // synchronous reset for stage 1 FF
89
input                           stage1_clk_en_i;        // synchronous clock enable for stage 1 FF
90
input   [width-1:0]             async_dat_i;            // asynchronous data input
91
output  [width-1:0]             sync_dat_o;             // synchronous data output
92
 
93
 
94
//
95
// Interal signal declarations
96
//
97
 
98
reg     [width-1:0]             sync_dat_o;
99
reg     [width-1:0]             flop_0;
100
 
101
 
102
// first stage
103
always @ (posedge clk_i or posedge rst_i)
104
begin
105
    if (rst_i)
106
        flop_0 <= #Tp {width{init_value}};
107
    else
108
        flop_0 <= #Tp async_dat_i;
109
end
110
 
111
// second stage
112
always @ (posedge clk_i or posedge rst_i)
113
begin
114
    if (rst_i)
115
        sync_dat_o <= #Tp {width{init_value}};
116
    else if (stage1_rst_i)
117
        sync_dat_o <= #Tp {width{init_value}};
118
    else if (stage1_clk_en_i)
119
        sync_dat_o <= #Tp flop_0;
120
end
121
 
122
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.