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[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [uart_transmitter.v] - Blame information for rev 43

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1 43 Revanth
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  uart_transmitter.v                                          ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  UART core transmitter logic                                 ////
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////                                                              ////
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////  Known problems (limits):                                    ////
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////  None known                                                  ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Thourough testing.                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////      - Igor Mohor (igorm@opencores.org)                      ////
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////                                                              ////
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////  Created:        2001/05/12                                  ////
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////  Last Updated:   2001/05/17                                  ////
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////                  (See log for the revision history)          ////
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////                                                              ////
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//// Modified for use in the ZAP project by Revanth Kamaraj       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.18  2002/07/22 23:02:23  gorban
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// Bug Fixes:
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//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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//   Problem reported by Kenny.Tung.
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//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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//  * Made FIFO's as general inferrable memory where possible.
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//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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//  * Added optional baudrate output (baud_o).
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//  This is identical to BAUDOUT* signal on 16550 chip.
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//  It outputs 16xbit_clock_rate - the divided clock.
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//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.16  2002/01/08 11:29:40  mohor
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// tf_pop was too wide. Now it is only 1 clk cycle width.
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//
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// Revision 1.15  2001/12/17 14:46:48  mohor
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// overrun signal was moved to separate block because many sequential lsr
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// reads were preventing data from being written to rx fifo.
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// underrun signal was not used and was removed from the project.
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//
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// Revision 1.14  2001/12/03 21:44:29  gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.13  2001/11/08 14:54:23  mohor
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// Comments in Slovene language deleted, few small fixes for better work of
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// old tools. IRQs need to be fix.
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//
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// Revision 1.12  2001/11/07 17:51:52  gorban
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// Heavily rewritten interrupt and LSR subsystems.
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// Many bugs hopefully squashed.
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//
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// Revision 1.11  2001/10/29 17:00:46  gorban
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// fixed parity sending and tx_fifo resets over- and underrun
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//
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// Revision 1.10  2001/10/20 09:58:40  gorban
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// Small synopsis fixes
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//
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// Revision 1.9  2001/08/24 21:01:12  mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.8  2001/08/23 16:05:05  mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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// Revision 1.6  2001/06/23 11:21:48  gorban
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// DL made 16-bit long. Fixed transmission/reception bugs.
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//
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// Revision 1.5  2001/06/02 14:28:14  gorban
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// Fixed receiver and transmitter. Major bug fixed.
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//
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// Revision 1.4  2001/05/31 20:08:01  gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.3  2001/05/27 17:37:49  gorban
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// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
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//
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// Revision 1.2  2001/05/21 19:12:02  gorban
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// Corrected some Linter messages.
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//
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// Revision 1.1  2001/05/17 18:34:18  gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0  2001-05-17 21:27:12+02  jacob
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// Initial revision
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//
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//
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`include "uart_defines.v"
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module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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input                                                                           clk;
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input                                                                           wb_rst_i;
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input [7:0]                                                              lcr;
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input                                                                           tf_push;
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input [7:0]                                                              wb_dat_i;
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input                                                                           enable;
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input                                                                           tx_reset;
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input                                                                           lsr_mask; //reset of fifo
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output                                                                          stx_pad_o;
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output [2:0]                                                             tstate;
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output [`UART_FIFO_COUNTER_W-1:0]        tf_count;
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reg [2:0]                                                                        tstate;
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reg [4:0]                                                                        counter;
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reg [2:0]                                                                        bit_counter;   // counts the bits to be sent
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reg [6:0]                                                                        shift_out;      // output shift register
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reg                                                                                     stx_o_tmp;
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reg                                                                                     parity_xor;  // parity of the word
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reg                                                                                     tf_pop;
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reg                                                                                     bit_out;
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// TX FIFO instance
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//
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// Transmitter FIFO signals
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wire [`UART_FIFO_WIDTH-1:0]                      tf_data_in;
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wire [`UART_FIFO_WIDTH-1:0]                      tf_data_out;
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wire                                                                                    tf_push;
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wire                                                                                    tf_overrun;
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wire [`UART_FIFO_COUNTER_W-1:0]          tf_count;
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assign                                                                          tf_data_in = wb_dat_i;
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uart_tfifo fifo_tx(     // error bit signal is not used in transmitter FIFO
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        .clk(           clk             ),
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        .wb_rst_i(      wb_rst_i        ),
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        .data_in(       tf_data_in      ),
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        .data_out(      tf_data_out     ),
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        .push(          tf_push         ),
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        .pop(           tf_pop          ),
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        .overrun(       tf_overrun      ),
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        .count(         tf_count        ),
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        .fifo_reset(    tx_reset        ),
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        .reset_status(lsr_mask)
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);
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// TRANSMITTER FINAL STATE MACHINE
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parameter s_idle        = 3'd0;
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parameter s_send_start  = 3'd1;
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parameter s_send_byte   = 3'd2;
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parameter s_send_parity = 3'd3;
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parameter s_send_stop   = 3'd4;
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parameter s_pop_byte    = 3'd5;
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always @(posedge clk or posedge wb_rst_i)
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begin
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  if (wb_rst_i)
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  begin
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        tstate       <= s_idle;
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        stx_o_tmp       <= 1'b1;
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        counter   <= 5'b0;
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        shift_out   <= 7'b0;
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        bit_out     <= 1'b0;
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        parity_xor  <= 1'b0;
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        tf_pop      <= 1'b0;
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        bit_counter <= 3'b0;
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  end
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  else
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  if (enable)
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  begin
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        case (tstate)
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        s_idle   :      if (~|tf_count) // if tf_count==0
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                        begin
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                                tstate <= s_idle;
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                                stx_o_tmp <= 1'b1;
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                        end
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                        else
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                        begin
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                                tf_pop <= 1'b0;
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                                stx_o_tmp  <= 1'b1;
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                                tstate  <= s_pop_byte;
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                        end
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        s_pop_byte :    begin
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                                tf_pop <= 1'b1;
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                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
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                                2'b00 : begin
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                                        bit_counter <= 3'b100;
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                                        parity_xor  <= ^tf_data_out[4:0];
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                                     end
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                                2'b01 : begin
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                                        bit_counter <= 3'b101;
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                                        parity_xor  <= ^tf_data_out[5:0];
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                                     end
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                                2'b10 : begin
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                                        bit_counter <= 3'b110;
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                                        parity_xor  <= ^tf_data_out[6:0];
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                                     end
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                                2'b11 : begin
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                                        bit_counter <= 3'b111;
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                                        parity_xor  <= ^tf_data_out[7:0];
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                                     end
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                                endcase
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                                {shift_out[6:0], bit_out} <= tf_data_out;
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                                tstate <= s_send_start;
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                        end
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        s_send_start :  begin
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                                tf_pop <= 1'b0;
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                                if (~|counter)
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                                        counter <= 5'b01111;
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                                else
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                                if (counter == 5'b00001)
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                                begin
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                                        counter <= 0;
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                                        tstate <= s_send_byte;
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                                end
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                                else
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                                        counter <= counter - 1'b1;
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                                stx_o_tmp <= 1'b0;
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                        end
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        s_send_byte :   begin
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                                if (~|counter)
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                                        counter <= 5'b01111;
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                                else
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                                if (counter == 5'b00001)
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                                begin
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                                        if (bit_counter > 3'b0)
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                                        begin
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                                                bit_counter <= bit_counter - 1'b1;
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                                                {shift_out[5:0],bit_out  } <= {shift_out[6:1], shift_out[0]};
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                                                tstate <= s_send_byte;
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                                        end
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                                        else   // end of byte
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                                        if (~lcr[`UART_LC_PE])
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                                        begin
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                                                tstate <= s_send_stop;
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                                        end
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                                        else
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                                        begin
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                                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
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                                                2'b00:  bit_out <= ~parity_xor;
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                                                2'b01:  bit_out <= 1'b1;
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                                                2'b10:  bit_out <= parity_xor;
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                                                2'b11:  bit_out <= 1'b0;
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                                                endcase
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                                                tstate <= s_send_parity;
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                                        end
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                                        counter <= 0;
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                                end
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                                else
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                                        counter <= counter - 1'b1;
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                                stx_o_tmp <= bit_out; // set output pin
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                        end
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        s_send_parity : begin
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                                if (~|counter)
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                                        counter <= 5'b01111;
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                                else
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                                if (counter == 5'b00001)
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                                begin
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                                        counter <= 4'b0;
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                                        tstate <= s_send_stop;
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                                end
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                                else
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                                        counter <= counter - 1'b1;
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                                stx_o_tmp <= bit_out;
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                        end
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        s_send_stop :  begin
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                                if (~|counter)
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                                  begin
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                                                casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
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                                                3'b0xx:   counter <= 5'b01101;     // 1 stop bit ok igor
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                                                3'b100:   counter <= 5'b10101;     // 1.5 stop bit
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                                                default:          counter <= 5'b11101;     // 2 stop bits
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                                                endcase
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                                        end
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                                else
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                                if (counter == 5'b00001)
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                                begin
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                                        counter <= 0;
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                                        tstate <= s_idle;
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                                end
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                                else
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                                        counter <= counter - 1'b1;
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                                stx_o_tmp <= 1'b1;
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                        end
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                default : // should never get here
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                        tstate <= s_idle;
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        endcase
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  end // end if enable
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  else
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    tf_pop <= 1'b0;  // tf_pop must be 1 cycle width
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end // transmitter logic
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assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
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endmodule

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