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[/] [zap/] [trunk/] [src/] [testbench/] [External_IP/] [uart16550/] [rtl/] [uart_wb.v] - Blame information for rev 43

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  uart_wb.v                                                   ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  UART core WISHBONE interface.                               ////
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////                                                              ////
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////  Known problems (limits):                                    ////
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////  Inserts one wait state on all transfers.                    ////
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////  Note affected signals and the way they are affected.        ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Nothing.                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////      - Igor Mohor (igorm@opencores.org)                      ////
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////                                                              ////
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////  Created:        2001/05/12                                  ////
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////  Last Updated:   2001/05/17                                  ////
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////                  (See log for the revision history)          ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.16  2002/07/29 21:16:18  gorban
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// The uart_defines.v file is included again in sources.
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//
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// Revision 1.15  2002/07/22 23:02:23  gorban
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// Bug Fixes:
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//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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//   Problem reported by Kenny.Tung.
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//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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//  * Made FIFO's as general inferrable memory where possible.
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//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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//  * Added optional baudrate output (baud_o).
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//  This is identical to BAUDOUT* signal on 16550 chip.
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//  It outputs 16xbit_clock_rate - the divided clock.
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//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.12  2001/12/19 08:03:34  mohor
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// Warnings cleared.
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//
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// Revision 1.11  2001/12/06 14:51:04  gorban
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// Bug in LSR[0] is fixed.
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// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
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//
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// Revision 1.10  2001/12/03 21:44:29  gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.9  2001/10/20 09:58:40  gorban
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// Small synopsis fixes
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//
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// Revision 1.8  2001/08/24 21:01:12  mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.7  2001/08/23 16:05:05  mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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// Revision 1.4  2001/05/31 20:08:01  gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.3  2001/05/21 19:12:01  gorban
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// Corrected some Linter messages.
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//
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// Revision 1.2  2001/05/17 18:34:18  gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0  2001-05-17 21:27:13+02  jacob
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// Initial revision
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//
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//
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// UART core WISHBONE interface 
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//
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// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
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// Company: Flextronics Semiconductor
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//
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`include "uart_defines.v"
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module uart_wb (clk, wb_rst_i,
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        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
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        wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
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        we_o, re_o // Write and read enable output for the core
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);
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input             clk;
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// WISHBONE interface   
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input             wb_rst_i;
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input             wb_we_i;
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input             wb_stb_i;
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input             wb_cyc_i;
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input [3:0]   wb_sel_i;
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input [`UART_ADDR_WIDTH-1:0]     wb_adr_i; //WISHBONE address line
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`ifdef DATA_BUS_WIDTH_8
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input [7:0]  wb_dat_i; //input WISHBONE bus 
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output [7:0] wb_dat_o;
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reg [7:0]         wb_dat_o;
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wire [7:0]        wb_dat_i;
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reg [7:0]         wb_dat_is;
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`else // for 32 data bus mode
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input [31:0]  wb_dat_i; //input WISHBONE bus 
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output [31:0] wb_dat_o;
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reg [31:0]         wb_dat_o;
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wire [31:0]   wb_dat_i;
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reg [31:0]         wb_dat_is;
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`endif // !`ifdef DATA_BUS_WIDTH_8
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output [`UART_ADDR_WIDTH-1:0]    wb_adr_int; // internal signal for address bus
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input [7:0]   wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
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output [7:0]  wb_dat8_i;
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input [31:0]  wb_dat32_o; // 32 bit data output (for debug interface)
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output            wb_ack_o;
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output            we_o;
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output            re_o;
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wire                      we_o;
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reg                       wb_ack_o;
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reg [7:0]          wb_dat8_i;
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wire [7:0]         wb_dat8_o;
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wire [`UART_ADDR_WIDTH-1:0]      wb_adr_int; // internal signal for address bus
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reg [`UART_ADDR_WIDTH-1:0]       wb_adr_is;
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reg                                                             wb_we_is;
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reg                                                             wb_cyc_is;
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reg                                                             wb_stb_is;
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reg [3:0]                                                wb_sel_is;
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wire [3:0]   wb_sel_i;
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reg                      wre ;// timing control signal for write or read enable
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// wb_ack_o FSM
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reg [1:0]         wbstate;
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always  @(posedge clk or posedge wb_rst_i)
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        if (wb_rst_i) begin
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                wb_ack_o <= 1'b0;
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                wbstate <= 0;
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                wre <= 1'b1;
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        end else
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                case (wbstate)
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                        0: begin
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                                if (wb_stb_is & wb_cyc_is) begin
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                                        wre <= 0;
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                                        wbstate <= 1;
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                                        wb_ack_o <= 1;
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                                end else begin
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                                        wre <= 1;
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                                        wb_ack_o <= 0;
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                                end
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                        end
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                        1: begin
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                           wb_ack_o <= 0;
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                                wbstate <= 2;
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                                wre <= 0;
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                        end
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                        2,3: begin
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                                wb_ack_o <= 0;
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                                wbstate <= 0;
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                                wre <= 0;
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                        end
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                endcase
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assign we_o =  wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers      
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assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers      
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// Sample input signals
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always  @(posedge clk or posedge wb_rst_i)
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        if (wb_rst_i) begin
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                wb_adr_is <= 0;
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                wb_we_is <= 0;
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                wb_cyc_is <= 0;
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                wb_stb_is <= 0;
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                wb_dat_is <= 0;
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                wb_sel_is <= 0;
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        end else begin
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                wb_adr_is <= wb_adr_i;
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                wb_we_is <= wb_we_i;
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                wb_cyc_is <= wb_cyc_i;
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                wb_stb_is <= wb_stb_i;
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                wb_dat_is <= wb_dat_i;
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                wb_sel_is <= wb_sel_i;
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        end
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`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
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always @(posedge clk or posedge wb_rst_i)
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        if (wb_rst_i)
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                wb_dat_o <= 0;
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        else
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                wb_dat_o <= wb_dat8_o;
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always @(wb_dat_is)
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        wb_dat8_i = wb_dat_is;
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assign wb_adr_int = wb_adr_is;
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`else // 32-bit bus
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// put output to the correct byte in 32 bits using select line
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always @(posedge clk or posedge wb_rst_i)
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        if (wb_rst_i)
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                wb_dat_o <= 0;
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        else if (re_o)
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                case (wb_sel_is)
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                        4'b0001: wb_dat_o <= {24'b0, wb_dat8_o};
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                        4'b0010: wb_dat_o <= {16'b0, wb_dat8_o, 8'b0};
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                        4'b0100: wb_dat_o <= {8'b0, wb_dat8_o, 16'b0};
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                        4'b1000: wb_dat_o <= {wb_dat8_o, 24'b0};
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                        4'b1111: wb_dat_o <= wb_dat32_o; // debug interface output
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                        default: wb_dat_o <= 0;
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                endcase // case(wb_sel_i)
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reg [1:0] wb_adr_int_lsb;
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always @(wb_sel_is or wb_dat_is)
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begin
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        case (wb_sel_is)
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                4'b0001 : wb_dat8_i = wb_dat_is[7:0];
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                4'b0010 : wb_dat8_i = wb_dat_is[15:8];
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                4'b0100 : wb_dat8_i = wb_dat_is[23:16];
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                4'b1000 : wb_dat8_i = wb_dat_is[31:24];
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                default : wb_dat8_i = wb_dat_is[7:0];
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        endcase // case(wb_sel_i)
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  `ifdef LITLE_ENDIAN
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        case (wb_sel_is)
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                4'b0001 : wb_adr_int_lsb = 2'h0;
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                4'b0010 : wb_adr_int_lsb = 2'h1;
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                4'b0100 : wb_adr_int_lsb = 2'h2;
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                4'b1000 : wb_adr_int_lsb = 2'h3;
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                default : wb_adr_int_lsb = 2'h0;
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        endcase // case(wb_sel_i)
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  `else
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        case (wb_sel_is)
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                4'b0001 : wb_adr_int_lsb = 2'h3;
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                4'b0010 : wb_adr_int_lsb = 2'h2;
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                4'b0100 : wb_adr_int_lsb = 2'h1;
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                4'b1000 : wb_adr_int_lsb = 2'h0;
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                default : wb_adr_int_lsb = 2'h0;
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        endcase // case(wb_sel_i)
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  `endif
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end
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assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
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`endif // !`ifdef DATA_BUS_WIDTH_8
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endmodule
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