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[/] [zap/] [trunk/] [src/] [testbench/] [chip_top.v] - Blame information for rev 43

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1 43 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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//
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// This is the chip top that contains the ZAP core along with
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// 2 x UARTs
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// 2 x Timers
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// 1 x VIC
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//
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// UART0  address space FFFFFFE0 to FFFFFFFF
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// Timer0 address space FFFFFFC0 to FFFFFFDF
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// VIC0   address space FFFFFFA0 to FFFFFFBF
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// UART1  address space FFFFFF80 to FFFFFF9F
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// Timer1 address space FFFFFF60 to FFFFFF7F
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// 
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// Accesses outside this go the the wishbone interface.
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//
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// An extenal Wishbone interface is provided to allow connection to an external
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// Wishbone network for RAMs, ROMs etc.
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//
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// -----------------------------------------------------------------------------
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module chip_top #(
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// CPU config.
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parameter DATA_SECTION_TLB_ENTRIES      = 4,
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parameter DATA_LPAGE_TLB_ENTRIES        = 8,
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parameter DATA_SPAGE_TLB_ENTRIES        = 16,
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parameter DATA_CACHE_SIZE               = 1024,
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parameter CODE_SECTION_TLB_ENTRIES      = 4,
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parameter CODE_LPAGE_TLB_ENTRIES        = 8,
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parameter CODE_SPAGE_TLB_ENTRIES        = 16,
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parameter CODE_CACHE_SIZE               = 1024,
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parameter FIFO_DEPTH                    = 4,
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parameter BP_ENTRIES                    = 1024,
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parameter STORE_BUFFER_DEPTH            = 32
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57
)(
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        // Clk and rst 
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        input wire          SYS_CLK,
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        input wire          SYS_RST,
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        // UART 0
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        input  wire         UART0_RXD,
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        output wire         UART0_TXD,
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        // UART 1
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        input  wire         UART1_RXD,
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        output wire         UART1_TXD,
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        // Remaining IRQs to the interrupt controller.
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        input   wire [27:0] I_IRQ,
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        // Single FIQ input directly to ZAP CPU.
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        input   wire        I_FIQ,
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76
        // External Wishbone Connection (for RAMs etc).
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        output wire         O_WB_STB,
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        output wire         O_WB_CYC,
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        output wire [31:0]  O_WB_DAT,
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        output wire [31:0]  O_WB_ADR,
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        output wire [3:0]   O_WB_SEL,
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        output wire         O_WB_WE,
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        input  wire         I_WB_ACK,
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        input  wire [31:0]  I_WB_DAT
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);
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87
`include "zap_defines.vh"
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`include "zap_localparams.vh"
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`include "zap_functions.vh"
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91
// Peripheral addresses.
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localparam UART0_LO                     = 32'hFFFFFFE0;
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localparam UART0_HI                     = 32'hFFFFFFFF;
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localparam TIMER0_LO                    = 32'hFFFFFFC0;
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localparam TIMER0_HI                    = 32'hFFFFFFDF;
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localparam VIC_LO                       = 32'hFFFFFFA0;
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localparam VIC_HI                       = 32'hFFFFFFBF;
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localparam UART1_LO                     = 32'hFFFFFF80;
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localparam UART1_HI                     = 32'hFFFFFF9F;
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localparam TIMER1_LO                    = 32'hFFFFFF60;
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localparam TIMER1_HI                    = 32'hFFFFFF7F;
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103
// Internal signals.
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wire            i_clk    = SYS_CLK;
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wire            i_reset  = SYS_RST;
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wire [1:0]      uart_in  = {UART1_RXD, UART0_RXD};
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wire [1:0]      uart_out;
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assign          {UART1_TXD, UART0_TXD} = uart_out;
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wire            data_wb_cyc;
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wire            data_wb_stb;
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reg [31:0]      data_wb_din;
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reg             data_wb_ack;
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reg             data_wb_cyc_ram, data_wb_cyc_uart [1:0], data_wb_cyc_timer [1:0], data_wb_cyc_vic;
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reg             data_wb_stb_ram, data_wb_stb_uart [1:0], data_wb_stb_timer [1:0], data_wb_stb_vic;
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wire [31:0]     data_wb_din_ram, data_wb_din_uart [1:0], data_wb_din_timer [1:0], data_wb_din_vic;
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wire            data_wb_ack_ram, data_wb_ack_uart [1:0], data_wb_ack_timer [1:0], data_wb_ack_vic;
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wire [3:0]      data_wb_sel;
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wire            data_wb_we;
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wire [31:0]     data_wb_dout;
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wire [31:0]     data_wb_adr;
121
wire [2:0]      data_wb_cti; // Cycle Type Indicator.
122
wire            global_irq;
123
wire [1:0]      uart_irq;
124
wire [1:0]      timer_irq;
125
wire            ext_stb;
126
wire            ext_cyc;
127
wire [31:0]     ext_adr;
128
 
129
// Assigns.
130
assign        O_WB_CYC        = data_wb_cyc_ram;
131
assign        O_WB_STB        = data_wb_stb_ram;
132
assign        O_WB_ADR        = data_wb_adr;
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assign        O_WB_WE         = data_wb_we;
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assign        O_WB_DAT        = data_wb_dout;
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assign        O_WB_SEL        = data_wb_sel;
136
assign        data_wb_din_ram = I_WB_DAT;
137
assign        data_wb_ack_ram = I_WB_ACK;
138
 
139
// Wishbone selector.
140
always @*
141
begin:blk1
142
        integer ii;
143
 
144
        for(ii=0;ii<=1;ii=ii+1)
145
        begin
146
                data_wb_cyc_uart [ii]  = 0;
147
                data_wb_stb_uart [ii]  = 0;
148
                data_wb_cyc_timer[ii] = 0;
149
                data_wb_stb_timer[ii] = 0;
150
        end
151
 
152
        data_wb_cyc_vic   = 0;
153
        data_wb_stb_vic   = 0;
154
 
155
        if ( data_wb_adr >= UART0_LO && data_wb_adr <= UART0_HI )        // UART0 access
156
        begin
157
                data_wb_cyc_uart[0] = data_wb_cyc;
158
                data_wb_stb_uart[0] = data_wb_stb;
159
                data_wb_ack        = data_wb_ack_uart[0];
160
                data_wb_din        = data_wb_din_uart[0];
161
        end
162
        else if ( data_wb_adr >= TIMER0_LO && data_wb_adr <= TIMER0_HI )  // Timer0 access
163
        begin
164
                data_wb_cyc_timer[0] = data_wb_cyc;
165
                data_wb_stb_timer[0] = data_wb_stb;
166
                data_wb_ack          = data_wb_ack_timer[0];
167
                data_wb_din          = data_wb_din_timer[0];
168
        end
169
        else if ( data_wb_adr >= VIC_LO && data_wb_adr <= VIC_HI )        // VIC access.
170
        begin
171
                data_wb_cyc_vic   = data_wb_cyc;
172
                data_wb_stb_vic   = data_wb_stb;
173
                data_wb_ack       = data_wb_ack_vic;
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                data_wb_din       = data_wb_din_vic;
175
        end
176
        else if ( data_wb_adr >= UART1_LO && data_wb_adr <= UART1_HI )    // UART1 access
177
        begin
178
                data_wb_cyc_uart[1] = data_wb_cyc;
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                data_wb_stb_uart[1] = data_wb_stb;
180
                data_wb_ack        = data_wb_ack_uart[1];
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                data_wb_din        = data_wb_din_uart[1];
182
        end
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        else if ( data_wb_adr >= TIMER1_LO && data_wb_adr <= TIMER1_HI )  // Timer1 access
184
        begin
185
                data_wb_cyc_timer[1] = data_wb_cyc;
186
                data_wb_stb_timer[1] = data_wb_stb;
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                data_wb_ack          = data_wb_ack_timer[1];
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                data_wb_din          = data_wb_din_timer[1];
189
        end
190
        else // External WB access.
191
        begin
192
                data_wb_ack      = data_wb_ack_ram;
193
                data_wb_din      = data_wb_din_ram;
194
        end
195
end
196
 
197
always @ (posedge i_clk)
198
begin
199
        if ( ext_adr < TIMER1_LO )
200
        begin
201
                data_wb_cyc_ram <= ext_cyc;
202
                data_wb_stb_ram <= ext_stb;
203
        end
204
        else
205
        begin
206
                data_wb_cyc_ram <= 1'd0;
207
                data_wb_stb_ram <= 1'd0;
208
        end
209
end
210
 
211
// =========================
212
// Processor core.
213
// =========================
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215
zap_top #(
216
        .FIFO_DEPTH(FIFO_DEPTH),
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        .BP_ENTRIES(BP_ENTRIES),
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        .STORE_BUFFER_DEPTH(STORE_BUFFER_DEPTH),
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        .DATA_SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES),
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        .DATA_LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
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        .DATA_SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
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        .DATA_CACHE_SIZE(DATA_CACHE_SIZE),
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        .CODE_SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES),
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        .CODE_LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
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        .CODE_SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES),
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        .CODE_CACHE_SIZE(CODE_CACHE_SIZE)
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)
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u_zap_top
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(
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        .i_clk(i_clk),
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        .i_reset(i_reset),
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        .i_irq(global_irq),
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        .i_fiq    (I_FIQ),
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        .o_wb_cyc (data_wb_cyc),
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        .o_wb_stb (data_wb_stb),
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        .o_wb_adr (data_wb_adr),
237
        .o_wb_we  (data_wb_we),
238
        .o_wb_cti (data_wb_cti),
239
        .i_wb_dat (data_wb_din),
240
        .o_wb_dat (data_wb_dout),
241
        .i_wb_ack (data_wb_ack),
242
        .o_wb_sel (data_wb_sel),
243
 
244
        // Strobe and CYC nxt pins.
245
        .o_wb_stb_nxt (ext_stb),
246
        .o_wb_cyc_nxt (ext_cyc),
247
        .o_wb_adr_nxt (ext_adr),
248
 
249
        .o_wb_bte ()             // Always zero.
250
 
251
);
252
 
253
// ===============================
254
// 2 x UART + 2 x Timer
255
// ===============================
256
 
257
genvar gi;
258
generate
259
begin
260
        for(gi=0;gi<=1;gi=gi+1)
261
        begin: uart_gen
262
                uart_top u_uart_top (
263
 
264
                        // WISHBONE interface
265
                        .wb_clk_i(i_clk),
266
                        .wb_rst_i(i_reset),
267
                        .wb_adr_i(data_wb_adr),
268
                        .wb_dat_i(data_wb_dout),
269
                        .wb_dat_o(data_wb_din_uart[gi]),
270
                        .wb_we_i (data_wb_we),
271
                        .wb_stb_i(data_wb_stb_uart[gi]),
272
                        .wb_cyc_i(data_wb_cyc_uart[gi]),
273
                        .wb_sel_i(data_wb_sel),
274
                        .wb_ack_o(data_wb_ack_uart[gi]),
275
                        .int_o   (uart_irq[gi]), // Interrupt.
276
 
277
                        // UART signals.
278
                        .srx_pad_i         (uart_in[gi]),
279
                        .stx_pad_o         (uart_out[gi]),
280
 
281
                        // Tied or open.
282
                        .rts_pad_o(),
283
                        .cts_pad_i(1'd0),
284
                        .dtr_pad_o(),
285
                        .dsr_pad_i(1'd0),
286
                        .ri_pad_i (1'd0),
287
                        .dcd_pad_i(1'd0)
288
                );
289
 
290
                timer u_timer (
291
                        .i_clk(i_clk),
292
                        .i_rst(i_reset),
293
                        .i_wb_adr(data_wb_adr),
294
                        .i_wb_dat(data_wb_dout),
295
                        .i_wb_stb(data_wb_stb_timer[gi]),
296
                        .i_wb_cyc(data_wb_cyc_timer[gi]),   // From core
297
                        .i_wb_wen(data_wb_we),
298
                        .i_wb_sel(data_wb_sel),
299
                        .o_wb_dat(data_wb_din_timer[gi]),   // To core.
300
                        .o_wb_ack(data_wb_ack_timer[gi]),
301
                        .o_irq(timer_irq[gi])               // Interrupt
302
                );
303
        end
304
end
305
endgenerate
306
 
307
// ===============================
308
// VIC
309
// ===============================
310
 
311
vic #(.SOURCES(32)) u_vic (
312
        .i_clk   (i_clk),
313
        .i_rst   (i_reset),
314
        .i_wb_adr(data_wb_adr),
315
        .i_wb_dat(data_wb_dout),
316
        .i_wb_stb(data_wb_stb_vic),
317
        .i_wb_cyc(data_wb_cyc_vic), // From core
318
        .i_wb_wen(data_wb_we),
319
        .i_wb_sel(data_wb_sel),
320
        .o_wb_dat(data_wb_din_vic), // To core.
321
        .o_wb_ack(data_wb_ack_vic),
322
        .i_irq({I_IRQ, timer_irq[1], uart_irq[1], timer_irq[0], uart_irq[0]}), // Concatenate 32 interrupt sources.
323
        .o_irq(global_irq)                                                   // Interrupt out
324
);
325
 
326
endmodule // chip_top

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