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[/] [zap/] [trunk/] [src/] [testbench/] [vic.v] - Blame information for rev 43

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1 43 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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//                                                                            --
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// A simple interrupt controller.                                             --
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//                                                                            --
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// Registers:                                                                 --
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// 0x0 - INT_STATUS - Interrupt status as reported by peripherals (sticky).   --
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// 0x4 - INT_MASK   - Interrupt mask - setting a bit to 1 masks the interrupt --
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// 0x8 - INT_CLEAR  - Write 1 to a particular bit to clear the interrupt      --
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//                    status.                                                 --
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//------------------------------------------------------------------------------
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`default_nettype none
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module vic #(
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        parameter [31:0]        SOURCES                    = 32'd4,
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        parameter [31:0]        INTERRUPT_PENDING_REGISTER = 32'h0,
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        parameter [31:0]        INTERRUPT_MASK_REGISTER    = 32'h4,
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        parameter [31:0]        INTERRUPT_CLEAR_REGISTER   = 32'h8
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) (
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// Clock and reset.
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input  wire                 i_clk,
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input  wire                 i_rst,
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// Wishbone interface.
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input  wire  [31:0]          i_wb_dat,
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input  wire   [3:0]          i_wb_adr,
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input  wire                  i_wb_stb,
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input  wire                  i_wb_cyc,
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input  wire                  i_wb_wen,
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input  wire  [3:0]           i_wb_sel,
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output reg  [31:0]           o_wb_dat,
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output reg                   o_wb_ack,
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// Interrupt sources in. Concatenate all
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// sources together.
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input wire   [SOURCES-1:0]       i_irq,
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// Interrupt output. Level interrupt.
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output  reg                  o_irq
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);
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`ifndef ZAP_SOC_VIC
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`define ZAP_SOC_VIC
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        `define INT_STATUS INTERRUPT_PENDING_REGISTER
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        `define INT_MASK   INTERRUPT_MASK_REGISTER
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        `define INT_CLEAR  INTERRUPT_CLEAR_REGISTER
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`endif
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reg [31:0] INT_STATUS;
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reg [31:0] INT_MASK;
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reg [31:0] wbstate;
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// Wishbone states.
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localparam WBIDLE       = 0;
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localparam WBREAD       = 1;
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localparam WBWRITE      = 2;
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localparam WBACK        = 3;
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localparam WBDONE       = 4;
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// Send out a global interrupt signal.
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always @ (posedge i_clk)
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begin
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        o_irq <= | ( INT_STATUS & ~INT_MASK );
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end
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// Wishbone access FSM
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always @ ( posedge i_clk )
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begin
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        if ( i_rst )
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        begin
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                wbstate         <= WBIDLE;
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                o_wb_dat        <= 0;
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                o_wb_ack        <= 0;
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                INT_MASK        <= 32'hffffffff;
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                INT_STATUS      <= 32'h0;
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        end
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        else
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        begin:blk1
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                integer i;
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                // Normally record interrupts. These are sticky bits.
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                for(i=0;i<SOURCES;i=i+1)
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                        INT_STATUS[i] <= INT_STATUS[i] == 0 ? i_irq[i] : 1'd1;
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                case(wbstate)
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                        WBIDLE:
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                        begin
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                                o_wb_ack <= 1'd0;
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                                if ( i_wb_stb && i_wb_cyc )
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                                begin
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                                        if ( i_wb_wen )
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                                                wbstate <= WBWRITE;
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                                        else
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                                                wbstate <= WBREAD;
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                                end
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                        end
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                        WBWRITE:
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                        begin
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                                case(i_wb_adr)
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                                `INT_MASK: // INT_MASK
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                                begin
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                                        $display($time, " - %m :: Writing to INT_MASK register...");
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                                        if ( i_wb_sel[0] ) INT_MASK[7:0]   <= i_wb_dat >> 0;
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                                        if ( i_wb_sel[1] ) INT_MASK[15:8]  <= i_wb_dat >> 8;
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                                        if ( i_wb_sel[2] ) INT_MASK[23:16] <= i_wb_dat >> 16;
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                                        if ( i_wb_sel[3] ) INT_MASK[31:24] <= i_wb_dat >> 24;
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                                end
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                                `INT_CLEAR: // INT_CLEAR
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                                begin: blk22
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                                        integer i;
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                                        $display($time, " - %m :: Writing to INT_CLEAR register...");
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                                        if ( i_wb_sel[0] ) for(i=0; i <=7;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
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                                        if ( i_wb_sel[1] ) for(i=8; i<=15;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
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                                        if ( i_wb_sel[2] ) for(i=16;i<=23;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
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                                        if ( i_wb_sel[3] ) for(i=24;i<=31;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
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                                end
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                                default: $display($time, " - %m :: Warning: Attemting to write to illgal register...");
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                                endcase
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                                wbstate <= WBACK;
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                        end
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                        WBREAD:
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                        begin
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                                case(i_wb_adr)
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                                `INT_STATUS:            o_wb_dat <= `INT_STATUS;
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                                `INT_MASK:              o_wb_dat <= `INT_MASK;
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                                default:
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                                begin
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                                        $display($time, " - %m --> Warning: Attempting to read from illegal register. Will return 0...");
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                                        o_wb_dat <= 0;
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                                end
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                                endcase
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                                wbstate <= WBACK;
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                        end
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                        WBACK:
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                        begin
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                                o_wb_ack   <= 1'd1;
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                                wbstate    <= WBDONE;
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                        end
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                        WBDONE:
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                        begin
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                                o_wb_ack   <= 1'd0;
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                                wbstate    <= WBIDLE;
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                        end
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                endcase
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        end
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end
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endmodule // vic
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`default_nettype wire

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