OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [testbench/] [zap_tb.v] - Blame information for rev 43

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 43 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
7
// -- This program is free software; you can redistribute it and/or           --
8
// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
11
// --                                                                         --
12
// -- This program is distributed in the hope that it will be useful,         --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
20
// -- 02110-1301, USA.                                                        --
21
// --                                                                         --
22
// -----------------------------------------------------------------------------
23
 
24
 
25
`default_nettype none
26
`include "zap_defines.vh"
27
 
28
module zap_test;
29
 
30
// CPU config.
31
parameter RAM_SIZE                      = 32768;
32
parameter DATA_SECTION_TLB_ENTRIES      = 4;
33
parameter DATA_LPAGE_TLB_ENTRIES        = 8;
34
parameter DATA_SPAGE_TLB_ENTRIES        = 16;
35
parameter DATA_CACHE_SIZE               = 1024;
36
parameter CODE_SECTION_TLB_ENTRIES      = 4;
37
parameter CODE_LPAGE_TLB_ENTRIES        = 8;
38
parameter CODE_SPAGE_TLB_ENTRIES        = 16;
39
parameter CODE_CACHE_SIZE               = 1024;
40
parameter FIFO_DEPTH                    = 4;
41
parameter BP_ENTRIES                    = 1024;
42
parameter STORE_BUFFER_DEPTH            = 32;
43
 
44
// TB related.
45
parameter START                         = 1992;
46
parameter COUNT                         = 120;
47
 
48
// Variables
49
reg             i_clk = 1'd0;
50
reg             i_reset = 1'd0;
51
wire [1:0]       uart_in;
52
wire [1:0]      uart_out;
53
integer         i;
54
reg [3:0]       clk_ctr = 4'd0;
55
integer         seed = `SEED;
56
integer         seed_new = `SEED + 1;
57
 
58
// Clock generator.
59
always #10      i_clk = !i_clk;
60
 
61
wire    w_wb_stb;
62
wire    w_wb_cyc;
63
wire [31:0] w_wb_dat_to_ram;
64
wire [31:0] w_wb_adr;
65
wire [3:0] w_wb_sel;
66
wire    w_wb_we;
67
wire    w_wb_ack;
68
wire [31:0] w_wb_dat_from_ram;
69
 
70
// DUT
71
chip_top #(
72
        .FIFO_DEPTH(FIFO_DEPTH),
73
        .BP_ENTRIES(BP_ENTRIES),
74
        .STORE_BUFFER_DEPTH(STORE_BUFFER_DEPTH),
75
        .DATA_SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES),
76
        .DATA_LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
77
        .DATA_SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
78
        .DATA_CACHE_SIZE(DATA_CACHE_SIZE),
79
        .CODE_SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES),
80
        .CODE_LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
81
        .CODE_SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES),
82
        .CODE_CACHE_SIZE(CODE_CACHE_SIZE)
83
 
84
) u_chip_top (
85
        .SYS_CLK  (i_clk),
86
        .SYS_RST  (i_reset),
87
        .UART0_RXD(uart_in[0]),
88
        .UART0_TXD(uart_out[0]),
89
        .UART1_RXD(uart_in[1]),
90
        .UART1_TXD(uart_out[1]),
91
        .I_IRQ    (28'd0),
92
        .I_FIQ    (1'd0),
93
        .O_WB_STB (w_wb_stb),
94
        .O_WB_CYC (w_wb_cyc),
95
        .O_WB_DAT (w_wb_dat_to_ram),
96
        .O_WB_ADR (w_wb_adr),
97
        .O_WB_SEL (w_wb_sel),
98
        .O_WB_WE  (w_wb_we),
99
        .I_WB_ACK (w_wb_ack),
100
        .I_WB_DAT (w_wb_dat_from_ram)
101
);
102
 
103
// RAM
104
ram #(.SIZE_IN_BYTES(RAM_SIZE)) u_ram (
105
        .i_clk(i_clk),
106
        .i_wb_stb (w_wb_stb),
107
        .i_wb_cyc (w_wb_cyc),
108
        .i_wb_dat (w_wb_dat_to_ram),
109
        .i_wb_adr (w_wb_adr),
110
        .i_wb_sel (w_wb_sel),
111
        .i_wb_we  (w_wb_we),
112
        .o_wb_ack (w_wb_ack),
113
        .o_wb_dat (w_wb_dat_from_ram)
114
);
115
 
116
// UART 0 dumper.
117
uart_tx_dumper #(.P(0)) UARTTX0 (
118
        .i_clk  (i_clk),
119
        .i_line (uart_out[0])
120
);
121
 
122
// UART 1 dumper.
123
uart_tx_dumper #(.P(1)) UARTTX1 (
124
        .i_clk  (i_clk),
125
        .i_line (uart_out[1])
126
);
127
 
128
// UART 0 logger.
129
uart_rx_logger #(.P(0)) UARTRX0 (
130
        .i_clk  (i_clk),
131
        .o_line (uart_in[0])
132
);
133
 
134
// UART 1 logger.
135
uart_rx_logger #(.P(1)) UARTRX1 (
136
        .i_clk  (i_clk),
137
        .o_line (uart_in[1])
138
);
139
 
140
// Run for MAX_CLOCK_CYCLES
141
initial
142
begin
143
        $display("SEED in decimal                         = %d", `SEED                          );
144
        $display("parameter RAM_SIZE                      = %d", RAM_SIZE                       );
145
        $display("parameter START                         = %d", START                          );
146
        $display("parameter COUNT                         = %d", COUNT                          );
147
        $display("parameter FIFO_DEPTH                    = %d", u_chip_top.FIFO_DEPTH          );
148
        $display("parameter DATA_SECTION_TLB_ENTRIES      = %d", DATA_SECTION_TLB_ENTRIES       ) ;
149
        $display("parameter DATA_LPAGE_TLB_ENTRIES        = %d", DATA_LPAGE_TLB_ENTRIES         ) ;
150
        $display("parameter DATA_SPAGE_TLB_ENTRIES        = %d", DATA_SPAGE_TLB_ENTRIES         ) ;
151
        $display("parameter DATA_CACHE_SIZE               = %d", DATA_CACHE_SIZE                ) ;
152
        $display("parameter CODE_SECTION_TLB_ENTRIES      = %d", CODE_SECTION_TLB_ENTRIES       ) ;
153
        $display("parameter CODE_LPAGE_TLB_ENTRIES        = %d", CODE_LPAGE_TLB_ENTRIES         ) ;
154
        $display("parameter CODE_SPAGE_TLB_ENTRIES        = %d", CODE_SPAGE_TLB_ENTRIES         ) ;
155
        $display("parameter CODE_CACHE_SIZE               = %d", CODE_CACHE_SIZE                ) ;
156
        $display("parameter STORE_BUFFER_DEPTH            = %d", STORE_BUFFER_DEPTH             ) ;
157
 
158
        `ifdef WAVES
159
                $dumpfile(`VCD_FILE_PATH);
160
                $dumpvars;
161
        `endif
162
 
163
        @(posedge i_clk);
164
        i_reset <= 1;
165
        @(posedge i_clk);
166
        i_reset <= 0;
167
 
168
        if (`MAX_CLOCK_CYCLES == 0 )
169
        begin
170
                forever @(negedge i_clk);
171
        end
172
        else
173
        begin
174
                repeat(`MAX_CLOCK_CYCLES)
175
                        @(negedge i_clk);
176
        end
177
 
178
       `include "zap_check.vh"
179
end
180
 
181
endmodule // zap_tb
182
 
183
`default_nettype wire

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.