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[/] [zap/] [trunk/] [src/] [ts/] [factorial/] [factorial.s] - Blame information for rev 38

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Line No. Rev Author Line
1 29 Revanth
//
2 26 Revanth
// Startup file for factorial.
3 29 Revanth
//
4 26 Revanth
 
5
.global _Reset
6
 
7
// Set up an interrupt vector table.
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_Reset   : b there
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_Undef   : b UNDEF
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_Swi     : b SWI
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_Pabt    : b __pabt
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_Dabt    : b __dabt
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reserved : b _Reset
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irq      : b IRQ
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fiq      : b FIQ
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17
UNDEF:
18 29 Revanth
 
19 26 Revanth
// Undefined vector.
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// LR Points to next instruction.
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stmfa sp!, {r0-r12, r14}
22 29 Revanth
 
23 26 Revanth
// Corrupt registers.
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mov r0, #1
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mov r1, #2
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mov r2, #3
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mov r3, #4
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mov r4, #5
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mov r5, #6
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mov r6, #7
31
mov r7, #8
32
mov r8, #9
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mov r9, #10
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mov r10, #12
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mov r11, #13
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mov r12, #14
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mov r14, #15
38 29 Revanth
 
39 26 Revanth
// Restore them.
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ldmfa sp!, {r0-r12, pc}^
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// IRQ.
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IRQ:
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sub r14, r14, #4
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stmfd sp!, {r0-r12, r14}
46 29 Revanth
 
47 26 Revanth
mov r0, #1
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mov r1, #2
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mov r2, #3
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mov r3, #4
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mov r4, #5
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mov r5, #6
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mov r6, #7
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mov r7, #8
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mov r8, #9
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mov r9, #10
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mov r10, #12
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mov r11, #13
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mov r12, #14
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mov r14, #15
61 29 Revanth
 
62
# Restart timer
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ldr r0 ,=#0xFFFFFFC0    // Timer base address.
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add r0, r0, #12
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ldr r1, =#0x1
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str r1, [r0]            // Restart the timer.
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# Clear interrupt in VIC.
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ldr r0, =#0xFFFFFFA0    // VIC base address
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add r0, r0, #8
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ldr r1, =#0xFFFFFFFF
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str r1, [r0]            // Clear all interrupt pending status
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74 26 Revanth
ldmfd sp!, {r0-r12, pc}^
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FIQ:
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# Return from FIQ after writing to FIQ registers.
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mov r8,  #9
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mov r9,  #10
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mov r10, #12
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mov r11, #13
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mov r12, #14
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #10
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mov r12, #0
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subs pc, r14, #4
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SWI:
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ldr sp,=#2500
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ldr r11, =#2004
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mov r0, #12
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mov r1, #0
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mov r2, r0, lsr #32
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mov r3, r0, lsr r1
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mov r4, #-1
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mov r5, #-1
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muls r6, r5, r4
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umull r8,  r7, r5, r4
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smull r10, r9, r5, r4
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mov r2, r10
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str r10, [r11, #4]!
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str r9,  [r11, #4]!
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add r11, r11, #4
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str r8,  [r11], #4
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str r7,  [r11], #4
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str r6,  [r11]
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stmib r11, {r6-r10}
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stmfd sp!, {r0-r12, r14}
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mrs r1, spsr
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orr r1, r1, #0x80
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msr spsr_c, r1
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mov r4, #0
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mcr p15, 0, r4, c7, c15, 0
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mov r4, #-1
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ldmfd sp!, {r0-r12, pc}^
118
 
119
there:
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// Switch to IRQ mode.
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mrs r2, cpsr
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bic r2, r2, #31
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orr r2, r2, #18
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msr cpsr_c, r2
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ldr sp, =#3000
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// Switch to UND mode.
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mrs r3, cpsr
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bic r3, r3, #31
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orr r3, r3, #27
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msr cpsr_c, r3
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mov r4, #1
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ldr sp, =#3500
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// Enable interrupts (FIQ and IRQ).
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mrs r1, cpsr
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bic r1, r1, #0xC0
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msr cpsr_c, r1
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// Enable cache (Uses a single bit to enable both caches).
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ldr r1, =#4100
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mcr p15, 0, r1, c1, c1, 0
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// Write out identitiy section mapping. Write 16KB to register 2.
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mov r1, #1
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mov r1, r1, lsl #14
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mcr p15, 0, r1, c2, c0, 1
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// Set domain access control to all 1s.
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mvn r1, #0
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mcr p15, 0, r1, c3, c0, 0
152
 
153
// Set up a section desctiptor for identity mapping that is Cachaeable.
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mov r1, #1
155 29 Revanth
mov r1, r1, lsl #14     // 16KB
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mov r2, #14             // Cacheable identity descriptor.
157
str r2, [r1]            // Write identity section desctiptor to 16KB location.
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ldr r6, [r1]            // R6 holds the descriptor.
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mov r7, r1              // R7 holds the address.
160
 
161
// Set up a section descriptor for upper 1MB of virtual address space.
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// This is identity mapping. Uncacheable.
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mov r1, #1
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mov r1, r1, lsl #14     // 16KB. This is descriptor 0.
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// Go to descriptor 4095. This is the address BASE + (#DESC * 4).
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ldr r2,=#16380
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add r1, r1, r2
168
// Prepare a descriptor. Descriptor = 0xFFF00002 (Uncacheable section descriptor).
169
ldr r2 ,=#0xFFF00002
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str r2, [r1]
171 26 Revanth
ldr r6, [r1]
172
mov r7, r1
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174
// ENABLE MMU
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ldr r1, =#4101
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mcr p15, 0, r1, c1, c1, 0
177
 
178
// Switch mode.
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mrs r2, cpsr
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bic r2, r2, #31
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orr r2, r2, #16
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msr cpsr_c, r2
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ldr sp,=#3500
184
 
185
// Run main loop.
186 29 Revanth
 
187
// Program VIC to allow timer interrupts.
188
ldr r0, =#0xFFFFFFA0    // VIC base address.
189
add r0, r0, #4          // Move to INT_MASK
190
ldr r1, =#0x0           // Prepare mask value
191
str r1, [r0]            // Unmask all interrupt sources.
192
 
193 38 Revanth
// Program timer peripheral to tick every 32 clock cycles.
194 29 Revanth
ldr r0 ,=#0xFFFFFFC0    // Timer base address.
195
ldr r1 ,=#1
196
str r1, [r0]            // Enable timer
197
add r0, r0, #4
198 38 Revanth
ldr r1, =#32
199 29 Revanth
str r1, [r0]            // Program to 255 clocks.
200
add r0, r0, #8
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ldr r1, =#0x1
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str r1, [r0]            // Start the timer.
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204
 
205 26 Revanth
bl main
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swi #0x00
207
here: b here
208
 

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