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[/] [zet86/] [trunk/] [cores/] [zet/] [rtl/] [cpu.v] - Blame information for rev 55

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1 17 zeus
/*
2
 *  Copyright (c) 2008  Zeus Gomez Marmolejo <zeus@opencores.org>
3
 *
4
 *  This file is part of the Zet processor. This processor is free
5
 *  hardware; you can redistribute it and/or modify it under the terms of
6
 *  the GNU General Public License as published by the Free Software
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 *  Foundation; either version 3, or (at your option) any later version.
8
 *
9 18 zeus
 *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11
 *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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 *  License for more details.
13 17 zeus
 *
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 *  You should have received a copy of the GNU General Public License
15 18 zeus
 *  along with Zet; see the file COPYING. If not, see
16 17 zeus
 *  <http://www.gnu.org/licenses/>.
17
 */
18
 
19 2 zeus
`timescale 1ns/10ps
20
 
21
`include "defines.v"
22
 
23 14 zeus
module cpu (
24 21 zeus
`ifdef DEBUG
25
    output [15:0] cs,
26
    output [15:0] ip,
27
    output [ 2:0] state,
28
    output [ 2:0] next_state,
29
    output [ 5:0] iralu,
30
    output [15:0] x,
31
    output [15:0] y,
32
    output [15:0] imm,
33 27 zeus
    output [15:0] aluo,
34 45 zeus
    output [15:0] ax,
35
    output [15:0] dx,
36
    output [15:0] bp,
37
    output [15:0] si,
38
    output [15:0] es,
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    input         dbg_block,
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    output [15:0] c,
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    output [ 3:0] addr_c,
42
    output [15:0] cpu_dat_o,
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    output [15:0] d,
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    output [ 3:0] addr_d,
45
    output        byte_exec,
46
    output [ 8:0] flags,
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    output        end_seq,
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    output        ext_int,
49
    output        cpu_block,
50 21 zeus
`endif
51
 
52 35 zeus
    // Wishbone master interface
53
    input         wb_clk_i,
54
    input         wb_rst_i,
55
    input  [15:0] wb_dat_i,
56
    output [15:0] wb_dat_o,
57
    output [19:1] wb_adr_o,
58
    output        wb_we_o,
59 42 zeus
    output        wb_tga_o,  // io/mem
60 35 zeus
    output [ 1:0] wb_sel_o,
61
    output        wb_stb_o,
62
    output        wb_cyc_o,
63 42 zeus
    input         wb_ack_i,
64
    input         wb_tgc_i,  // intr
65
    output        wb_tgc_o   // inta
66 2 zeus
  );
67
 
68
  // Net declarations
69 21 zeus
`ifndef DEBUG
70
  wire [15:0] cs, ip;
71
  wire [15:0] imm;
72 45 zeus
  wire [15:0] cpu_dat_o;
73
  wire        byte_exec;
74
  wire        cpu_block;
75 21 zeus
`endif
76 2 zeus
  wire [`IR_SIZE-1:0] ir;
77 21 zeus
  wire [15:0] off;
78
 
79 2 zeus
  wire [19:0] addr_exec, addr_fetch;
80 45 zeus
  wire byte_fetch, fetch_or_exec;
81 2 zeus
  wire of, zf, cx_zero;
82 30 zeus
  wire div_exc;
83 32 zeus
  wire wr_ip0;
84 42 zeus
  wire ifl;
85 2 zeus
 
86 35 zeus
  wire        cpu_byte_o;
87
  wire        cpu_m_io;
88
  wire [19:0] cpu_adr_o;
89 45 zeus
  wire        wb_block;
90 35 zeus
  wire [15:0] cpu_dat_i;
91
  wire        cpu_we_o;
92 42 zeus
  wire [15:0] iid_dat_i;
93 35 zeus
 
94 2 zeus
  // Module instantiations
95 21 zeus
  fetch fetch0 (
96
`ifdef DEBUG
97
    .state      (state),
98
    .next_state (next_state),
99 45 zeus
    .ext_int    (ext_int),
100
    .end_seq    (end_seq),
101 21 zeus
`endif
102 35 zeus
    .clk  (wb_clk_i),
103
    .rst  (wb_rst_i),
104 21 zeus
    .cs   (cs),
105
    .ip   (ip),
106
    .of   (of),
107
    .zf   (zf),
108 35 zeus
    .data (cpu_dat_i),
109 21 zeus
    .ir   (ir),
110
    .off  (off),
111
    .imm  (imm),
112
    .pc   (addr_fetch),
113 2 zeus
 
114 21 zeus
    .cx_zero       (cx_zero),
115
    .bytefetch     (byte_fetch),
116
    .fetch_or_exec (fetch_or_exec),
117 35 zeus
    .block         (cpu_block),
118 30 zeus
    .div_exc       (div_exc),
119 32 zeus
 
120 42 zeus
    .wr_ip0  (wr_ip0),
121
 
122 45 zeus
    .intr (wb_tgc_i),
123
    .ifl  (ifl),
124 42 zeus
    .inta (wb_tgc_o)
125 21 zeus
  );
126
 
127
  exec exec0 (
128
`ifdef DEBUG
129 27 zeus
    .x    (x),
130
    .y    (y),
131
    .aluo (aluo),
132 45 zeus
    .ax   (ax),
133
    .dx   (dx),
134
    .bp   (bp),
135
    .si   (si),
136
    .es   (es),
137
    .c    (c),
138
    .addr_c (addr_c),
139
    .omemalu (d),
140
    .addr_d (addr_d),
141
    .flags  (flags),
142 21 zeus
`endif
143
    .ir      (ir),
144
    .off     (off),
145
    .imm     (imm),
146
    .cs      (cs),
147
    .ip      (ip),
148
    .of      (of),
149
    .zf      (zf),
150
    .cx_zero (cx_zero),
151 35 zeus
    .clk     (wb_clk_i),
152
    .rst     (wb_rst_i),
153 42 zeus
    .memout  (iid_dat_i),
154 35 zeus
    .wr_data (cpu_dat_o),
155 21 zeus
    .addr    (addr_exec),
156 35 zeus
    .we      (cpu_we_o),
157
    .m_io    (cpu_m_io),
158 21 zeus
    .byteop  (byte_exec),
159 35 zeus
    .block   (cpu_block),
160 30 zeus
    .div_exc (div_exc),
161 42 zeus
    .wrip0   (wr_ip0),
162
 
163
    .ifl     (ifl)
164 21 zeus
  );
165
 
166 35 zeus
  wb_master wm0 (
167
    .cpu_byte_o (cpu_byte_o),
168
    .cpu_memop  (ir[`MEM_OP]),
169
    .cpu_m_io   (cpu_m_io),
170
    .cpu_adr_o  (cpu_adr_o),
171 45 zeus
    .cpu_block  (wb_block),
172 35 zeus
    .cpu_dat_i  (cpu_dat_i),
173
    .cpu_dat_o  (cpu_dat_o),
174
    .cpu_we_o   (cpu_we_o),
175
 
176
    .wb_clk_i  (wb_clk_i),
177
    .wb_rst_i  (wb_rst_i),
178
    .wb_dat_i  (wb_dat_i),
179
    .wb_dat_o  (wb_dat_o),
180
    .wb_adr_o  (wb_adr_o),
181
    .wb_we_o   (wb_we_o),
182
    .wb_tga_o  (wb_tga_o),
183
    .wb_sel_o  (wb_sel_o),
184
    .wb_stb_o  (wb_stb_o),
185
    .wb_cyc_o  (wb_cyc_o),
186
    .wb_ack_i  (wb_ack_i)
187
  );
188
 
189 21 zeus
  // Assignments
190 35 zeus
  assign cpu_adr_o  = fetch_or_exec ? addr_exec : addr_fetch;
191
  assign cpu_byte_o = fetch_or_exec ? byte_exec : byte_fetch;
192 42 zeus
  assign iid_dat_i  = wb_tgc_o ? wb_dat_i : cpu_dat_i;
193 21 zeus
 
194
`ifdef DEBUG
195
  assign iralu = ir[28:23];
196 45 zeus
  assign cpu_block = wb_block | dbg_block;
197
`else
198
  assign cpu_block = wb_block;
199 21 zeus
`endif
200 2 zeus
endmodule
201 35 zeus
 
202
module wb_master (
203
    input             cpu_byte_o,
204
    input             cpu_memop,
205
    input             cpu_m_io,
206
    input      [19:0] cpu_adr_o,
207
    output reg        cpu_block,
208
    output reg [15:0] cpu_dat_i,
209
    input      [15:0] cpu_dat_o,
210
    input             cpu_we_o,
211
 
212
    input             wb_clk_i,
213
    input             wb_rst_i,
214
    input      [15:0] wb_dat_i,
215
    output     [15:0] wb_dat_o,
216
    output reg [19:1] wb_adr_o,
217
    output            wb_we_o,
218
    output            wb_tga_o,
219
    output reg [ 1:0] wb_sel_o,
220
    output reg        wb_stb_o,
221
    output reg        wb_cyc_o,
222
    input             wb_ack_i
223
  );
224
 
225
  // Register and nets declarations
226
  reg  [ 1:0] cs; // current state
227 53 zeus
  reg  [ 1:0] ns; // next state
228 35 zeus
 
229
  wire        op; // in an operation
230
  wire        odd_word; // unaligned word
231
  wire        a0;  // address 0 pin
232
  wire [15:0] blw; // low byte (sign extended)
233
  wire [15:0] bhw; // high byte (sign extended)
234
  wire [19:1] adr1; // next address (for unaligned acc)
235
  wire [ 1:0] sel_o; // bus byte select
236
 
237
  // Declare the symbolic names for states
238 53 zeus
  localparam [1:0]
239
    IDLE = 2'd0,
240
    stb1_lo = 2'd1,
241
    stb2_hi = 2'd2;
242 35 zeus
 
243
  // Assignments
244
  assign op       = (cpu_memop | cpu_m_io);
245
  assign odd_word = (cpu_adr_o[0] & !cpu_byte_o);
246
  assign a0       = cpu_adr_o[0];
247
  assign blw      = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
248
  assign bhw      = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
249
  assign adr1     = a0 ? (cpu_adr_o[19:1] + 1'b1)
250
                       : cpu_adr_o[19:1];
251
  assign wb_dat_o = a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
252
                       : cpu_dat_o;
253
  assign wb_we_o  = cpu_we_o;
254
  assign wb_tga_o = cpu_m_io;
255
  assign sel_o    = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
256
 
257
  // Behaviour
258
  // cpu_dat_i
259
  always @(posedge wb_clk_i)
260 53 zeus
    cpu_dat_i <= (cs == IDLE) ?
261 35 zeus
                   (wb_ack_i ?
262
                     (a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
263
                   : cpu_dat_i)
264
                 : ((cs == stb1_lo && wb_ack_i) ?
265
                     { wb_dat_i[7:0], cpu_dat_i[7:0] }
266
                   : cpu_dat_i);
267
 
268
  // outputs setup
269
  always @(*)
270
    case (cs)
271
      default:
272
        begin
273
          cpu_block <= op;
274
          wb_adr_o  <= cpu_adr_o[19:1];
275
          wb_sel_o  <= sel_o;
276
          wb_stb_o  <= op;
277
          wb_cyc_o  <= op;
278
        end
279
      stb1_lo:
280
        begin
281
          cpu_block <= 1'b1;
282
          wb_adr_o  <= adr1;
283
          wb_sel_o  <= 2'b01;
284
          wb_stb_o  <= 1'b1;
285
          wb_cyc_o  <= 1'b1;
286
        end
287
      stb2_hi:
288
        begin
289
          cpu_block <= wb_ack_i;
290
          wb_adr_o  <= adr1;
291
          wb_sel_o  <= 2'b01;
292
          wb_stb_o  <= 1'b0;
293
          wb_cyc_o  <= 1'b0;
294
        end
295
    endcase
296
 
297
  // state machine
298 53 zeus
  // cs - current state
299 35 zeus
  always @(posedge wb_clk_i)
300 53 zeus
    cs <= wb_rst_i ? IDLE : ns;
301 35 zeus
 
302 53 zeus
  // ns - next state
303
  always @(*)
304
    case (cs)
305
      default:  ns <= wb_ack_i ?
306
                      (op ? (odd_word ? stb1_lo : stb2_hi) : IDLE)
307
                    : IDLE;
308
      stb1_lo:  ns <= wb_ack_i ? stb2_hi : stb1_lo;
309
      stb2_hi:  ns <= wb_ack_i ? stb2_hi : IDLE;
310
    endcase
311
 
312 35 zeus
endmodule

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