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[/] [zet86/] [trunk/] [cores/] [zet/] [rtl/] [regfile.v] - Blame information for rev 55

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1 17 zeus
/*
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 *  Copyright (c) 2008  Zeus Gomez Marmolejo <zeus@opencores.org>
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 *
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 *  This file is part of the Zet processor. This processor is free
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 *  hardware; you can redistribute it and/or modify it under the terms of
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 *  the GNU General Public License as published by the Free Software
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 *  Foundation; either version 3, or (at your option) any later version.
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 *
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 *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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 *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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 *  License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with Zet; see the file COPYING. If not, see
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 *  <http://www.gnu.org/licenses/>.
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 */
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19 2 zeus
`timescale 1ns/10ps
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21 37 zeus
`include "defines.v"
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23 30 zeus
module regfile (
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`ifdef DEBUG
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    output [15:0] ax,
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    output [15:0] dx,
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    output [15:0] bp,
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    output [15:0] si,
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    output [15:0] es,
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`endif
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    output [15:0] a,
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    output [15:0] b,
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    output [15:0] c,
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    output [15:0] cs,
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    output [15:0] ip,
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    input  [31:0] d,
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    output [15:0] s,
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40 30 zeus
    output reg [8:0] flags,
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    input         wr,
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    input         wrfl,
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    input         wrhi,
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    input         clk,
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    input         rst,
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    input  [ 3:0] addr_a,
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    input  [ 3:0] addr_b,
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    input  [ 3:0] addr_c,
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    input  [ 3:0] addr_d,
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    input  [ 1:0] addr_s,
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    input  [ 8:0] iflags,
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    input         word_op,
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    input         a_byte,
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    input         b_byte,
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    input         c_byte,
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    output        cx_zero,
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    input         wr_ip0
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  );
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  // Net declarations
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  reg [15:0] r[15:0];
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  wire [7:0] a8, b8, c8;
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  // Assignments
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`ifdef DEBUG
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  assign ax = r[0];
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  assign dx = r[2];
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  assign bp = r[5];
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  assign si = r[6];
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  assign es = r[8];
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`endif
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  assign a = (a_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
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  assign a8 = addr_a[2] ? r[addr_a[1:0]][15:8] : r[addr_a][7:0];
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  assign b = (b_byte & ~addr_b[3]) ? { {8{b8[7]}}, b8} : r[addr_b];
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  assign b8 = addr_b[2] ? r[addr_b[1:0]][15:8] : r[addr_b][7:0];
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  assign c = (c_byte & ~addr_c[3]) ? { {8{c8[7]}}, c8} : r[addr_c];
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  assign c8 = addr_c[2] ? r[addr_c[1:0]][15:8] : r[addr_c][7:0];
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  assign s = r[{2'b10,addr_s}];
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  assign cs = r[9];
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  assign cx_zero = (addr_d==4'd1) ? (d==16'd0) : (r[1]==16'd0);
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  assign ip = r[15];
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  // Behaviour
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  always @(posedge clk)
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    if (rst) begin
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      r[0]  <= 16'd0; r[1]  <= 16'd0;
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      r[2]  <= 16'd0; r[3]  <= 16'd0;
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      r[4]  <= 16'd0; r[5]  <= 16'd0;
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      r[6]  <= 16'd0; r[7]  <= 16'd0;
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      r[8]  <= 16'd0; r[9]  <= 16'hf000;
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      r[10] <= 16'd0; r[11] <= 16'd0;
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      r[12] <= 16'd0; r[13] <= 16'd0;
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      r[14] <= 16'd0; r[15] <= 16'hfff0;
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      flags <= 9'd0;
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    end else
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      begin
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        if (wr) begin
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          if (word_op | addr_d[3:2]==2'b10)
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             r[addr_d] <= word_op ? d[15:0] : {{8{d[7]}},d[7:0]};
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          else if (addr_d[3]~^addr_d[2]) r[addr_d][7:0] <= d[7:0];
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          else r[{2'b0,addr_d[1:0]}][15:8] <= d[7:0];
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        end
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        if (wrfl) flags <= iflags;
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        if (wrhi) r[4'd2] <= d[31:16];
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        if (wr_ip0) r[14] <= ip;
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      end
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endmodule

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