OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [Makefile] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 dgisselq
################################################################################
2
#
3
# Filename:     Makefile
4
#
5
# Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
6
#
7
# Purpose:      This is a grand makefile for the entire project.  It will
8
#               build the assembler, and a Verilog testbench, and then
9
#               even test the CPU via that test bench.
10
#
11
#       Targets include:
12
#
13
#               bench   Build the CPP test bench/debugger facility.
14
#
15
#               rtl     Run Verilator on the RTL
16
#
17
#               sw      Build the assembler.
18
#
19
#               test    Run the test bench on the assembler test file.
20
#
21
#
22
# Creator:      Dan Gisselquist, Ph.D.
23
#               Gisselquist Tecnology, LLC
24
#
25
################################################################################
26
#
27
# Copyright (C) 2015, Gisselquist Technology, LLC
28
#
29
# This program is free software (firmware): you can redistribute it and/or
30
# modify it under the terms of  the GNU General Public License as published
31
# by the Free Software Foundation, either version 3 of the License, or (at
32
# your option) any later version.
33
#
34
# This program is distributed in the hope that it will be useful, but WITHOUT
35
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
36
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
37
# for more details.
38
#
39
# License:      GPL, v3, as defined and found on www.gnu.org,
40
#               http://www.gnu.org/licenses/gpl.html
41
#
42
#
43
################################################################################
44
#
45
.PHONY: all
46
all: rtl sw bench
47
 
48
.PHONY: rtl
49
rtl:
50
        cd rtl; make
51
 
52
.PHONY: sw
53
sw:
54
        cd sw/zasm; make
55
 
56
.PHONY: bench
57
bench:  rtl
58
        cd bench/cpp; make
59
 
60
test: sw rtl
61
        cd sw/zasm; make test
62
        cd bench/cpp; make test
63
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.