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[/] [zipcpu/] [trunk/] [Makefile] - Blame information for rev 48

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Line No. Rev Author Line
1 28 dgisselq
################################################################################
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#
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# Filename:     Makefile
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#
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# Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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#
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# Purpose:      This is a grand makefile for the entire project.  It will
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#               build the assembler, and a Verilog testbench, and then
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#               even test the CPU via that test bench.
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#
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#       Targets include:
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#
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#               bench   Build the CPP test bench/debugger facility.
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#
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#               rtl     Run Verilator on the RTL
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#
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#               sw      Build the assembler.
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#
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#               test    Run the test bench on the assembler test file.
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#
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#
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# Creator:      Dan Gisselquist, Ph.D.
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#               Gisselquist Tecnology, LLC
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#
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################################################################################
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#
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# Copyright (C) 2015, Gisselquist Technology, LLC
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#
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# This program is free software (firmware): you can redistribute it and/or
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# modify it under the terms of  the GNU General Public License as published
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# by the Free Software Foundation, either version 3 of the License, or (at
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# your option) any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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# for more details.
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#
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# License:      GPL, v3, as defined and found on www.gnu.org,
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#               http://www.gnu.org/licenses/gpl.html
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#
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#
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################################################################################
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#
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.PHONY: all
46 36 dgisselq
all: doc rtl sw bench
47 28 dgisselq
 
48 36 dgisselq
.PHONY: doc
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doc:
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        cd doc; make
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52 28 dgisselq
.PHONY: rtl
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rtl:
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        cd rtl; make
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.PHONY: sw
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sw:
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        cd sw/zasm; make
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.PHONY: bench
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bench:  rtl
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        cd bench/cpp; make
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test: sw rtl
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        cd sw/zasm; make test
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        cd bench/cpp; make test
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