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[/] [zipcpu/] [trunk/] [bench/] [asm/] [ivec.S] - Blame information for rev 187

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename:     ivec.S
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;
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; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose:      Just to test whether or not a timer works as desired.  This
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;               will set the timer to interrupt every millisecond, and then
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;               update a counter on every interrupt.
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;
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;               On any failure, the processor will execute a BUSY command.
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;
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; Creator:      Dan Gisselquist, Ph.D.
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;               Gisselquist Technology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of  the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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; for more details.
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;
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; License:      GPL, v3, as defined and found on www.gnu.org,
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;               http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Registers:
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;       sR0     Peripheral address
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;       sR2     Interrupt controller command
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;       sR3     Timer peripheral command
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;       sR4     User program entry address (Could also be (re)entry address,
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;                       but isn't in this implementation)
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;       sR5     Whether or not we've gotten the first interrupt
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;       sR6     Number of times we've been interrupted
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;       sR7     Number of times R6 has overflowed
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reset:
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        CLR     R0              ; Load the address of the interrupt controller
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        LDIHI   $c000h,R0       ; into R0
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        LDI     $-1,R2          ; Acknowledge and disable all interrupts
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        LDIHI   $7fffh,R2       ;
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        STO     R2,(R0)         ;
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        ; Set the timer for a programmaable interrupt, every 100k clocks,
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        ; or roughly 1,000 times a second on a 100 MHz clock.
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        LDIHI   $0xc001h,R3     ; R3 = 100k, save that the top two bits are
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        LDILO   $0x86a0h,R3     ; also set (start timer, and auto reload)
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        STO     R3,$6(C0)
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        ; Now that timer-C is set, let's enable it's interrupts
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        LDIHI   $8004h,R2       ; Leaving the bottom all ones acknowledges and
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        STO     R2,(R0)         ; clears any interrupts (again)
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        ; Clear our counter variables
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        CLR     R5
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        CLR     R6
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        CLR     R7
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        ; Program our wait for interrupt routine
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        MOV     $8(PC),R4
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        MOV     R4,uPC
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        RTU
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on_first_interrupt:
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        ADD     $1,R5
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setup_for_next_interrupt:
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        RTU
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on_subsequent_interrupt:
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        ADD     $1,R6
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        ADD.C   $1,R7
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        BRA     $-4
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haltcpu:
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        BUSY                    ; We've failed if we ever get here
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waitforinterrupt:
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        WAIT
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        BRA     $-2
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        MOV     $0,R0
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        MOV     $0,R0
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        BUSY

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