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[/] [zipcpu/] [trunk/] [bench/] [asm/] [nullpc.s] - Blame information for rev 187

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Line No. Rev Author Line
1 74 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename:     nullpc.s
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;
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; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose:      A quick test of whether or not the prefetch shuts down and
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;               idles properly when given an invalid (NULL) address.  This is
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;       intended to be run in the simulator (zippy_tb), as I don't know how I
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;       would verify operation on a real device.
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;
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; Creator:      Dan Gisselquist, Ph.D.
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;               Gisselquist Technology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of  the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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; for more details.
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;
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; License:      GPL, v3, as defined and found on www.gnu.org,
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;               http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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start:
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        CLR     R0
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        CLR     R1
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        CLR     R2
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        CLR     R3
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        CLR     R4
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        MOV     R0,uR0
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        MOV     R0,uR1
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        MOV     R0,uR2
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        MOV     R0,uR3
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        MOV     R0,uR4
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        MOV     user_start(PC),uPC
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        MOV     R0,uCC
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        RTU
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        MOV     uCC,R0
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        TST     0x100,R0
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        BNZ     user_test_worked
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        ; We could do a BUSY.Z, but then the simulator wouldn't have
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        ; picked up our stop condition
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        BUSY
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user_test_worked:
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        MOV     user_dive_test(PC),uPC
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        RTU
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        MOV     uCC,R0
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        TST     0x0800,R0
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        BRA     user_dive_worked
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        BUSY
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user_dive_worked:
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        ; Finally, let's test whether or not a null address from supervisor
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        ; mode halts the CPU as desired.
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        JMP     R1
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        NOOP
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        NOOP
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        ; HALT = success.  However, if we halt here we certainly don't have
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        ; a success.  Hence, signal a test failure by calling a busy instruction
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        BUSY
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; Let's see if jumping to a null address creates the exception we want
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user_start:
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        JMP     R1
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        NOOP
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        NOOP
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; How about divide by zero?
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user_dive_test:
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        LDI     25,R0
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        CLR     R1
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        CLR     R2
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        DIVS    R1,R0
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        ADD     1,R2
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        ADD     1,R2
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        ADD     1,R2
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        ADD     1,R2
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        ADD     1,R2
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        BUSY

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