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[/] [zipcpu/] [trunk/] [bench/] [asm/] [poptest.s] - Blame information for rev 187

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Line No. Rev Author Line
1 74 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename:     poptest.s
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;
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; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose:      Testing whether or not the new popcount (POPC) and bit reversal
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;               (BREV) operations work by using software to duplicate these
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;       instructions and then comparing the software result to the actual
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;       harddware result.  As of the first half billion values, this works.
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;       (I'm still running on the rest ....)
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;
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; Creator:      Dan Gisselquist, Ph.D.
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;               Gisselquist Technology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of  the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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; for more details.
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;
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; License:      GPL, v3, as defined and found on www.gnu.org,
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;               http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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#define LFSRFILL        0x000001
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#define LFSRTAPS        0x0408b85
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master_entry:
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        MOV     user_entry(PC),uPC
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        MOV     stack(PC),uSP
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        ;
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        RTU
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        ; 
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        HALT
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user_entry:
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        ; LDI   LFSRFILL,R6
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        ; LDI   LFSRTAPS,R7
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        CLR     R6
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        LDI     1,R7
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        CLR     R8
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        CLR     R12
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function_test_loop:
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        ; Pseudorandom number generator
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        ; LSR   1,R6
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        ; XOR.C R7,R6
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        ; In order number generator
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        ADD     R7,R6
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        MOV     R6,R0
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        ADD     1,R8
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        POPC    R0,R4
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        BREV    R0,R5
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        MOV     2+__HERE__(PC),R1
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        BRA     sw_pop_count
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        CMP     R0,R4
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        ADD.NZ  1,R12
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        TRAP.NZ 0
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        MOV     R6,R0
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        MOV     2+__HERE__(PC),R1
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        BRA     sw_reverse_bit_order
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        CMP     R0,R5
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        ADD.NZ  2,R12
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        TRAP.NZ 0x01000
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        ;       
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        ; CMP   LFSRFILL,R6
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        ; TRAP.Z        0
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        ;
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        CMP     0,R6
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        TRAP.Z  0
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        BRA     function_test_loop
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sw_pop_count:
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        ; On entry, R0 = value of interest
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        ;               R1 = return address
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        ; On exit, R0 = result
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        ;               R1 = return address
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        SUB     2,SP
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        STO     R1,(SP)         ; R1 will be our loop counter
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        STO     R2,1(SP)        ; R2 will be our accumulator and eventual result
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        CLR     R2
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sw_pop_count_loop:
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        LSR     1,R0
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        ADD.C   1,R2
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        BZ      sw_pop_count_exit
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        BRA     sw_pop_count_loop
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sw_pop_count_exit:
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        MOV     R2,R0
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        LOD     (SP),R1
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        LOD     1(SP),R2
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        ADD     2,SP
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        JMP     R1
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sw_reverse_bit_order:
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        ; On entry, R0 = value of interest
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        ;               R1 = return address
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        ; On exit, R0 = result
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        ;               R1 = return address
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        SUB     2,SP
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        STO     R1,(SP)         ; R1 will be our loop counter
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        STO     R2,1(SP)        ; R2 will be our accumulator and eventual result
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        LDI     32,R1
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        CLR     R2
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reverse_bit_order_loop:
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        LSL     1,R2
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        LSR     1,R0
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        OR.C    1,R2
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        SUB     1,R1
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        BZ      reverse_bit_order_exit
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        BRA     reverse_bit_order_loop
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reverse_bit_order_exit:
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        MOV     R2,R0
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        LOD     (SP),R1
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        LOD     1(SP),R2
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        ADD     2,SP
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        JMP     R1
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        fill    512,0
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stack:  // Must point to a valid word initially
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        word    0

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