OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [memsim.h] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    memsim.h
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU core
6
//
7
// Purpose:     This creates a memory like device to act on a WISHBONE bus.
8
//              It doesn't exercise the bus thoroughly, but does give some
9
//              exercise to the bus to see whether or not the bus master
10
//              can control it.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
////////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// You should have received a copy of the GNU General Public License along
31
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
32
// target there if the PDF file isn't present.)  If not, see
33
// <http://www.gnu.org/licenses/> for a copy.
34
//
35
// License:     GPL, v3, as defined and found on www.gnu.org,
36
//              http://www.gnu.org/licenses/gpl.html
37
//
38
//
39
////////////////////////////////////////////////////////////////////////////////
40
#ifndef MEMSIM_H
41
#define MEMSIM_H
42
 
43
class   MEMSIM {
44
public:
45
        typedef unsigned int    BUSW;
46
        typedef unsigned char   uchar;
47
 
48
        BUSW    *m_mem, m_len, m_mask;
49
 
50
 
51
        MEMSIM(const unsigned int nwords);
52
        ~MEMSIM(void);
53
        void    load(const char *fname);
54
        void    apply(const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
55
                        const BUSW wb_addr, const BUSW wb_data,
56
                        uchar &o_ack, uchar &o_stall, BUSW &o_data);
57
        void    operator()(const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
58
                        const BUSW wb_addr, const BUSW wb_data,
59
                        uchar &o_ack, uchar &o_stall, BUSW &o_data) {
60
                apply(wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data);
61
        }
62
        BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; }
63
};
64
 
65
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.