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dgisselq |
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename: zippy_tb.cpp
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: A bench simulator for the CPU. Eventually, you should be
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// able to give this program the name of a piece of compiled
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// code to load into memory. For now, we hand assemble with the
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// computers help.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <signal.h>
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#include <time.h>
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dgisselq |
#include <unistd.h>
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#include <ctype.h>
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#include <ncurses.h>
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#include "verilated.h"
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#include "Vzipsystem.h"
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#include "testb.h"
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// #include "twoc.h"
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// #include "qspiflashsim.h"
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#include "memsim.h"
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#include "zopcodes.h"
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#include "zparser.h"
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#define CMD_REG 0
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#define CMD_DATA 1
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#define CMD_HALT (1<<10)
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#define CMD_STALL (1<<9)
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#define CMD_STEP (1<<8)
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#define CMD_INT (1<<7)
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#define CMD_RESET (1<<6)
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// No particular "parameters" need definition or redefinition here.
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class ZIPPY_TB : public TESTB<Vzipsystem> {
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public:
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unsigned long m_mem_size;
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MEMSIM m_mem;
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// QSPIFLASHSIM m_flash;
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FILE *dbg_fp;
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bool dbg_flag, bomb;
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ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
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//dbg_fp = fopen("dbg.txt", "w");
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dbg_fp = NULL;
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dbg_flag = false;
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bomb = false;
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}
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void reset(void) {
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// m_flash.debug(false);
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TESTB<Vzipsystem>::reset();
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}
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bool on_tick(void) {
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tick();
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return true;
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}
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void showval(int y, int x, const char *lbl, unsigned int v) {
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mvprintw(y,x, "%s: 0x%08x", lbl, v);
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}
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void dispreg(int y, int x, const char *n, unsigned int v) {
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// 4,4,8,1 = 17 of 20, +3 = 19
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mvprintw(y, x, "%s: 0x%08x", n, v);
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}
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void showreg(int y, int x, const char *n, int r) {
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// 4,4,8,1 = 17 of 20, +3 = 19
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mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
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addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
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&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
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&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
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?'a':' ');
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addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
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&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
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&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
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?'b':' ');
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addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
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&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
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?'W':' ');
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}
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void showins(int y, const char *lbl, const int ce, const int valid,
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const int gie, const int stall, const unsigned int pc) {
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char line[80];
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if (ce)
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mvprintw(y, 0, "Ck ");
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else
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mvprintw(y, 0, " ");
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if (stall)
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printw("Stl ");
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else
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printw(" ");
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printw("%s: 0x%08x", lbl, pc);
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if (valid) {
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if (gie) attroff(A_BOLD);
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else attron(A_BOLD);
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zipi_to_string(m_mem[pc], line);
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printw(" %-20s", &line[1]);
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} else {
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attroff(A_BOLD);
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printw(" (0x%08x)%28s", m_mem[pc],"");
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}
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attroff(A_BOLD);
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}
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void dbgins(const char *lbl, const int ce, const int valid,
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const int gie, const int stall, const unsigned int pc) {
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char line[80];
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if (!dbg_fp)
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return;
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if (ce)
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fprintf(dbg_fp, "%s Ck ", lbl);
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else
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fprintf(dbg_fp, "%s ", lbl);
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if (stall)
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fprintf(dbg_fp, "Stl ");
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else
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fprintf(dbg_fp, " ");
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fprintf(dbg_fp, "0x%08x: ", pc);
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if (valid) {
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zipi_to_string(m_mem[pc], line);
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fprintf(dbg_fp, " %-20s\n", &line[1]);
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} else {
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fprintf(dbg_fp, " (0x%08x)\n", m_mem[pc]);
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}
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}
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void show_state(void) {
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int ln= 0;
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mvprintw(ln,0, "Peripherals-SS"); ln++;
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/*
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showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
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mvprintw(ln, 17, "%s%s",
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((m_core->v__DOT__sys_cyc)
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&&(m_core->v__DOT__sys_we)
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&&(m_core->v__DOT__sys_addr == 0))?"W":" ",
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(m_core->v__DOT__trap_int)?"I":" ");
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*/
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showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
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showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
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showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
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showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
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ln++;
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showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
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showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
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showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
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showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
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ln++;
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showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
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dgisselq |
showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
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dgisselq |
showval(ln,41, "UPST", m_core->v__DOT__upc_data);
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dgisselq |
showval(ln,61, "UICT", m_core->v__DOT__uic_data);
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2 |
dgisselq |
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ln++;
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mvprintw(ln, 40, "%s %s",
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(m_core->v__DOT__cpu_halt)? "CPU-HALT": " ",
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(m_core->v__DOT__cpu_reset)?"CPU-RESET":" "); ln++;
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mvprintw(ln, 40, "%s %s %s 0x%02x",
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(m_core->v__DOT__cmd_halt)? "HALT": " ",
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(m_core->v__DOT__cmd_reset)?"RESET":" ",
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(m_core->v__DOT__cmd_step)? "STEP" :" ",
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(m_core->v__DOT__cmd_addr)&0x3f);
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if (m_core->v__DOT__thecpu__DOT__gie)
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attroff(A_BOLD);
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else
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attron(A_BOLD);
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mvprintw(ln, 0, "Supervisor Registers");
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ln++;
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showreg(ln, 1, "sR0 ", 0);
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showreg(ln,21, "sR1 ", 1);
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showreg(ln,41, "sR2 ", 2);
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showreg(ln,61, "sR3 ", 3); ln++;
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showreg(ln, 1, "sR4 ", 4);
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showreg(ln,21, "sR5 ", 5);
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showreg(ln,41, "sR6 ", 6);
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showreg(ln,61, "sR7 ", 7); ln++;
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showreg(ln, 1, "sR8 ", 8);
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showreg(ln,21, "sR9 ", 9);
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showreg(ln,41, "sR10", 10);
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showreg(ln,61, "sR11", 11); ln++;
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showreg(ln, 1, "sR12", 12);
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showreg(ln,21, "sSP ", 13);
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mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
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(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
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(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
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(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
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(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
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(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
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(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
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(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
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mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
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ln++;
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| 238 |
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if (m_core->v__DOT__thecpu__DOT__gie)
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attron(A_BOLD);
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else
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attroff(A_BOLD);
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mvprintw(ln, 0, "User Registers"); ln++;
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| 243 |
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showreg(ln, 1, "uR0 ", 16);
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showreg(ln,21, "uR1 ", 17);
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| 245 |
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showreg(ln,41, "uR2 ", 18);
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| 246 |
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showreg(ln,61, "uR3 ", 19); ln++;
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| 247 |
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| 248 |
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showreg(ln, 1, "uR4 ", 20);
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| 249 |
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showreg(ln,21, "uR5 ", 21);
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| 250 |
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showreg(ln,41, "uR6 ", 22);
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| 251 |
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showreg(ln,61, "uR7 ", 23); ln++;
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| 252 |
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| 253 |
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showreg(ln, 1, "uR8 ", 24);
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| 254 |
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showreg(ln,21, "uR9 ", 25);
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| 255 |
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showreg(ln,41, "uR10", 26);
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| 256 |
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showreg(ln,61, "uR11", 27); ln++;
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| 257 |
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| 258 |
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showreg(ln, 1, "uR12", 28);
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| 259 |
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showreg(ln,21, "uSP ", 29);
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| 260 |
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mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
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| 261 |
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(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
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| 262 |
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(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
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| 263 |
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(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
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| 264 |
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(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
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| 265 |
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(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
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| 266 |
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(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
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| 267 |
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(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
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| 268 |
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mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
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| 269 |
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| 270 |
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attroff(A_BOLD);
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| 271 |
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ln+=1;
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| 272 |
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| 273 |
4 |
dgisselq |
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
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| 274 |
2 |
dgisselq |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
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m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
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| 276 |
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m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
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| 277 |
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m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
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| 278 |
4 |
dgisselq |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
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| 279 |
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m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
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| 280 |
2 |
dgisselq |
ln++;
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| 281 |
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mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
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| 282 |
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(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
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| 283 |
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(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
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| 284 |
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" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
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| 285 |
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(m_core->v__DOT__thecpu__DOT__pf_addr),
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| 286 |
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0, // (m_core->v__DOT__thecpu__DOT__pf_data),
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| 287 |
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(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
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| 288 |
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(m_core->v__DOT__cpu_stall)?"STL":" ",
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| 289 |
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(m_core->v__DOT__wb_data)); ln++;
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| 290 |
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| 291 |
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mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
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| 292 |
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|
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":" ",
|
| 293 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":" ",
|
| 294 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_we )?"WE":" ",
|
| 295 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_addr),
|
| 296 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_data),
|
| 297 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ",
|
| 298 |
|
|
(m_core->v__DOT__cpu_stall)?"STL":" ",
|
| 299 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
|
| 300 |
|
|
|
| 301 |
|
|
mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
| 302 |
|
|
(m_core->o_wb_cyc)?"CYC":" ",
|
| 303 |
|
|
(m_core->o_wb_stb)?"STB":" ",
|
| 304 |
|
|
(m_core->o_wb_we )?"WE":" ",
|
| 305 |
|
|
(m_core->o_wb_addr),
|
| 306 |
|
|
(m_core->o_wb_data),
|
| 307 |
|
|
(m_core->i_wb_ack)?"ACK":" ",
|
| 308 |
|
|
(m_core->i_wb_stall)?"STL":" ",
|
| 309 |
|
|
(m_core->i_wb_data)); ln+=2;
|
| 310 |
|
|
|
| 311 |
|
|
showins(ln, "I ",
|
| 312 |
|
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
| 313 |
|
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
| 314 |
|
|
//m_core->v__DOT__thecpu__DOT__instruction_gie,
|
| 315 |
|
|
m_core->v__DOT__thecpu__DOT__gie,
|
| 316 |
|
|
0,
|
| 317 |
|
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
| 318 |
|
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
| 319 |
|
|
|
| 320 |
|
|
showins(ln, "Dc",
|
| 321 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
| 322 |
|
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
| 323 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
| 324 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
| 325 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
| 326 |
|
|
|
| 327 |
|
|
showins(ln, "Op",
|
| 328 |
|
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
| 329 |
|
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
| 330 |
|
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
| 331 |
|
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
| 332 |
|
|
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
|
| 333 |
|
|
|
| 334 |
|
|
showins(ln, "Al",
|
| 335 |
|
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
| 336 |
|
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
| 337 |
|
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
| 338 |
|
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
| 339 |
|
|
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
|
| 340 |
|
|
|
| 341 |
|
|
mvprintw(ln-4, 48,
|
| 342 |
|
|
(m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":" ");
|
| 343 |
|
|
printw("(%s:%02x,%x)",
|
| 344 |
|
|
(m_core->v__DOT__thecpu__DOT__set_cond)?"SET":" ",
|
| 345 |
|
|
(m_core->v__DOT__thecpu__DOT__opF&0x0ff),
|
| 346 |
|
|
(m_core->v__DOT__thecpu__DOT__op_gie)
|
| 347 |
|
|
? (m_core->v__DOT__thecpu__DOT__w_uflags)
|
| 348 |
|
|
: (m_core->v__DOT__thecpu__DOT__w_iflags));
|
| 349 |
|
|
|
| 350 |
|
|
printw("(%s%s%s:%02x)",
|
| 351 |
|
|
(m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":" ",
|
| 352 |
|
|
(m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":" ",
|
| 353 |
|
|
(m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
|
| 354 |
|
|
(m_core->v__DOT__thecpu__DOT__alu_flags));
|
| 355 |
|
|
/*
|
| 356 |
|
|
mvprintw(ln-3, 48, "dcdI : 0x%08x",
|
| 357 |
|
|
m_core->v__DOT__thecpu__DOT__dcdI);
|
| 358 |
|
|
mvprintw(ln-2, 48, "r_opB: 0x%08x",
|
| 359 |
|
|
m_core->v__DOT__thecpu__DOT__opB);
|
| 360 |
|
|
*/
|
| 361 |
|
|
mvprintw(ln-3, 48, "Op(%x)%8x %8x->%08x",
|
| 362 |
|
|
m_core->v__DOT__thecpu__DOT__opn,
|
| 363 |
|
|
m_core->v__DOT__thecpu__DOT__opA,
|
| 364 |
|
|
m_core->v__DOT__thecpu__DOT__opB,
|
| 365 |
|
|
m_core->v__DOT__thecpu__DOT__alu_result);
|
| 366 |
|
|
mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
|
| 367 |
|
|
(m_core->v__DOT__thecpu__DOT__opM)?"M":" ",
|
| 368 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":" ",
|
| 369 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
|
| 370 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":" ",
|
| 371 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":" ",
|
| 372 |
|
|
zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
|
| 373 |
|
|
}
|
| 374 |
|
|
|
| 375 |
|
|
unsigned int cmd_read(unsigned int a) {
|
| 376 |
|
|
if (dbg_fp) {
|
| 377 |
|
|
dbg_flag= true;
|
| 378 |
|
|
fprintf(dbg_fp, "CMD-READ(%d)\n", a);
|
| 379 |
|
|
}
|
| 380 |
|
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
| 381 |
|
|
while((wb_read(CMD_REG) & CMD_STALL) == 0)
|
| 382 |
|
|
;
|
| 383 |
|
|
unsigned int v = wb_read(CMD_DATA);
|
| 384 |
|
|
|
| 385 |
|
|
if (dbg_flag)
|
| 386 |
|
|
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
|
| 387 |
|
|
v);
|
| 388 |
|
|
dbg_flag = false;
|
| 389 |
|
|
return v;
|
| 390 |
|
|
}
|
| 391 |
|
|
|
| 392 |
|
|
void read_state(void) {
|
| 393 |
|
|
int ln= 0;
|
| 394 |
|
|
|
| 395 |
|
|
mvprintw(ln,0, "Peripherals-RS"); ln++;
|
| 396 |
|
|
showval(ln, 1, "PIC ", cmd_read(32+ 0));
|
| 397 |
|
|
showval(ln,21, "WDT ", cmd_read(32+ 1));
|
| 398 |
|
|
showval(ln,41, "CACH", cmd_read(32+ 2));
|
| 399 |
|
|
showval(ln,61, "PIC2", cmd_read(32+ 3));
|
| 400 |
|
|
ln++;
|
| 401 |
|
|
showval(ln, 1, "TMRA", cmd_read(32+ 4));
|
| 402 |
|
|
showval(ln,21, "TMRB", cmd_read(32+ 5));
|
| 403 |
|
|
showval(ln,41, "TMRC", cmd_read(32+ 6));
|
| 404 |
|
|
showval(ln,61, "JIF ", cmd_read(32+ 7));
|
| 405 |
|
|
|
| 406 |
|
|
ln++;
|
| 407 |
|
|
showval(ln, 1, "UTSK", cmd_read(32+12));
|
| 408 |
|
|
showval(ln,21, "UMST", cmd_read(32+13));
|
| 409 |
|
|
showval(ln,41, "UPST", cmd_read(32+14));
|
| 410 |
|
|
showval(ln,61, "UAST", cmd_read(32+15));
|
| 411 |
|
|
|
| 412 |
|
|
ln++;
|
| 413 |
|
|
ln++;
|
| 414 |
|
|
unsigned int cc = cmd_read(14);
|
| 415 |
|
|
if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
|
| 416 |
|
|
m_core->v__DOT__thecpu__DOT__gie);
|
| 417 |
|
|
if (cc & 0x020)
|
| 418 |
|
|
attroff(A_BOLD);
|
| 419 |
|
|
else
|
| 420 |
|
|
attron(A_BOLD);
|
| 421 |
|
|
mvprintw(ln, 0, "Supervisor Registers");
|
| 422 |
|
|
ln++;
|
| 423 |
|
|
|
| 424 |
|
|
dispreg(ln, 1, "sR0 ", cmd_read(0));
|
| 425 |
|
|
dispreg(ln,21, "sR1 ", cmd_read(1));
|
| 426 |
|
|
dispreg(ln,41, "sR2 ", cmd_read(2));
|
| 427 |
|
|
dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
|
| 428 |
|
|
|
| 429 |
|
|
dispreg(ln, 1, "sR4 ", cmd_read(4));
|
| 430 |
|
|
dispreg(ln,21, "sR5 ", cmd_read(5));
|
| 431 |
|
|
dispreg(ln,41, "sR6 ", cmd_read(6));
|
| 432 |
|
|
dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
|
| 433 |
|
|
|
| 434 |
|
|
dispreg(ln, 1, "sR8 ", cmd_read( 8));
|
| 435 |
|
|
dispreg(ln,21, "sR9 ", cmd_read( 9));
|
| 436 |
|
|
dispreg(ln,41, "sR10", cmd_read(10));
|
| 437 |
|
|
dispreg(ln,61, "sR11", cmd_read(11)); ln++;
|
| 438 |
|
|
|
| 439 |
|
|
dispreg(ln, 1, "sR12", cmd_read(12));
|
| 440 |
|
|
dispreg(ln,21, "sSP ", cmd_read(13));
|
| 441 |
|
|
|
| 442 |
|
|
mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
|
| 443 |
|
|
(cc & 0x040)?"STP":" ",
|
| 444 |
|
|
(cc & 0x020)?"GIE":" ",
|
| 445 |
|
|
(cc & 0x010)?"SLP":" ",
|
| 446 |
|
|
(cc&8)?"V":" ",
|
| 447 |
|
|
(cc&4)?"N":" ",
|
| 448 |
|
|
(cc&2)?"C":" ",
|
| 449 |
|
|
(cc&1)?"Z":" ");
|
| 450 |
|
|
mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
|
| 451 |
|
|
ln++;
|
| 452 |
|
|
|
| 453 |
|
|
if (cc & 0x020)
|
| 454 |
|
|
attron(A_BOLD);
|
| 455 |
|
|
else
|
| 456 |
|
|
attroff(A_BOLD);
|
| 457 |
|
|
mvprintw(ln, 0, "User Registers"); ln++;
|
| 458 |
|
|
dispreg(ln, 1, "uR0 ", cmd_read(16));
|
| 459 |
|
|
dispreg(ln,21, "uR1 ", cmd_read(17));
|
| 460 |
|
|
dispreg(ln,41, "uR2 ", cmd_read(18));
|
| 461 |
|
|
dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
|
| 462 |
|
|
|
| 463 |
|
|
dispreg(ln, 1, "uR4 ", cmd_read(20));
|
| 464 |
|
|
dispreg(ln,21, "uR5 ", cmd_read(21));
|
| 465 |
|
|
dispreg(ln,41, "uR6 ", cmd_read(22));
|
| 466 |
|
|
dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
|
| 467 |
|
|
|
| 468 |
|
|
dispreg(ln, 1, "uR8 ", cmd_read(24));
|
| 469 |
|
|
dispreg(ln,21, "uR9 ", cmd_read(25));
|
| 470 |
|
|
dispreg(ln,41, "uR10", cmd_read(26));
|
| 471 |
|
|
dispreg(ln,61, "uR11", cmd_read(27)); ln++;
|
| 472 |
|
|
|
| 473 |
|
|
dispreg(ln, 1, "uR12", cmd_read(28));
|
| 474 |
|
|
dispreg(ln,21, "uSP ", cmd_read(29));
|
| 475 |
|
|
cc = cmd_read(30);
|
| 476 |
|
|
mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
|
| 477 |
|
|
(cc&0x040)?"STP":" ",
|
| 478 |
|
|
(cc&0x020)?"GIE":" ",
|
| 479 |
|
|
(cc&0x010)?"SLP":" ",
|
| 480 |
|
|
(cc&8)?"V":" ",
|
| 481 |
|
|
(cc&4)?"N":" ",
|
| 482 |
|
|
(cc&2)?"C":" ",
|
| 483 |
|
|
(cc&1)?"Z":" ");
|
| 484 |
|
|
mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
|
| 485 |
|
|
|
| 486 |
|
|
attroff(A_BOLD);
|
| 487 |
|
|
ln+=2;
|
| 488 |
|
|
|
| 489 |
|
|
ln+=3;
|
| 490 |
|
|
|
| 491 |
|
|
showins(ln, "I ",
|
| 492 |
|
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
| 493 |
|
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
| 494 |
|
|
m_core->v__DOT__thecpu__DOT__gie,
|
| 495 |
|
|
0,
|
| 496 |
|
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
| 497 |
|
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
| 498 |
|
|
|
| 499 |
|
|
showins(ln, "Dc",
|
| 500 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
| 501 |
|
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
| 502 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
| 503 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
| 504 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
| 505 |
|
|
|
| 506 |
|
|
showins(ln, "Op",
|
| 507 |
|
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
| 508 |
|
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
| 509 |
|
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
| 510 |
|
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
| 511 |
|
|
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
|
| 512 |
|
|
|
| 513 |
|
|
showins(ln, "Al",
|
| 514 |
|
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
| 515 |
|
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
| 516 |
|
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
| 517 |
|
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
| 518 |
|
|
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
|
| 519 |
|
|
}
|
| 520 |
|
|
void tick(void) {
|
| 521 |
|
|
int gie = m_core->v__DOT__thecpu__DOT__gie;
|
| 522 |
|
|
/*
|
| 523 |
|
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
| 524 |
|
|
m_core->o_qspi_sck,
|
| 525 |
|
|
m_core->o_qspi_dat);
|
| 526 |
|
|
*/
|
| 527 |
|
|
|
| 528 |
11 |
dgisselq |
int stb = m_core->o_wb_stb;
|
| 529 |
|
|
if ((m_core->o_wb_addr & (-1<<20))!=1)
|
| 530 |
|
|
stb = 0;
|
| 531 |
2 |
dgisselq |
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
|
| 532 |
|
|
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
|
| 533 |
|
|
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
|
| 534 |
11 |
dgisselq |
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
|
| 535 |
|
|
m_core->i_wb_ack = 1;
|
| 536 |
2 |
dgisselq |
|
| 537 |
|
|
if ((dbg_flag)&&(dbg_fp)) {
|
| 538 |
|
|
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
|
| 539 |
|
|
(m_core->i_dbg_cyc)?"CYC":" ",
|
| 540 |
|
|
(m_core->i_dbg_stb)?"STB":
|
| 541 |
|
|
((m_core->v__DOT__dbg_stb)?"DBG":" "),
|
| 542 |
|
|
((m_core->i_dbg_we)?"WE":" "),
|
| 543 |
|
|
(m_core->i_dbg_addr),0,
|
| 544 |
|
|
m_core->i_dbg_data,
|
| 545 |
|
|
(m_core->o_dbg_ack)?"ACK":" ",
|
| 546 |
|
|
(m_core->o_dbg_stall)?"STALL":" ",
|
| 547 |
|
|
(m_core->o_dbg_data),
|
| 548 |
|
|
(m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
|
| 549 |
|
|
(m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
|
| 550 |
|
|
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
|
| 551 |
|
|
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
|
| 552 |
|
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
|
| 553 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
|
| 554 |
|
|
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
|
| 555 |
|
|
(m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
|
| 556 |
|
|
(m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
|
| 557 |
|
|
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
|
| 558 |
|
|
fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
|
| 559 |
|
|
(m_core->v__DOT__sys_cyc)?"CYC":" ",
|
| 560 |
|
|
(m_core->v__DOT__sys_stb)?"STB":" ",
|
| 561 |
|
|
(m_core->v__DOT__sys_we)?"WE":" ",
|
| 562 |
|
|
(m_core->v__DOT__sys_addr),
|
| 563 |
|
|
(m_core->v__DOT__dbg_addr),
|
| 564 |
|
|
(m_core->v__DOT__sys_data),
|
| 565 |
|
|
(m_core->v__DOT__dbg_ack)?"ACK":" ",
|
| 566 |
|
|
(m_core->v__DOT__wb_data));
|
| 567 |
|
|
}
|
| 568 |
|
|
|
| 569 |
|
|
if (dbg_fp)
|
| 570 |
|
|
fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
|
| 571 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
| 572 |
|
|
m_core->v__DOT__thecpu__DOT__dcd_pc,
|
| 573 |
|
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
| 574 |
|
|
m_core->v__DOT__thecpu__DOT__op_pc,
|
| 575 |
|
|
m_core->v__DOT__thecpu__DOT__dcdA,
|
| 576 |
|
|
m_core->v__DOT__thecpu__DOT__opR,
|
| 577 |
|
|
m_core->v__DOT__cmd_halt,
|
| 578 |
|
|
m_core->v__DOT__cpu_halt,
|
| 579 |
|
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
| 580 |
|
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
| 581 |
|
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
| 582 |
|
|
m_core->v__DOT__thecpu__DOT__alu_reg,
|
| 583 |
|
|
m_core->v__DOT__thecpu__DOT__ipc,
|
| 584 |
|
|
m_core->v__DOT__thecpu__DOT__upc);
|
| 585 |
|
|
|
| 586 |
|
|
if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
|
| 587 |
|
|
fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
|
| 588 |
|
|
m_core->v__DOT__pic_interrupt,
|
| 589 |
|
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
| 590 |
|
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
| 591 |
|
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
| 592 |
|
|
m_core->v__DOT__cmd_addr,
|
| 593 |
|
|
m_core->v__DOT__dbg_idata,
|
| 594 |
|
|
m_core->v__DOT__thecpu__DOT__master_ce,
|
| 595 |
|
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
| 596 |
|
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
| 597 |
|
|
m_core->v__DOT__thecpu__DOT__mem_valid);
|
| 598 |
|
|
} else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
|
| 599 |
|
|
fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
|
| 600 |
|
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
| 601 |
|
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
| 602 |
|
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
| 603 |
|
|
m_core->v__DOT__cmd_addr,
|
| 604 |
|
|
m_core->v__DOT__dbg_idata,
|
| 605 |
|
|
m_core->v__DOT__thecpu__DOT__master_ce,
|
| 606 |
|
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
| 607 |
|
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
| 608 |
|
|
m_core->v__DOT__thecpu__DOT__mem_valid,
|
| 609 |
|
|
m_core->v__DOT__thecpu__DOT__w_iflags,
|
| 610 |
|
|
m_core->v__DOT__thecpu__DOT__w_uflags);
|
| 611 |
|
|
fprintf(dbg_fp, "\tbrk=%d,%d\n",
|
| 612 |
|
|
m_core->v__DOT__thecpu__DOT__break_en,
|
| 613 |
|
|
m_core->v__DOT__thecpu__DOT__op_break);
|
| 614 |
|
|
}
|
| 615 |
|
|
|
| 616 |
|
|
TESTB<Vzipsystem>::tick();
|
| 617 |
|
|
if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
|
| 618 |
|
|
fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
|
| 619 |
|
|
(gie)?"User":"Supervisor",
|
| 620 |
|
|
(gie)?"Supervisor":"User",
|
| 621 |
|
|
m_core->v__DOT__thecpu__DOT__ipc,
|
| 622 |
|
|
m_core->v__DOT__thecpu__DOT__upc,
|
| 623 |
|
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
| 624 |
|
|
} if (dbg_fp) {
|
| 625 |
|
|
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
|
| 626 |
|
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
| 627 |
|
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
| 628 |
|
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
| 629 |
|
|
m_core->v__DOT__thecpu__DOT__op_pc-1);
|
| 630 |
|
|
dbgins("Al - ",
|
| 631 |
|
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
| 632 |
|
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
| 633 |
|
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
| 634 |
|
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
| 635 |
|
|
m_core->v__DOT__thecpu__DOT__alu_pc-1);
|
| 636 |
|
|
|
| 637 |
|
|
}
|
| 638 |
|
|
|
| 639 |
|
|
if (m_core->v__DOT__cpu_dbg_we) {
|
| 640 |
|
|
printf("WRITE-ENABLE!!\n");
|
| 641 |
|
|
bomb = true;
|
| 642 |
|
|
}
|
| 643 |
|
|
}
|
| 644 |
|
|
|
| 645 |
|
|
bool test_success(void) {
|
| 646 |
|
|
return ((!m_core->v__DOT__thecpu__DOT__gie)
|
| 647 |
|
|
&&(m_core->v__DOT__thecpu__DOT__sleep));
|
| 648 |
|
|
}
|
| 649 |
|
|
|
| 650 |
|
|
bool test_failure(void) {
|
| 651 |
|
|
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
| 652 |
|
|
&&(!m_core->v__DOT__thecpu__DOT__alu_gie)
|
| 653 |
|
|
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
|
| 654 |
|
|
== 0x2f0f7fff));
|
| 655 |
|
|
}
|
| 656 |
|
|
|
| 657 |
|
|
void wb_write(unsigned a, unsigned int v) {
|
| 658 |
|
|
mvprintw(0,35, "%40s", "");
|
| 659 |
|
|
mvprintw(0,40, "wb_write(%d,%x)", a, v);
|
| 660 |
|
|
m_core->i_dbg_cyc = 1;
|
| 661 |
|
|
m_core->i_dbg_stb = 1;
|
| 662 |
|
|
m_core->i_dbg_we = 1;
|
| 663 |
|
|
m_core->i_dbg_addr = a & 1;
|
| 664 |
|
|
m_core->i_dbg_data = v;
|
| 665 |
|
|
|
| 666 |
|
|
tick();
|
| 667 |
|
|
while(m_core->o_dbg_stall)
|
| 668 |
|
|
tick();
|
| 669 |
|
|
|
| 670 |
|
|
m_core->i_dbg_stb = 0;
|
| 671 |
|
|
while(!m_core->o_dbg_ack)
|
| 672 |
|
|
tick();
|
| 673 |
|
|
|
| 674 |
|
|
// Release the bus
|
| 675 |
|
|
m_core->i_dbg_cyc = 0;
|
| 676 |
|
|
m_core->i_dbg_stb = 0;
|
| 677 |
|
|
tick();
|
| 678 |
|
|
mvprintw(0,35, "%40s", "");
|
| 679 |
|
|
mvprintw(0,40, "wb_write -- complete");
|
| 680 |
|
|
}
|
| 681 |
|
|
|
| 682 |
|
|
unsigned long wb_read(unsigned a) {
|
| 683 |
|
|
unsigned int v;
|
| 684 |
|
|
mvprintw(0,35, "%40s", "");
|
| 685 |
|
|
mvprintw(0,40, "wb_read(0x%08x)", a);
|
| 686 |
|
|
m_core->i_dbg_cyc = 1;
|
| 687 |
|
|
m_core->i_dbg_stb = 1;
|
| 688 |
|
|
m_core->i_dbg_we = 0;
|
| 689 |
|
|
m_core->i_dbg_addr = a & 1;
|
| 690 |
|
|
|
| 691 |
|
|
tick();
|
| 692 |
|
|
while(m_core->o_dbg_stall)
|
| 693 |
|
|
tick();
|
| 694 |
|
|
|
| 695 |
|
|
m_core->i_dbg_stb = 0;
|
| 696 |
|
|
while(!m_core->o_dbg_ack)
|
| 697 |
|
|
tick();
|
| 698 |
|
|
v = m_core->o_dbg_data;
|
| 699 |
|
|
|
| 700 |
|
|
// Release the bus
|
| 701 |
|
|
m_core->i_dbg_cyc = 0;
|
| 702 |
|
|
m_core->i_dbg_stb = 0;
|
| 703 |
|
|
tick();
|
| 704 |
|
|
|
| 705 |
|
|
mvprintw(0,35, "%40s", "");
|
| 706 |
|
|
mvprintw(0,40, "wb_read = 0x%08x", v);
|
| 707 |
|
|
|
| 708 |
|
|
return v;
|
| 709 |
|
|
}
|
| 710 |
|
|
|
| 711 |
|
|
};
|
| 712 |
|
|
|
| 713 |
|
|
|
| 714 |
|
|
int main(int argc, char **argv) {
|
| 715 |
|
|
Verilated::commandArgs(argc, argv);
|
| 716 |
|
|
ZIPPY_TB *tb = new ZIPPY_TB();
|
| 717 |
|
|
ZPARSER zp;
|
| 718 |
|
|
|
| 719 |
|
|
printf("uCC = %d\n", (int)zp.ZIP_uCC);
|
| 720 |
|
|
printf("MOV CC,R0 = 0x%08x\n", zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0));
|
| 721 |
|
|
// = 0x200e8000
|
| 722 |
|
|
// Op = 0x2
|
| 723 |
|
|
// Result = 0x0, R0 (Supervisor/default)
|
| 724 |
|
|
// Cond = 0x0
|
| 725 |
|
|
// BReg = 0xe (CC)
|
| 726 |
|
|
// BMap = 1, BReg = uCC
|
| 727 |
|
|
//
|
| 728 |
|
|
|
| 729 |
|
|
initscr();
|
| 730 |
|
|
raw();
|
| 731 |
|
|
noecho();
|
| 732 |
|
|
keypad(stdscr, true);
|
| 733 |
|
|
|
| 734 |
|
|
// mem[0x00000] = 0xbe000010; // Halt instruction
|
| 735 |
|
|
unsigned int mptr = 0;
|
| 736 |
|
|
|
| 737 |
9 |
dgisselq |
if (argc <= 1) {
|
| 738 |
2 |
dgisselq |
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // 0: CLR R0
|
| 739 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); // 1: MOV R0,R1
|
| 740 |
|
|
tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); // 2: MOV $1+R0,R2
|
| 741 |
|
|
tb->m_mem[mptr++] = zp.op_mov(2,zp.ZIP_R0,zp.ZIP_R3); // 3: MOV $2+R0,R3
|
| 742 |
|
|
tb->m_mem[mptr++] = zp.op_mov(0x022, zp.ZIP_R0, zp.ZIP_R4); // 4: MOV $22h+R0,R4
|
| 743 |
|
|
tb->m_mem[mptr++] = zp.op_mov(0x377, zp.ZIP_R0, zp.ZIP_uR5); // 5: MOV $377h+R0,uR5
|
| 744 |
|
|
tb->m_mem[mptr++] = zp.op_noop(); // 6: NOOP
|
| 745 |
|
|
tb->m_mem[mptr++] = zp.op_add(0,zp.ZIP_R2,zp.ZIP_R0); // 7: ADD R2,R0
|
| 746 |
|
|
tb->m_mem[mptr++] = zp.op_add(32,zp.ZIP_R0); // 8: ADD $32,R0
|
| 747 |
|
|
tb->m_mem[mptr++] = zp.op_add(-33,zp.ZIP_R0); // 9: ADD -$33,R0
|
| 748 |
|
|
tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_Z, zp.ZIP_R0); // A: NOT.Z R0
|
| 749 |
|
|
tb->m_mem[mptr++] = zp.op_clrf(zp.ZIP_R0); // B: CLRF R0
|
| 750 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(5,zp.ZIP_R1); // C: LDI $5,R1
|
| 751 |
|
|
tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R0,zp.ZIP_R1); // D: CMP R0,R1
|
| 752 |
|
|
tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_LT, zp.ZIP_R0); // E: NOT.LT R0
|
| 753 |
|
|
tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_GE, zp.ZIP_R1); // F: NOT.GE R1
|
| 754 |
|
|
tb->m_mem[mptr++] = zp.op_lod(-7,zp.ZIP_PC, zp.ZIP_R2); // 10: LOD $-7(PC),R2
|
| 755 |
|
|
tb->m_mem[mptr++] = zp.op_ldihi(0xdead, zp.ZIP_R3); // 11: LODIHI $deadh,R3
|
| 756 |
|
|
tb->m_mem[mptr++] = zp.op_ldilo(0xbeef, zp.ZIP_R3); // 12: LODILO $beefh,R3
|
| 757 |
|
|
|
| 758 |
|
|
// Let's build a software test bench.
|
| 759 |
|
|
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R12);// 0: CLR R12
|
| 760 |
|
|
tb->m_mem[mptr++] = zp.op_ldihi(0xc000,zp.ZIP_R12);
|
| 761 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R12,zp.ZIP_uR12);
|
| 762 |
|
|
tb->m_mem[mptr++] = zp.op_mov(10,zp.ZIP_PC,zp.ZIP_uPC);
|
| 763 |
|
|
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // Clear R0, and disable ints
|
| 764 |
|
|
tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R12);
|
| 765 |
|
|
tb->m_mem[mptr++] = zp.op_rtu(); // 7: RTU // Switch to user mode
|
| 766 |
|
|
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0); // Check result
|
| 767 |
|
|
tb->m_mem[mptr++] = zp.op_tst(-256,zp.ZIP_R0);
|
| 768 |
|
|
tb->m_mem[mptr++] = zp.op_bnz(1);
|
| 769 |
|
|
tb->m_mem[mptr++] = zp.op_halt();// On SUCCESS
|
| 770 |
|
|
tb->m_mem[mptr++] = zp.op_busy(); // On FAILURE
|
| 771 |
|
|
|
| 772 |
|
|
|
| 773 |
|
|
// Now for a series of tests. If the test fails, call the trap
|
| 774 |
|
|
// interrupt with the test number that failed. Upon completion,
|
| 775 |
|
|
// call the trap with #0.
|
| 776 |
|
|
|
| 777 |
|
|
// Now for a series of tests. If the test fails, call the trap
|
| 778 |
|
|
// interrupt with the test number that failed. Upon completion,
|
| 779 |
|
|
// call the trap with #0.
|
| 780 |
|
|
|
| 781 |
|
|
// Test LDI to PC
|
| 782 |
|
|
// Some data registers
|
| 783 |
|
|
tb->m_mem[mptr] = mptr + 5 + 0x0100000; mptr++;
|
| 784 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x020,zp.ZIP_CC); // LDI $GIE,CC
|
| 785 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x0200,zp.ZIP_R11); // LDI $200h,R11
|
| 786 |
|
|
tb->m_mem[mptr++] = zp.op_lod(-4,zp.ZIP_PC,zp.ZIP_PC); // 1: LOD $-3(PC),PC
|
| 787 |
|
|
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); // 2: CLR R11
|
| 788 |
|
|
tb->m_mem[mptr++] = zp.op_noop(); // 3: NOOP
|
| 789 |
|
|
tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R11); // 4: CMP $0,R11
|
| 790 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_R10); // 5: STO.Z R11,(R12)
|
| 791 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_CC); // 5: STO.Z R11,(R12)
|
| 792 |
|
|
tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); // 6: ADD $1,R0
|
| 793 |
|
|
tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); // 7: ADD $1,R0
|
| 794 |
|
|
|
| 795 |
|
|
// Let's test whether overflow works
|
| 796 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x0300,zp.ZIP_R11); // 0: LDI $3,R11
|
| 797 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(-1,zp.ZIP_R0); // 1: LDI $-1,R0
|
| 798 |
|
|
tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0); // R0 // R0 = max int
|
| 799 |
|
|
tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); // Should set ovfl
|
| 800 |
|
|
tb->m_mem[mptr++] = zp.op_bv(1); // 4: BV $1+PC
|
| 801 |
|
|
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 802 |
|
|
// Overflow set from subtraction
|
| 803 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x0400,zp.ZIP_R11); // 6: LDI $4,R11
|
| 804 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); // 7: LDI $1,R0
|
| 805 |
8 |
dgisselq |
tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0); // 8: ROL $31,R0
|
| 806 |
2 |
dgisselq |
tb->m_mem[mptr++] = zp.op_sub(1,zp.ZIP_R0); // Should set ovfl
|
| 807 |
|
|
tb->m_mem[mptr++] = zp.op_bv(1); // A: BV $1+PC
|
| 808 |
|
|
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 809 |
|
|
// Overflow set from LSR
|
| 810 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x0500,zp.ZIP_R11); // C: LDI $5,R11
|
| 811 |
8 |
dgisselq |
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
|
| 812 |
|
|
tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
|
| 813 |
|
|
tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0);
|
| 814 |
|
|
tb->m_mem[mptr++] = zp.op_bv(1);
|
| 815 |
2 |
dgisselq |
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 816 |
|
|
// Overflow set from LSL
|
| 817 |
8 |
dgisselq |
tb->m_mem[mptr++] = zp.op_ldi(0x0600,zp.ZIP_R11);
|
| 818 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
|
| 819 |
|
|
tb->m_mem[mptr++] = zp.op_rol(30,zp.ZIP_R0);
|
| 820 |
|
|
tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
|
| 821 |
|
|
tb->m_mem[mptr++] = zp.op_bv(1);
|
| 822 |
2 |
dgisselq |
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 823 |
|
|
// Overflow set from LSL, negative to positive
|
| 824 |
8 |
dgisselq |
tb->m_mem[mptr++] = zp.op_ldi(0x0700,zp.ZIP_R11);
|
| 825 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
|
| 826 |
|
|
tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
|
| 827 |
|
|
tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
|
| 828 |
2 |
dgisselq |
tb->m_mem[mptr++] = zp.op_bv(1); // A: BV $1+PC
|
| 829 |
|
|
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
// Test carry
|
| 833 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x01000, zp.ZIP_R11); // 0: LDI $16,R11
|
| 834 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(-1, zp.ZIP_R0); // 1: LDI $-1,R0
|
| 835 |
|
|
tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); // 2: ADD $1,R0
|
| 836 |
|
|
tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); // 3: TST $2,CC // Is the carry set?
|
| 837 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 838 |
|
|
// and carry from subtraction
|
| 839 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x01100, zp.ZIP_R11); // 0: LDI $17,R11
|
| 840 |
|
|
tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R0); // 1: SUB $1,R0
|
| 841 |
|
|
tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); // 2: TST $2,CC // Is the carry set?
|
| 842 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
|
| 843 |
|
|
|
| 844 |
|
|
|
| 845 |
|
|
|
| 846 |
|
|
// Let's try a loop: for i=0; i<5; i++)
|
| 847 |
|
|
// We'll use R0=i, Immediates for 5
|
| 848 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x01200, zp.ZIP_R11); // 0: LDI $18,R11
|
| 849 |
|
|
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // 0: CLR R0
|
| 850 |
|
|
tb->m_mem[mptr++] = zp.op_noop();
|
| 851 |
|
|
tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); // 2: R0 = R0 + 1
|
| 852 |
|
|
tb->m_mem[mptr++] = zp.op_cmp(5, zp.ZIP_R0); // 3: CMP $5,R0
|
| 853 |
|
|
tb->m_mem[mptr++] = zp.op_blt(-4); // 4: BLT PC-4
|
| 854 |
|
|
//
|
| 855 |
|
|
// Let's try a reverse loop. Such loops are usually cheaper to
|
| 856 |
|
|
// implement, and this one is no different: 2 loop instructions
|
| 857 |
|
|
// (minus setup instructions) vs 3 from before.
|
| 858 |
|
|
// R0 = 5; (from before)
|
| 859 |
|
|
// do {
|
| 860 |
|
|
// } while (R0 > 0);
|
| 861 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x01300, zp.ZIP_R11); // 0: LDI $18,R11
|
| 862 |
|
|
tb->m_mem[mptr++] = zp.op_noop(); // 5: NOOP
|
| 863 |
|
|
tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0); // 6: R0 = R0 - 1
|
| 864 |
|
|
tb->m_mem[mptr++] = zp.op_bgt(-3); // 7: BGT PC-3
|
| 865 |
|
|
// How about the same thing with a >= comparison?
|
| 866 |
|
|
// R1 = 5; // Need to do this explicitly
|
| 867 |
|
|
// do {
|
| 868 |
|
|
// } while(R1 >= 0);
|
| 869 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x01400, zp.ZIP_R11); // 0: LDI $18,R11
|
| 870 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R1);
|
| 871 |
|
|
tb->m_mem[mptr++] = zp.op_noop();
|
| 872 |
|
|
tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R1);
|
| 873 |
|
|
tb->m_mem[mptr++] = zp.op_bge(-3);
|
| 874 |
|
|
|
| 875 |
|
|
// Let's try the reverse loop again, only this time we'll store our
|
| 876 |
|
|
// loop variable in memory.
|
| 877 |
|
|
// R0 = 5; (from before)
|
| 878 |
|
|
// do {
|
| 879 |
|
|
// } while (R0 > 0);
|
| 880 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(0x01500, zp.ZIP_R11); // 0: LDI $18,R11
|
| 881 |
|
|
tb->m_mem[mptr++] = zp.op_bra(1); // Give us a memory location
|
| 882 |
|
|
tb->m_mem[mptr++] = 5; // Loop five times
|
| 883 |
|
|
tb->m_mem[mptr++] = zp.op_mov(-2, zp.ZIP_PC, zp.ZIP_R1); // Get var adr
|
| 884 |
|
|
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R2);
|
| 885 |
|
|
tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R0);
|
| 886 |
|
|
tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R1);
|
| 887 |
|
|
tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R2);
|
| 888 |
|
|
tb->m_mem[mptr++] = zp.op_add(14,zp.ZIP_R0);
|
| 889 |
|
|
tb->m_mem[mptr++] = zp.op_lod(0,zp.ZIP_R1,zp.ZIP_R0);
|
| 890 |
|
|
tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0);
|
| 891 |
|
|
tb->m_mem[mptr++] = zp.op_bgt(-6);
|
| 892 |
|
|
tb->m_mem[mptr++] = zp.op_cmp( 5, zp.ZIP_R2);
|
| 893 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_NZ, 0, zp.ZIP_R11, zp.ZIP_CC);
|
| 894 |
|
|
|
| 895 |
|
|
// Return success / Test the trap interrupt
|
| 896 |
|
|
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); // 0: CLR R11
|
| 897 |
|
|
tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R11, zp.ZIP_CC);
|
| 898 |
|
|
tb->m_mem[mptr++] = zp.op_noop(); // 2: NOOP // Give it a chance to take
|
| 899 |
|
|
tb->m_mem[mptr++] = zp.op_noop(); // 3: NOOP // effect
|
| 900 |
|
|
|
| 901 |
|
|
// Go into an infinite loop if the trap fails
|
| 902 |
|
|
// Permanent loop instruction -- a busy halt if you will
|
| 903 |
|
|
tb->m_mem[mptr++] = zp.op_busy(); // 4: BRA PC-1
|
| 904 |
|
|
|
| 905 |
|
|
// And, in case we miss a halt ...
|
| 906 |
|
|
tb->m_mem[mptr++] = zp.op_halt(); // HALT
|
| 907 |
|
|
|
| 908 |
9 |
dgisselq |
} else {
|
| 909 |
|
|
for(int argn=1; argn<argc; argn++) {
|
| 910 |
|
|
if (access(argv[argn], R_OK)==0) {
|
| 911 |
|
|
FILE *fp = fopen(argv[argn], "r");
|
| 912 |
|
|
if (fp == NULL) {
|
| 913 |
|
|
printf("Cannot open %s\n", argv[argn]);
|
| 914 |
|
|
perror("O/S Err: ");
|
| 915 |
|
|
exit(-1);
|
| 916 |
|
|
} mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
|
| 917 |
|
|
fclose(fp);
|
| 918 |
|
|
}
|
| 919 |
|
|
}
|
| 920 |
|
|
}
|
| 921 |
|
|
|
| 922 |
2 |
dgisselq |
tb->reset();
|
| 923 |
|
|
int chv = 'q';
|
| 924 |
|
|
const bool live_debug_mode = true;
|
| 925 |
|
|
|
| 926 |
|
|
if (live_debug_mode) {
|
| 927 |
|
|
bool done = false, halted = true, manual = true;
|
| 928 |
|
|
|
| 929 |
|
|
halfdelay(1);
|
| 930 |
|
|
tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
|
| 931 |
|
|
// while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
|
| 932 |
|
|
// tb->show_state();
|
| 933 |
|
|
|
| 934 |
|
|
while(!done) {
|
| 935 |
|
|
chv = getch();
|
| 936 |
|
|
switch(chv) {
|
| 937 |
|
|
case 'h': case 'H':
|
| 938 |
|
|
tb->wb_write(CMD_REG, CMD_HALT);
|
| 939 |
|
|
if (!halted)
|
| 940 |
|
|
erase();
|
| 941 |
|
|
halted = true;
|
| 942 |
|
|
break;
|
| 943 |
|
|
case 'g': case 'G':
|
| 944 |
|
|
tb->wb_write(CMD_REG, 0);
|
| 945 |
|
|
if (halted)
|
| 946 |
|
|
erase();
|
| 947 |
|
|
halted = false;
|
| 948 |
|
|
manual = false;
|
| 949 |
|
|
break;
|
| 950 |
|
|
case 'q': case 'Q':
|
| 951 |
|
|
done = true;
|
| 952 |
|
|
break;
|
| 953 |
|
|
case 'r': case 'R':
|
| 954 |
|
|
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
|
| 955 |
|
|
halted = true;
|
| 956 |
|
|
erase();
|
| 957 |
|
|
break;
|
| 958 |
|
|
case 's': case 'S':
|
| 959 |
|
|
tb->wb_write(CMD_REG, CMD_STEP);
|
| 960 |
|
|
manual = false;
|
| 961 |
|
|
break;
|
| 962 |
|
|
case 't': case 'T':
|
| 963 |
|
|
manual = true;
|
| 964 |
|
|
tb->tick();
|
| 965 |
|
|
break;
|
| 966 |
|
|
case ERR:
|
| 967 |
|
|
default:
|
| 968 |
|
|
if (!manual)
|
| 969 |
|
|
tb->tick();
|
| 970 |
|
|
}
|
| 971 |
|
|
|
| 972 |
|
|
if (manual) {
|
| 973 |
|
|
tb->show_state();
|
| 974 |
|
|
} else if (halted) {
|
| 975 |
|
|
if (tb->dbg_fp)
|
| 976 |
|
|
fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
|
| 977 |
|
|
tb->read_state();
|
| 978 |
|
|
} else
|
| 979 |
|
|
tb->show_state();
|
| 980 |
|
|
|
| 981 |
|
|
if (tb->m_core->i_rst)
|
| 982 |
|
|
done =true;
|
| 983 |
|
|
if (tb->bomb)
|
| 984 |
|
|
done = true;
|
| 985 |
|
|
}
|
| 986 |
|
|
|
| 987 |
|
|
} else { // Manual stepping mode
|
| 988 |
|
|
tb->show_state();
|
| 989 |
|
|
|
| 990 |
|
|
while('q' != tolower(chv = getch())) {
|
| 991 |
|
|
tb->tick();
|
| 992 |
|
|
tb->show_state();
|
| 993 |
|
|
|
| 994 |
|
|
if (tb->test_success())
|
| 995 |
|
|
break;
|
| 996 |
|
|
else if (tb->test_failure())
|
| 997 |
|
|
break;
|
| 998 |
|
|
}
|
| 999 |
|
|
}
|
| 1000 |
|
|
|
| 1001 |
|
|
endwin();
|
| 1002 |
|
|
|
| 1003 |
|
|
if (tb->test_success())
|
| 1004 |
|
|
printf("SUCCESS!\n");
|
| 1005 |
|
|
else if (tb->test_failure())
|
| 1006 |
|
|
printf("TEST FAILED!\n");
|
| 1007 |
|
|
else if (chv == 'q')
|
| 1008 |
|
|
printf("chv = %c\n", chv);
|
| 1009 |
|
|
exit(0);
|
| 1010 |
|
|
}
|
| 1011 |
|
|
|
