OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68 57 dgisselq
#define MAXERR          10000
69
 
70 76 dgisselq
 
71
class   SPARSEMEM {
72
public:
73
        bool    m_valid;
74
        unsigned int    m_a, m_d;
75
};
76
 
77
class   ZIPSTATE {
78
public:
79
        bool            m_valid, m_gie, m_last_pc_valid;
80
        unsigned int    m_sR[16], m_uR[16];
81
        unsigned int    m_p[20];
82
        unsigned int    m_last_pc, m_pc, m_sp;
83
        SPARSEMEM       m_smem[5];
84
        SPARSEMEM       m_imem[5];
85
        ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
86
 
87
        void    step(void) {
88
                m_last_pc_valid = true;
89
                m_last_pc = m_pc;
90
        }
91
};
92
 
93
 
94 2 dgisselq
// No particular "parameters" need definition or redefinition here.
95
class   ZIPPY_TB : public TESTB<Vzipsystem> {
96
public:
97 9 dgisselq
        unsigned long   m_mem_size;
98 2 dgisselq
        MEMSIM          m_mem;
99
        // QSPIFLASHSIM m_flash;
100 58 dgisselq
        FILE            *dbg_fp, *m_profile_fp;
101 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
102 34 dgisselq
        int             m_cursor;
103 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
104 76 dgisselq
        ZIPSTATE        m_state;
105 2 dgisselq
 
106 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
107 76 dgisselq
                if (false) {
108 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
109
                        dbg_flag = true;
110
                } else {
111
                        dbg_fp = NULL;
112
                        dbg_flag = false;
113
                }
114 2 dgisselq
                bomb = false;
115 34 dgisselq
                m_cursor = 0;
116 43 dgisselq
                m_show_user_timers = false;
117 58 dgisselq
 
118
                m_last_instruction_tickcount = 0l;
119
                if (true) {
120
                        m_profile_fp = fopen("pfile.bin","wb");
121
                } else {
122
                        m_profile_fp = NULL;
123
                }
124 2 dgisselq
        }
125
 
126 69 dgisselq
        ~ZIPPY_TB(void) {
127
                if (dbg_fp)
128
                        fclose(dbg_fp);
129
                if (m_profile_fp)
130
                        fclose(m_profile_fp);
131
        }
132
 
133 2 dgisselq
        void    reset(void) {
134
                // m_flash.debug(false);
135
                TESTB<Vzipsystem>::reset();
136
        }
137
 
138
        bool    on_tick(void) {
139
                tick();
140
                return true;
141
        }
142
 
143 76 dgisselq
        void    step(void) {
144
                wb_write(CMD_REG, CMD_STEP);
145
                m_state.step();
146
        }
147
 
148
        void    read_raw_state(void) {
149
                m_state.m_valid = false;
150
                for(int i=0; i<16; i++)
151
                        m_state.m_sR[i] = cmd_read(i);
152
                for(int i=0; i<16; i++)
153
                        m_state.m_uR[i] = cmd_read(i+16);
154
                for(int i=0; i<20; i++)
155
                        m_state.m_p[i]  = cmd_read(i+32);
156
 
157
                m_state.m_gie = (m_state.m_sR[14] & 0x020);
158
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
159
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
160
 
161
                if (m_state.m_last_pc_valid)
162
                        m_state.m_imem[0].m_a = m_state.m_last_pc;
163
                else
164
                        m_state.m_imem[0].m_a = m_state.m_pc - 1;
165
                m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
166
                m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
167
                m_state.m_imem[1].m_a = m_state.m_pc;
168
                m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
169
                m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
170
 
171
                for(int i=1; i<4; i++) {
172
                        if (!m_state.m_imem[i].m_valid) {
173
                                m_state.m_imem[i+1].m_valid = false;
174
                                m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
175
                                continue;
176
                        }
177
                        m_state.m_imem[i+1].m_a = zop_early_branch(
178
                                        m_state.m_imem[i].m_a,
179
                                        m_state.m_imem[i].m_d);
180
                        m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
181
                        m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
182
                }
183
 
184
                m_state.m_smem[0].m_a = m_state.m_sp;
185
                for(int i=1; i<5; i++)
186
                        m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
187
                for(int i=0; i<5; i++) {
188
                        m_state.m_smem[i].m_valid =
189
                                (m_state.m_imem[i].m_a > 0x10000);
190
                        m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
191
                }
192
                m_state.m_valid = true;
193
        }
194
 
195
        void    read_raw_state_cheating(void) {
196
                m_state.m_valid = false;
197
                for(int i=0; i<16; i++)
198
                        m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
199
                m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
200
                m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
201
                for(int i=0; i<16; i++)
202
                        m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
203
                m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
204
                m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__upc;
205
 
206
                m_state.m_gie = (m_state.m_sR[14] & 0x020);
207
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
208
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
209
 
210
                m_state.m_p[0] = m_core->v__DOT__pic_data;
211
                m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
212
                if (!m_show_user_timers) {
213
                        m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
214
                } else {
215
                        m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
216
                }
217
 
218
                m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
219
                m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
220
                m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
221
                m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
222
                m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
223
 
224
                m_state.m_p[ 8] = m_core->v__DOT__utc_data;
225
                m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
226
                m_state.m_p[10] = m_core->v__DOT__upc_data;
227
                m_state.m_p[11] = m_core->v__DOT__uic_data;
228
 
229
                m_state.m_p[12] = m_core->v__DOT__mtc_data;
230
                m_state.m_p[13] = m_core->v__DOT__moc_data;
231
                m_state.m_p[14] = m_core->v__DOT__mpc_data;
232
                m_state.m_p[15] = m_core->v__DOT__mic_data;
233
 
234
        }
235
 
236 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
237
                if (c)
238
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
239
                else
240
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
241 2 dgisselq
        }
242
 
243 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
244 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
245 34 dgisselq
                if (c)
246
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
247
                else
248
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
249 2 dgisselq
        }
250
 
251 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
252 76 dgisselq
                if (r < 16)
253
                        dispreg(y, x, n, m_state.m_sR[r], c);
254 34 dgisselq
                else
255 76 dgisselq
                        dispreg(y, x, n, m_state.m_uR[r-16], c);
256
                move(y,x+17);
257
 
258 69 dgisselq
#ifdef  OPT_PIPELINED
259 76 dgisselq
                addch( ((r == (int)(dcdA()&0x01f))&&(dcdvalid())
260 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
261 34 dgisselq
                        ?'a':((c)?'<':' '));
262 76 dgisselq
                addch( ((r == (int)(dcdB()&0x01f))&&(dcdvalid())
263 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
264 76 dgisselq
                        ?'b':' ');
265 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
266
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
267 76 dgisselq
                        ?'W':' ');
268
#else
269
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
270
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
271 34 dgisselq
                        ?'W':((c)?'<':' '));
272 76 dgisselq
#endif
273 2 dgisselq
        }
274
 
275
        void    showins(int y, const char *lbl, const int ce, const int valid,
276 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
277
                        const bool phase) {
278
                char    la[80], lb[80];
279 2 dgisselq
 
280
                if (ce)
281
                        mvprintw(y, 0, "Ck ");
282
                else
283
                        mvprintw(y, 0, "   ");
284
                if (stall)
285
                        printw("Stl ");
286
                else
287
                        printw("    ");
288
                printw("%s: 0x%08x", lbl, pc);
289
 
290
                if (valid) {
291
                        if (gie) attroff(A_BOLD);
292
                        else    attron(A_BOLD);
293 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
294
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
295
                                printw("  %-24s", la);
296
                        else
297
                                printw("  %-24s", lb);
298 2 dgisselq
                } else {
299
                        attroff(A_BOLD);
300
                        printw("  (0x%08x)%28s", m_mem[pc],"");
301
                }
302
                attroff(A_BOLD);
303
        }
304
 
305
        void    dbgins(const char *lbl, const int ce, const int valid,
306 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
307
                        const bool phase, const bool illegal) {
308
                char    la[80], lb[80];
309 2 dgisselq
 
310
                if (!dbg_fp)
311
                        return;
312
 
313
                if (ce)
314
                        fprintf(dbg_fp, "%s Ck ", lbl);
315
                else
316
                        fprintf(dbg_fp, "%s    ", lbl);
317
                if (stall)
318
                        fprintf(dbg_fp, "Stl ");
319
                else
320
                        fprintf(dbg_fp, "    ");
321
                fprintf(dbg_fp, "0x%08x:  ", pc);
322
 
323
                if (valid) {
324 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
325
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
326
                                fprintf(dbg_fp, "  %-24s", la);
327
                        else
328
                                fprintf(dbg_fp, "  %-24s", lb);
329 2 dgisselq
                } else {
330 76 dgisselq
                        fprintf(dbg_fp, "  (0x%08x)", m_mem[pc]);
331
                } if (illegal)
332
                        fprintf(dbg_fp, " (Illegal)");
333
                fprintf(dbg_fp, "\n");
334 2 dgisselq
        }
335
 
336
        void    show_state(void) {
337
                int     ln= 0;
338
 
339 76 dgisselq
                read_raw_state_cheating();
340
 
341 2 dgisselq
                mvprintw(ln,0, "Peripherals-SS"); ln++;
342 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
343 36 dgisselq
                printw(" %s",
344
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
345
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
346
                        );
347 39 dgisselq
#endif
348
 
349
#ifdef  OPT_EARLY_BRANCHING
350 69 dgisselq
                printw(" %s",
351 105 dgisselq
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":"  ");
352
                if (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
353
                        printw(" 0x%08x", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc);
354
                else    printw(" %10s", "");
355
                printw(" %s",
356
                        (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":"     ");
357 39 dgisselq
#endif
358 36 dgisselq
 
359
                /*
360 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
361
                        mvprintw(ln, 17, "%s%s",
362
                                ((m_core->v__DOT__sys_cyc)
363
                                &&(m_core->v__DOT__sys_we)
364
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
365
                                (m_core->v__DOT__trap_int)?"I":" ");
366
                */
367 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
368
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
369 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
370 57 dgisselq
 
371
                if (!m_show_user_timers) {
372
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
373
                } else {
374
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
375
                }
376
 
377 76 dgisselq
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
378 2 dgisselq
 
379
                ln++;
380 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
381
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
382
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
383
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
384 2 dgisselq
 
385 43 dgisselq
 
386
                if (!m_show_user_timers) {
387
                        ln++;
388 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
389
                        showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
390
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
391
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
392 43 dgisselq
                } else {
393
                        ln++;
394 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
395
                        showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
396
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
397
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
398 43 dgisselq
                }
399 2 dgisselq
 
400
                ln++;
401
                mvprintw(ln, 40, "%s %s",
402
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
403
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
404 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
405 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
406
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
407
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
408 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
409
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
410
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
411 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
412
                        attroff(A_BOLD);
413
                else
414
                        attron(A_BOLD);
415
                mvprintw(ln, 0, "Supervisor Registers");
416
                ln++;
417
 
418 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
419
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
420
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
421
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
422 2 dgisselq
 
423 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
424
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
425
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
426
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
427 2 dgisselq
 
428 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
429
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
430
                showreg(ln,40, "sR10", 10, (m_cursor==22));
431
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
432 2 dgisselq
 
433 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
434
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
435 76 dgisselq
 
436
                unsigned int cc = m_state.m_sR[14];
437 134 dgisselq
                if (false) {
438 76 dgisselq
                        mvprintw(ln,40, "%ssCC : 0x%08x",
439
                                (m_cursor==26)?">":" ", cc);
440
                } else {
441
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
442
                                (m_cursor==26)?">":" ",
443
                                (cc&0x01000)?"FE":"",
444
                                (cc&0x00800)?"DE":"",
445
                                (cc&0x00400)?"BE":"",
446
                                (cc&0x00200)?"TP":"",
447
                                (cc&0x00100)?"IL":"",
448
                                (cc&0x00080)?"BK":"",
449
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
450
                        mvprintw(ln, 54, "%s%s%s%s",
451
                                (cc&8)?"V":" ",
452
                                (cc&4)?"N":" ",
453
                                (cc&2)?"C":" ",
454
                                (cc&1)?"Z":" ");
455
                }
456
                showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
457 69 dgisselq
                mvprintw(ln,60,"%s",
458
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
459
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
460
                                ?"V"
461
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
462
                                &&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
463
                        :" "));
464 2 dgisselq
                ln++;
465
 
466
                if (m_core->v__DOT__thecpu__DOT__gie)
467
                        attron(A_BOLD);
468
                else
469
                        attroff(A_BOLD);
470 69 dgisselq
                mvprintw(ln, 0, "User Registers");
471
                mvprintw(ln, 42, "DCDR=%02x %s%s",
472
                        dcdR(),
473
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
474
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
475
                mvprintw(ln, 62, "OPR =%02x %s%s",
476
                        m_core->v__DOT__thecpu__DOT__opR,
477
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
478
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
479
                ln++;
480 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
481
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
482
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
483
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
484 2 dgisselq
 
485 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
486
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
487
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
488
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
489 2 dgisselq
 
490 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
491
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
492
                showreg(ln,40, "uR10", 26, (m_cursor==38));
493
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
494 2 dgisselq
 
495 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
496
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
497 76 dgisselq
                cc = m_state.m_uR[14];
498
                if (false) {
499
                        mvprintw(ln,40, "%cuCC : 0x%08x",
500
                                (m_cursor == 42)?'>':' ', cc);
501
                } else {
502
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
503
                                (m_cursor == 42)?'>':' ',
504
                                (cc & 0x1000)?"FE":"",
505
                                (cc & 0x0800)?"DE":"",
506
                                (cc & 0x0400)?"BE":"",
507
                                (cc & 0x0200)?"TP":"",
508
                                (cc & 0x0100)?"IL":"",
509
                                (cc & 0x0040)?"ST":"",
510
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
511
                        mvprintw(ln, 54, "%s%s%s%s",
512
                                (cc&8)?"V":" ",
513
                                (cc&4)?"N":" ",
514
                                (cc&2)?"C":" ",
515
                                (cc&1)?"Z":" ");
516
                }
517
                showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
518 69 dgisselq
                mvprintw(ln,60,"%s",
519
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
520
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
521
                                ?"V"
522
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
523
                                &&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
524
                        :" "));
525 2 dgisselq
 
526
                attroff(A_BOLD);
527
                ln+=1;
528
 
529 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
530 69 dgisselq
                ln++;
531
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
532
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
533
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
534
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
535
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
536
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
537
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
538
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
539
                        (m_core->v__DOT__wb_data)); ln++;
540 39 dgisselq
#else
541 69 dgisselq
 
542 76 dgisselq
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
543 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
544
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
545 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
546 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
547
                        m_core->v__DOT__thecpu__DOT__pf_pc,
548
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
549
 
550 2 dgisselq
                ln++;
551
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
552
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
553
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
554
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
555
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
556
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
557
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
558 69 dgisselq
                        (pfstall())?"STL":"   ",
559 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
560 39 dgisselq
#endif
561 2 dgisselq
 
562
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
563 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
564
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
565
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
566
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
567 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
568
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
569
                        (m_core->v__DOT__thecpu__DOT__mem_data),
570
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
571 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
572 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
573
// #define      OPT_PIPELINED_BUS_ACCESS
574
#ifdef  OPT_PIPELINED_BUS_ACCESS
575
                printw(" %x%x%c%c",
576
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
577
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
578 134 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_op_pipe)?'P':'-',
579 39 dgisselq
                        (mem_pipe_stalled())?'S':'-'); ln++;
580
#else
581
                ln++;
582
#endif
583 2 dgisselq
 
584 69 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
585 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
586 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
587
                        (m_core->o_wb_stb)?"STB":"   ",
588
                        (m_core->o_wb_we )?"WE":"  ",
589
                        (m_core->o_wb_addr),
590
                        (m_core->o_wb_data),
591
                        (m_core->i_wb_ack)?"ACK":"   ",
592
                        (m_core->i_wb_stall)?"STL":"   ",
593 69 dgisselq
                        (m_core->i_wb_data),
594
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
595 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
596
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
597
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
598 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
599
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
600
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
601
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
602 58 dgisselq
                        (!mem_stalled()),       //1
603 2 dgisselq
 
604 58 dgisselq
                        (mem_stalled()),
605 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
606
                        (m_core->v__DOT__thecpu__DOT__master_ce),
607
                        (mem_pipe_stalled()),
608 134 dgisselq
                        (!m_core->v__DOT__thecpu__DOT__r_op_pipe),
609 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
610
                        );
611 76 dgisselq
                printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__dcd_pipe);
612
                // mvprintw(4,4,"r_dcdI = 0x%06x",
613
                        // (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
614 39 dgisselq
#endif
615
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
616 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
617
                printw(" A:%c%c B:%c%c",
618 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
619
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
620 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
621
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
622 69 dgisselq
#else
623
                printw(" A:xx B:xx");
624 57 dgisselq
#endif
625 69 dgisselq
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
626 39 dgisselq
 
627
 
628 2 dgisselq
                showins(ln, "I ",
629 69 dgisselq
#ifdef  OPT_PIPELINED
630 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
631 69 dgisselq
#else
632
                        1,
633
#endif
634 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
635
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
636
                        m_core->v__DOT__thecpu__DOT__gie,
637
                        0,
638 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
639
                        true); ln++;
640 36 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
641 2 dgisselq
 
642
                showins(ln, "Dc",
643 69 dgisselq
                        dcd_ce(), dcdvalid(),
644 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
645 69 dgisselq
#ifdef  OPT_PIPELINED
646 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
647 69 dgisselq
#else
648
                        0,
649
#endif
650 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
651
#ifdef  OPT_VLIW
652
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
653
#else
654
                        false
655
#endif
656
                        ); ln++;
657 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
658
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
659
                        mvprintw(ln-1,10,"I");
660
                else
661
#endif
662
                if (m_core->v__DOT__thecpu__DOT__dcdM)
663
                        mvprintw(ln-1,10,"M");
664 2 dgisselq
 
665
                showins(ln, "Op",
666 69 dgisselq
                        op_ce(),
667 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
668
                        m_core->v__DOT__thecpu__DOT__op_gie,
669
                        m_core->v__DOT__thecpu__DOT__op_stall,
670 76 dgisselq
                        op_pc(),
671
#ifdef  OPT_VLIW
672
                        m_core->v__DOT__thecpu__DOT__r_op_phase
673
#else
674
                        false
675
#endif
676
                        ); ln++;
677 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
678
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
679
                        mvprintw(ln-1,10,"I");
680
                else
681
#endif
682
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
683
                        mvprintw(ln-1,10,"M");
684
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
685
                        mvprintw(ln-1,10,"A");
686 2 dgisselq
 
687
                showins(ln, "Al",
688
                        m_core->v__DOT__thecpu__DOT__alu_ce,
689
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
690
                        m_core->v__DOT__thecpu__DOT__alu_gie,
691 69 dgisselq
#ifdef  OPT_PIPELINED
692 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__alu_stall,
693 69 dgisselq
#else
694
                        0,
695
#endif
696 76 dgisselq
                        alu_pc(),
697
#ifdef  OPT_VLIW
698
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
699
#else
700
                        false
701
#endif
702
                        ); ln++;
703 39 dgisselq
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
704
                        mvprintw(ln-1,10,"W");
705 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
706
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
707
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
708
                        mvprintw(ln-1,10,"v");
709 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
710 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
711
                        mvprintw(ln-1,10,"I");
712 58 dgisselq
#endif
713 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
714
                        // mvprintw(ln-1,10,"i");
715 2 dgisselq
 
716 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
717 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
718
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
719 2 dgisselq
                mvprintw(ln-4, 48,
720
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
721
                printw("(%s:%02x,%x)",
722
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
723
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
724
                        (m_core->v__DOT__thecpu__DOT__op_gie)
725
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
726
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
727
 
728
                printw("(%s%s%s:%02x)",
729
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
730
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
731
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
732
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
733
                /*
734
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
735
                        m_core->v__DOT__thecpu__DOT__dcdI);
736
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
737
                        m_core->v__DOT__thecpu__DOT__opB);
738
                */
739 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
740 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
741 87 dgisselq
                        m_core->v__DOT__thecpu__DOT__opA,
742
                        m_core->v__DOT__thecpu__DOT__opB);
743 27 dgisselq
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
744
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
745
                else
746
                        printw("%8s","");
747 76 dgisselq
                mvprintw(ln-1, 48, "%s%s%s ",
748
                        (m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
749 87 dgisselq
                          :((m_core->v__DOT__thecpu__DOT__doalu__DOT__genblk2__DOT__r_busy)?"a":" "),
750 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"D"
751
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
752
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"F"
753
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
754
                printw("MEM: %s%s %s%s %s %-5s",
755 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
756 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
757
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
758 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
759 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
760 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
761
        }
762
 
763 43 dgisselq
        void    show_user_timers(bool v) {
764
                m_show_user_timers = v;
765
        }
766
 
767 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
768 57 dgisselq
                int     errcount = 0;
769 2 dgisselq
                if (dbg_fp) {
770
                        dbg_flag= true;
771
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
772
                }
773
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
774 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
775
                        errcount++;
776
                if (errcount >= MAXERR) {
777
                        endwin();
778
 
779
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
780
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
781
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
782
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
783
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
784
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
785
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
786 69 dgisselq
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
787
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
788
#ifdef  OPT_PIPELINED
789 57 dgisselq
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
790 69 dgisselq
#endif
791 57 dgisselq
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
792 105 dgisselq
// #ifdef       OPT_EARLY_BRANCHING
793 69 dgisselq
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
794 105 dgisselq
// #endif
795 57 dgisselq
 
796
                        exit(-2);
797
                }
798
 
799
                assert(errcount < MAXERR);
800 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
801
 
802
                if (dbg_flag)
803 76 dgisselq
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a, v);
804 2 dgisselq
                dbg_flag = false;
805
                return v;
806
        }
807
 
808 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
809 57 dgisselq
                int     errcount = 0;
810 34 dgisselq
                if ((a&0x0f)==0x0f)
811
                        dbg_flag = true;
812
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
813 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
814
                        errcount++;
815
                assert(errcount < MAXERR);
816 34 dgisselq
                if (dbg_flag)
817
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
818
                wb_write(CMD_DATA, v);
819
        }
820
 
821 27 dgisselq
        bool    halted(void) {
822
                return (m_core->v__DOT__cmd_halt != 0);
823
        }
824
 
825 2 dgisselq
        void    read_state(void) {
826
                int     ln= 0;
827 34 dgisselq
                bool    gie;
828 2 dgisselq
 
829 76 dgisselq
                read_raw_state();
830 34 dgisselq
                if (m_cursor < 0)
831
                        m_cursor = 0;
832
                else if (m_cursor >= 44)
833
                        m_cursor = 43;
834
 
835
                mvprintw(ln,0, "Peripherals-RS");
836
                mvprintw(ln,40,"%-40s", "CPU State: ");
837
                {
838
                        unsigned int v = wb_read(CMD_REG);
839
                        mvprintw(ln,51, "");
840
                        if (v & 0x010000)
841
                                printw("EXT-INT ");
842
                        if ((v & 0x003000) == 0x03000)
843
                                printw("Halted ");
844
                        else if (v & 0x001000)
845
                                printw("Sleeping ");
846
                        else if (v & 0x002000)
847 76 dgisselq
                                printw("User Mod ");
848 34 dgisselq
                        if (v & 0x008000)
849
                                printw("Break-Enabled ");
850
                        if (v & 0x000080)
851
                                printw("PIC Enabled ");
852
                } ln++;
853 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
854
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
855
                showval(ln,40, "WBUS", m_state.m_p[2], false);
856
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
857 2 dgisselq
                ln++;
858 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
859
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
860
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
861
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
862 2 dgisselq
 
863
                ln++;
864 43 dgisselq
                if (!m_show_user_timers) {
865 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
866
                        showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
867
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
868
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
869 43 dgisselq
                } else {
870 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
871
                        showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
872
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
873
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
874 43 dgisselq
                }
875 2 dgisselq
 
876
                ln++;
877
                ln++;
878 76 dgisselq
                unsigned int cc = m_state.m_sR[14];
879 2 dgisselq
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
880
                        m_core->v__DOT__thecpu__DOT__gie);
881 34 dgisselq
                gie = (cc & 0x020);
882
                if (gie)
883 2 dgisselq
                        attroff(A_BOLD);
884
                else
885
                        attron(A_BOLD);
886
                mvprintw(ln, 0, "Supervisor Registers");
887
                ln++;
888
 
889 76 dgisselq
                dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
890
                dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
891
                dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
892
                dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
893 2 dgisselq
 
894 76 dgisselq
                dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
895
                dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
896
                dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
897
                dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
898 2 dgisselq
 
899 76 dgisselq
                dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
900
                dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
901
                dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
902
                dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
903 2 dgisselq
 
904 76 dgisselq
                dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
905
                dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
906 2 dgisselq
 
907 76 dgisselq
                if (true) {
908
                        mvprintw(ln,40, "%ssCC : 0x%08x",
909
                                (m_cursor==26)?">":" ", cc);
910
                } else {
911
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
912
                                (m_cursor==26)?">":" ",
913
                                (cc&0x01000)?"FE":"",
914
                                (cc&0x00800)?"DE":"",
915
                                (cc&0x00400)?"BE":"",
916
                                (cc&0x00200)?"TP":"",
917
                                (cc&0x00100)?"IL":"",
918
                                (cc&0x00080)?"BK":"",
919
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
920
                        mvprintw(ln, 54, "%s%s%s%s",
921
                                (cc&8)?"V":" ",
922
                                (cc&4)?"N":" ",
923
                                (cc&2)?"C":" ",
924
                                (cc&1)?"Z":" ");
925
                }
926 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
927 2 dgisselq
                ln++;
928
 
929 34 dgisselq
                if (gie)
930 2 dgisselq
                        attron(A_BOLD);
931
                else
932
                        attroff(A_BOLD);
933 69 dgisselq
                mvprintw(ln, 0, "User Registers");
934
                mvprintw(ln, 42, "DCDR=%02x %s",
935
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
936
                mvprintw(ln, 62, "OPR =%02x %s%s",
937
                        m_core->v__DOT__thecpu__DOT__opR,
938
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
939
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
940
                ln++;
941 76 dgisselq
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
942
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
943
                dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
944
                dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
945 2 dgisselq
 
946 76 dgisselq
                dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
947
                dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
948
                dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
949
                dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
950 2 dgisselq
 
951 76 dgisselq
                dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
952
                dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
953
                dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
954
                dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
955 2 dgisselq
 
956 76 dgisselq
                dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
957
                dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
958
                cc = m_state.m_uR[14];
959
                if (false) {
960
                        mvprintw(ln,40, "%cuCC : 0x%08x",
961
                                (m_cursor == 42)?'>':' ', cc);
962
                } else {
963
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
964
                                (m_cursor == 42)?'>':' ',
965
                                (cc & 0x1000)?"FE":"",
966
                                (cc & 0x0800)?"DE":"",
967
                                (cc & 0x0400)?"BE":"",
968
                                (cc & 0x0200)?"TP":"",
969
                                (cc & 0x0100)?"IL":"",
970
                                (cc & 0x0040)?"ST":"",
971
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
972
                        mvprintw(ln, 54, "%s%s%s%s",
973
                                (cc&8)?"V":" ",
974
                                (cc&4)?"N":" ",
975
                                (cc&2)?"C":" ",
976
                                (cc&1)?"Z":" ");
977
                }
978
                dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
979 2 dgisselq
 
980
                attroff(A_BOLD);
981
                ln+=2;
982
 
983
                ln+=3;
984
 
985
                showins(ln, "I ",
986 69 dgisselq
#ifdef  OPT_PIPELINED
987 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
988 69 dgisselq
#else
989
                        1,
990
#endif
991 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
992
                        m_core->v__DOT__thecpu__DOT__gie,
993
                        0,
994 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
995
                        true); ln++;
996 57 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
997 2 dgisselq
 
998
                showins(ln, "Dc",
999 69 dgisselq
                        dcd_ce(), dcdvalid(),
1000 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
1001 69 dgisselq
#ifdef  OPT_PIPELINED
1002 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
1003 69 dgisselq
#else
1004
                        0,
1005
#endif
1006 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1007
#ifdef  OPT_VLIW
1008
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
1009
#else
1010
                        false
1011
#endif
1012
                        ); ln++;
1013 2 dgisselq
 
1014
                showins(ln, "Op",
1015 69 dgisselq
                        op_ce(),
1016 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
1017
                        m_core->v__DOT__thecpu__DOT__op_gie,
1018
                        m_core->v__DOT__thecpu__DOT__op_stall,
1019 76 dgisselq
                        op_pc(),
1020
#ifdef  OPT_VLIW
1021
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1022
#else
1023
                        false
1024
#endif
1025
                        ); ln++;
1026 2 dgisselq
 
1027
                showins(ln, "Al",
1028
                        m_core->v__DOT__thecpu__DOT__alu_ce,
1029
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1030
                        m_core->v__DOT__thecpu__DOT__alu_gie,
1031 69 dgisselq
#ifdef  OPT_PIPELINED
1032 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__alu_stall,
1033 69 dgisselq
#else
1034
                        0,
1035
#endif
1036 76 dgisselq
                        alu_pc(),
1037
#ifdef  OPT_VLIW
1038
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1039
#else
1040
                        false
1041
#endif
1042
                        ); ln++;
1043 2 dgisselq
        }
1044 69 dgisselq
 
1045 2 dgisselq
        void    tick(void) {
1046
                int gie = m_core->v__DOT__thecpu__DOT__gie;
1047
                /*
1048
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
1049
                                                m_core->o_qspi_sck,
1050
                                                m_core->o_qspi_dat);
1051
                */
1052
 
1053 11 dgisselq
                int stb = m_core->o_wb_stb;
1054
                if ((m_core->o_wb_addr & (-1<<20))!=1)
1055
                        stb = 0;
1056
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
1057
                        m_core->i_wb_ack = 1;
1058 2 dgisselq
 
1059
                if ((dbg_flag)&&(dbg_fp)) {
1060 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
1061 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
1062
                                (m_core->i_dbg_stb)?"STB":
1063
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
1064
                                ((m_core->i_dbg_we)?"WE":"  "),
1065
                                (m_core->i_dbg_addr),0,
1066
                                m_core->i_dbg_data,
1067
                                (m_core->o_dbg_ack)?"ACK":"   ",
1068
                                (m_core->o_dbg_stall)?"STALL":"     ",
1069
                                (m_core->o_dbg_data),
1070
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
1071
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
1072 69 dgisselq
                                (dcdvalid())?"DCDV ":"",
1073 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
1074
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
1075 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
1076
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
1077 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
1078
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
1079
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
1080
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
1081
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
1082
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
1083
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
1084
                                (m_core->v__DOT__sys_we)?"WE":"  ",
1085
                                (m_core->v__DOT__sys_addr),
1086
                                (m_core->v__DOT__dbg_addr),
1087
                                (m_core->v__DOT__sys_data),
1088
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
1089
                                (m_core->v__DOT__wb_data));
1090
                }
1091
 
1092
                if (dbg_fp)
1093
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
1094 69 dgisselq
                                dcd_ce(),
1095 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
1096 69 dgisselq
                                op_ce(),
1097 39 dgisselq
                                op_pc(),
1098 69 dgisselq
                                dcdA()&0x01f,
1099 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opR,
1100
                                m_core->v__DOT__cmd_halt,
1101
                                m_core->v__DOT__cpu_halt,
1102
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1103
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1104
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1105
                                m_core->v__DOT__thecpu__DOT__alu_reg,
1106
                                m_core->v__DOT__thecpu__DOT__ipc,
1107
                                m_core->v__DOT__thecpu__DOT__upc);
1108
 
1109
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
1110
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
1111 69 dgisselq
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
1112 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1113
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1114
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
1115
                                m_core->v__DOT__cmd_addr,
1116
                                m_core->v__DOT__dbg_idata,
1117
                                m_core->v__DOT__thecpu__DOT__master_ce,
1118
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1119
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1120
                                m_core->v__DOT__thecpu__DOT__mem_valid);
1121
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
1122
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
1123
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1124
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1125
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
1126
                                m_core->v__DOT__cmd_addr,
1127
                                m_core->v__DOT__dbg_idata,
1128
                                m_core->v__DOT__thecpu__DOT__master_ce,
1129
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1130
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1131
                                m_core->v__DOT__thecpu__DOT__mem_valid,
1132
                                m_core->v__DOT__thecpu__DOT__w_iflags,
1133
                                m_core->v__DOT__thecpu__DOT__w_uflags);
1134 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
1135
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1136 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
1137
                                m_core->v__DOT__thecpu__DOT__op_break);
1138 36 dgisselq
                } else if ((dbg_fp)&&
1139
                                ((m_core->v__DOT__thecpu__DOT__op_break)
1140 76 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
1141 36 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
1142
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
1143 76 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
1144 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1145
                                m_core->v__DOT__thecpu__DOT__break_en,
1146
                                m_core->v__DOT__thecpu__DOT__dcd_break,
1147 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__op_break,
1148
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
1149 2 dgisselq
                }
1150
 
1151 34 dgisselq
                if (dbg_fp) {
1152
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
1153
                                fprintf(dbg_fp, "\tClear Pipeline\n");
1154
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
1155
                                fprintf(dbg_fp, "\tNew PC\n");
1156
                }
1157
 
1158 36 dgisselq
                if (dbg_fp)
1159
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
1160
                if (false) {
1161
                        m_core->i_clk = 1;
1162
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1163
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1164
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1165
                        eval();
1166
                        m_core->i_clk = 0;
1167
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1168
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1169
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1170
                        eval();
1171
                        m_tickcount++;
1172
                } else {
1173
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1174
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1175
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1176 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
1177
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
1178
                                m_core->i_wb_err = 1;
1179
                        else
1180
                                m_core->i_wb_err = 0;
1181 36 dgisselq
                        TESTB<Vzipsystem>::tick();
1182
                }
1183 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
1184
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
1185
                                (gie)?"User":"Supervisor",
1186
                                (gie)?"Supervisor":"User",
1187
                                m_core->v__DOT__thecpu__DOT__ipc,
1188
                                m_core->v__DOT__thecpu__DOT__upc,
1189
                                m_core->v__DOT__thecpu__DOT__pf_pc);
1190
                } if (dbg_fp) {
1191 76 dgisselq
#ifdef  OPT_TRADITIONAL_PFCACHE
1192
                        fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
1193 69 dgisselq
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
1194
                                m_core->v__DOT__thecpu__DOT__pf_pc,
1195 105 dgisselq
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc,
1196
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
1197 69 dgisselq
                                &&(dcdvalid())
1198
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
1199
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
1200
                                m_core->v__DOT__thecpu__DOT__instruction_pc,
1201
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
1202 76 dgisselq
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
1203
                                (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
1204 69 dgisselq
#endif
1205
                        dbgins("Dc - ",
1206
                                dcd_ce(), dcdvalid(),
1207 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
1208 69 dgisselq
#ifdef  OPT_PIPELINED
1209 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
1210 69 dgisselq
#else
1211
                                0,
1212
#endif
1213 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1214
#ifdef  OPT_VLIW
1215
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
1216
#else
1217
                                false,
1218
#endif
1219
#ifdef  OPT_ILLEGAL_INSTRUCTION
1220
                                m_core->v__DOT__thecpu__DOT__dcd_illegal
1221
#else
1222
                                false
1223
#endif
1224
                                );
1225 69 dgisselq
                        dbgins("Op - ",
1226
                                op_ce(),
1227 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opvalid,
1228
                                m_core->v__DOT__thecpu__DOT__op_gie,
1229
                                m_core->v__DOT__thecpu__DOT__op_stall,
1230 76 dgisselq
                                op_pc(),
1231
#ifdef  OPT_VLIW
1232
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
1233
#else
1234
                                false,
1235 57 dgisselq
#endif
1236 76 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
1237
                                m_core->v__DOT__thecpu__DOT__op_illegal
1238
#else
1239
                                false
1240
#endif
1241
                                );
1242 2 dgisselq
                        dbgins("Al - ",
1243
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1244
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1245
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1246 69 dgisselq
#ifdef  OPT_PIPELINED
1247 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1248 69 dgisselq
#else
1249
                                0,
1250
#endif
1251 76 dgisselq
                                alu_pc(),
1252
#ifdef  OPT_VLIW
1253
                                m_core->v__DOT__thecpu__DOT__r_alu_phase,
1254
#else
1255
                                false,
1256
#endif
1257
#ifdef  OPT_ILLEGAL_INSTRUCTION
1258
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
1259
#else
1260
                                false
1261
#endif
1262
                                );
1263 2 dgisselq
 
1264
                }
1265 58 dgisselq
 
1266
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1267
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
1268
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1269
                        if (m_profile_fp) {
1270
                                unsigned buf[2];
1271
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
1272
                                buf[1] = iticks;
1273
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1274
                        }
1275
                        m_last_instruction_tickcount = m_tickcount;
1276
                }
1277 2 dgisselq
        }
1278
 
1279
        bool    test_success(void) {
1280
                return ((!m_core->v__DOT__thecpu__DOT__gie)
1281
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1282
        }
1283
 
1284 39 dgisselq
        unsigned        op_pc(void) {
1285
                /*
1286
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
1287
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
1288
                        r--;
1289
                return r;
1290
                */
1291
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
1292
        }
1293
 
1294 69 dgisselq
        bool    dcd_ce(void) {
1295
#ifdef  OPT_PIPELINED
1296
                return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
1297
#else
1298
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
1299
#endif
1300
        } bool  dcdvalid(void) {
1301
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
1302
        }
1303
        bool    pfstall(void) {
1304
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1305
                        ||(m_core->v__DOT__cpu_stall));
1306
        }
1307
        unsigned        dcdR(void) {
1308
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1309
        }
1310
        unsigned        dcdA(void) {
1311
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1312
        }
1313
        unsigned        dcdB(void) {
1314
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1315
        }
1316
 
1317
        bool    op_ce(void) {
1318
#ifdef  OPT_PIPELINED
1319
                return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
1320
#else
1321
                // return (dcdvalid())&&(opvalid())
1322
                //      &&(m_core->v__DOT__thecpu__DOT__op_stall);
1323
                return  dcdvalid();
1324
#endif
1325
        } bool  opvalid(void) {
1326
                return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
1327
        }
1328
 
1329 58 dgisselq
        bool    mem_busy(void) {
1330
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1331 69 dgisselq
#ifdef  OPT_PIPELINED
1332 58 dgisselq
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1333 69 dgisselq
#else
1334
                return 0;
1335
#endif
1336 58 dgisselq
        }
1337
 
1338
        bool    mem_stalled(void) {
1339
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1340
 
1341
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1342
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1343
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
1344
 
1345 69 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
1346
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1347
                a = mem_pipe_stalled();
1348 134 dgisselq
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
1349 69 dgisselq
#else
1350
                a = false;
1351
                b = false;
1352
#endif
1353 58 dgisselq
                d = ((wr_write_pc)||(wr_write_cc));
1354
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1355 69 dgisselq
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1356 58 dgisselq
                        &&d);
1357
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
1358
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1359
        }
1360
 
1361 39 dgisselq
        unsigned        alu_pc(void) {
1362
                /*
1363
                unsigned        r = op_pc();
1364
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1365
                        r--;
1366
                return r;
1367
                */
1368
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
1369
        }
1370
 
1371
#ifdef  OPT_PIPELINED_BUS_ACCESS
1372 69 dgisselq
        bool    mem_pipe_stalled(void) {
1373 39 dgisselq
                int     r = 0;
1374
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
1375
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1376
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1377
                        ||(
1378
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1379
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1380
                return r;
1381
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1382
        }
1383
#endif
1384
 
1385 2 dgisselq
        bool    test_failure(void) {
1386 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1387
                        return 0;
1388
                else if (m_core->v__DOT__thecpu__DOT__gie)
1389 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
1390 134 dgisselq
                else if (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7883ffff)
1391
                        return true; // ADD to PC instruction
1392
                else // MOV to PC instruction
1393 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
1394 43 dgisselq
                /*
1395 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1396 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1397 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1398 43 dgisselq
                */
1399 2 dgisselq
        }
1400
 
1401
        void    wb_write(unsigned a, unsigned int v) {
1402 36 dgisselq
                int     errcount = 0;
1403 2 dgisselq
                mvprintw(0,35, "%40s", "");
1404
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1405
                m_core->i_dbg_cyc = 1;
1406
                m_core->i_dbg_stb = 1;
1407
                m_core->i_dbg_we  = 1;
1408
                m_core->i_dbg_addr = a & 1;
1409
                m_core->i_dbg_data = v;
1410
 
1411
                tick();
1412 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1413 2 dgisselq
                        tick();
1414
 
1415
                m_core->i_dbg_stb = 0;
1416 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1417 2 dgisselq
                        tick();
1418
 
1419
                // Release the bus
1420
                m_core->i_dbg_cyc = 0;
1421
                m_core->i_dbg_stb = 0;
1422
                tick();
1423
                mvprintw(0,35, "%40s", "");
1424
                mvprintw(0,40, "wb_write -- complete");
1425 36 dgisselq
 
1426
 
1427
                if (errcount >= 100)
1428
                        bomb = true;
1429 2 dgisselq
        }
1430
 
1431
        unsigned long   wb_read(unsigned a) {
1432
                unsigned int    v;
1433 36 dgisselq
                int     errcount = 0;
1434 2 dgisselq
                mvprintw(0,35, "%40s", "");
1435
                mvprintw(0,40, "wb_read(0x%08x)", a);
1436
                m_core->i_dbg_cyc = 1;
1437
                m_core->i_dbg_stb = 1;
1438
                m_core->i_dbg_we  = 0;
1439
                m_core->i_dbg_addr = a & 1;
1440
 
1441
                tick();
1442 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1443 2 dgisselq
                        tick();
1444
 
1445
                m_core->i_dbg_stb = 0;
1446 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1447 2 dgisselq
                        tick();
1448
                v = m_core->o_dbg_data;
1449
 
1450
                // Release the bus
1451
                m_core->i_dbg_cyc = 0;
1452
                m_core->i_dbg_stb = 0;
1453
                tick();
1454
 
1455
                mvprintw(0,35, "%40s", "");
1456
                mvprintw(0,40, "wb_read = 0x%08x", v);
1457
 
1458 36 dgisselq
                if (errcount >= 100)
1459
                        bomb = true;
1460 2 dgisselq
                return v;
1461
        }
1462
 
1463 34 dgisselq
        void    cursor_up(void) {
1464
                if (m_cursor > 3)
1465
                        m_cursor -= 4;
1466
        } void  cursor_down(void) {
1467
                if (m_cursor < 40)
1468
                        m_cursor += 4;
1469
        } void  cursor_left(void) {
1470
                if (m_cursor > 0)
1471
                        m_cursor--;
1472
                else    m_cursor = 43;
1473
        } void  cursor_right(void) {
1474
                if (m_cursor < 43)
1475
                        m_cursor++;
1476
                else    m_cursor = 0;
1477
        }
1478
 
1479
        int     cursor(void) { return m_cursor; }
1480 2 dgisselq
};
1481
 
1482 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1483
        int     wy, wx, ra;
1484
        int     c = tb->cursor();
1485
 
1486
        wx = (c & 0x03) * 20 + 9;
1487
        wy = (c>>2);
1488
        if (wy >= 3+4)
1489
                wy++;
1490
        if (wy > 3)
1491
                wy += 2;
1492
        wy++;
1493
 
1494
        if (c >= 12)
1495
                ra = c - 12;
1496
        else
1497
                ra = c + 32;
1498
 
1499
        bool    done = false;
1500
        char    str[16];
1501
        int     pos = 0; str[pos] = '\0';
1502
        while(!done) {
1503
                int     chv = getch();
1504
                switch(chv) {
1505
                case KEY_ESCAPE:
1506
                        pos = 0; str[pos] = '\0'; done = true;
1507
                        break;
1508
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1509
                        done = true;
1510
                        break;
1511
                case KEY_LEFT: case KEY_BACKSPACE:
1512
                        if (pos > 0) pos--;
1513
                        break;
1514 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1515 34 dgisselq
                case KEY_CLEAR:
1516
                        pos = 0;
1517
                        break;
1518
                case '0': case ' ': str[pos++] = '0'; break;
1519
                case '1': str[pos++] = '1'; break;
1520
                case '2': str[pos++] = '2'; break;
1521
                case '3': str[pos++] = '3'; break;
1522
                case '4': str[pos++] = '4'; break;
1523
                case '5': str[pos++] = '5'; break;
1524
                case '6': str[pos++] = '6'; break;
1525
                case '7': str[pos++] = '7'; break;
1526
                case '8': str[pos++] = '8'; break;
1527
                case '9': str[pos++] = '9'; break;
1528
                case 'A': case 'a': str[pos++] = 'A'; break;
1529
                case 'B': case 'b': str[pos++] = 'B'; break;
1530
                case 'C': case 'c': str[pos++] = 'C'; break;
1531
                case 'D': case 'd': str[pos++] = 'D'; break;
1532
                case 'E': case 'e': str[pos++] = 'E'; break;
1533
                case 'F': case 'f': str[pos++] = 'F'; break;
1534
                }
1535
 
1536
                if (pos > 8)
1537
                        pos = 8;
1538
                str[pos] = '\0';
1539
 
1540
                attron(A_NORMAL | A_UNDERLINE);
1541
                mvprintw(wy, wx, "%-8s", str);
1542
                if (pos > 0) {
1543
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1544
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1545
                }
1546
                attrset(A_NORMAL);
1547
        }
1548
 
1549
        if (pos > 0) {
1550
                int     v;
1551
                v = strtoul(str, NULL, 16);
1552
                if (!tb->halted()) {
1553
                        switch(ra) {
1554
                        case 15:
1555
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1556
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1557
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1558
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1559
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1560
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1561 69 dgisselq
#ifdef  OPT_PIPELINED
1562 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1563 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1564
#endif
1565 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1566
                                }
1567
                                break;
1568
                        case 31:
1569
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1570
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1571
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1572
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1573
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1574
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1575 69 dgisselq
#ifdef  OPT_PIPELINED
1576 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1577 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1578
#endif
1579 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1580
                                }
1581
                                break;
1582
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1583
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1584 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1585 69 dgisselq
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1586 34 dgisselq
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1587
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1588
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1589
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1590
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1591
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1592
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1593
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1594
                        default:
1595
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1596
                                break;
1597
                        }
1598
                } else
1599
                        tb->cmd_write(ra, v);
1600
        }
1601
}
1602
 
1603 27 dgisselq
void    usage(void) {
1604
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1605
        printf("\n");
1606
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1607
        printf("\t-a\tSets the testbench to run automatically without any\n");
1608
        printf("\t\tuser interaction.\n");
1609
        printf("\n");
1610
        printf("\tUser Commands:\n");
1611
        printf("\t\tWhen the test bench is run interactively, the following\n");
1612
        printf("\t\tkey strokes are recognized:\n");
1613
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1614
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1615
        printf("\t\t\tuser intervention.\n");
1616
        printf("\t\t\'q\'\tQuit the simulation.\n");
1617
        printf("\t\t\'r\'\tReset the processor.\n");
1618
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1619
        printf("\t\t\tThis may consume more than one tick.\n");
1620
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1621
}
1622 2 dgisselq
 
1623 43 dgisselq
bool    signalled = false;
1624
 
1625
void    sigint(int v) {
1626
        signalled = true;
1627
}
1628
 
1629 2 dgisselq
int     main(int argc, char **argv) {
1630
        Verilated::commandArgs(argc, argv);
1631
        ZIPPY_TB        *tb = new ZIPPY_TB();
1632 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1633 2 dgisselq
 
1634
        // mem[0x00000] = 0xbe000010; // Halt instruction
1635
        unsigned int mptr = 0;
1636
 
1637 43 dgisselq
        signal(SIGINT, sigint);
1638
 
1639 9 dgisselq
        if (argc <= 1) {
1640 27 dgisselq
                usage();
1641
                exit(-1);
1642 9 dgisselq
        } else {
1643
                for(int argn=1; argn<argc; argn++) {
1644 27 dgisselq
                        if (argv[argn][0] == '-') {
1645
                                switch(argv[argn][1]) {
1646
                                case 'a':
1647
                                        autorun = true;
1648
                                        break;
1649
                                case 'e':
1650
                                        exit_on_done = true;
1651
                                        break;
1652
                                case 'h':
1653
                                        usage();
1654
                                        exit(0);
1655
                                        break;
1656 36 dgisselq
                                case 's':
1657
                                        autostep = true;
1658
                                        break;
1659 27 dgisselq
                                default:
1660
                                        usage();
1661
                                        exit(-1);
1662
                                        break;
1663
                                }
1664
                        } else if (access(argv[argn], R_OK)==0) {
1665 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1666 58 dgisselq
                                int     nr, nv = 0;
1667 9 dgisselq
                                if (fp == NULL) {
1668
                                        printf("Cannot open %s\n", argv[argn]);
1669
                                        perror("O/S Err: ");
1670
                                        exit(-1);
1671 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1672 9 dgisselq
                                fclose(fp);
1673 58 dgisselq
                                mptr+= nr;
1674
                                if (nr == 0) {
1675
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
1676
                                        perror("O/S  Err?:");
1677
                                        exit(-2);
1678
                                } for(int i=0; i<nr; i++) {
1679
                                        if (tb->m_mem[mptr-nr+i])
1680
                                                nv++;
1681
                                } if (nv == 0) {
1682
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
1683
                                        perror("O/S  Err?:");
1684
                                        exit(-2);
1685
                                }
1686
                        } else {
1687
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
1688
                                exit(-2);
1689 9 dgisselq
                        }
1690
                }
1691
        }
1692
 
1693 58 dgisselq
 
1694
        assert(mptr > 0);
1695
 
1696 27 dgisselq
        if (autorun) {
1697
                bool    done = false;
1698 2 dgisselq
 
1699 27 dgisselq
                printf("Running in non-interactive mode\n");
1700
                tb->reset();
1701
                for(int i=0; i<2; i++)
1702
                        tb->tick();
1703
                tb->m_core->v__DOT__cmd_halt = 0;
1704
                while(!done) {
1705
                        tb->tick();
1706
 
1707
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1708
                                // tb->m_core->v__DOT__cmd_halt = 0;
1709
                                // tb->m_core->v__DOT__cmd_step = 0;
1710
 
1711 34 dgisselq
                        /*
1712 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1713
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1714
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1715
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1716 34 dgisselq
                        */
1717 27 dgisselq
 
1718
                        done = (tb->test_success())||(tb->test_failure());
1719 43 dgisselq
                        done = done || signalled;
1720 27 dgisselq
                }
1721 36 dgisselq
        } else if (autostep) {
1722
                bool    done = false;
1723
 
1724
                printf("Running in non-interactive mode, via step commands\n");
1725
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1726
                while(!done) {
1727
                        tb->wb_write(CMD_REG, CMD_STEP);
1728
                        done = (tb->test_success())||(tb->test_failure());
1729 43 dgisselq
                        done = done || signalled;
1730 36 dgisselq
                }
1731 27 dgisselq
        } else { // Interactive
1732
                initscr();
1733
                raw();
1734
                noecho();
1735
                keypad(stdscr, true);
1736
 
1737 69 dgisselq
                // tb->reset();
1738
                // for(int i=0; i<2; i++)
1739
                        // tb->tick();
1740
                tb->m_core->v__DOT__cmd_reset = 1;
1741 27 dgisselq
                tb->m_core->v__DOT__cmd_halt = 0;
1742
 
1743 76 dgisselq
                /*
1744
                // For debugging purposes: do we wish to skip some number of
1745
                // instructions to fast forward to a time of interest??
1746
                for(int i=0; i<0x4d0; i++) {
1747
                        tb->m_core->v__DOT__cmd_halt = 0;
1748
                        tb->tick();
1749
                }
1750
                */
1751
 
1752 27 dgisselq
                int     chv = 'q';
1753
 
1754 43 dgisselq
                bool    done = false, halted = true, manual = true,
1755
                        high_speed = false;
1756 2 dgisselq
 
1757
                halfdelay(1);
1758 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1759 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1760
                        // tb->show_state();
1761
 
1762
                while(!done) {
1763 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1764 87 dgisselq
                                // chv = getch();
1765
 
1766 43 dgisselq
                                struct  pollfd  fds[1];
1767
                                fds[0].fd = STDIN_FILENO;
1768
                                fds[0].events = POLLIN;
1769 87 dgisselq
 
1770 43 dgisselq
                                if (poll(fds, 1, 0) > 0)
1771
                                        chv = getch();
1772
                                else
1773
                                        chv = ERR;
1774 87 dgisselq
 
1775 43 dgisselq
                        } else {
1776
                                chv = getch();
1777
                        }
1778 2 dgisselq
                        switch(chv) {
1779
                        case 'h': case 'H':
1780
                                tb->wb_write(CMD_REG, CMD_HALT);
1781
                                if (!halted)
1782
                                        erase();
1783
                                halted = true;
1784
                                break;
1785 43 dgisselq
                        case 'G':
1786
                                high_speed = true;
1787 87 dgisselq
                                // cbreak();
1788 43 dgisselq
                        case 'g':
1789 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1790
                                if (halted)
1791
                                        erase();
1792
                                halted = false;
1793
                                manual = false;
1794
                                break;
1795 43 dgisselq
                        case 'm':
1796
                                tb->show_user_timers(false);
1797
                                break;
1798 2 dgisselq
                        case 'q': case 'Q':
1799
                                done = true;
1800
                                break;
1801
                        case 'r': case 'R':
1802 36 dgisselq
                                if (manual)
1803
                                        tb->reset();
1804
                                else
1805
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1806 2 dgisselq
                                halted = true;
1807
                                erase();
1808
                                break;
1809 39 dgisselq
                        case 's':
1810 34 dgisselq
                                if (!halted)
1811 27 dgisselq
                                        erase();
1812 76 dgisselq
                                tb->step();
1813 2 dgisselq
                                manual = false;
1814 34 dgisselq
                                halted = true;
1815 87 dgisselq
                                // if (high_speed)
1816
                                        // halfdelay(1);
1817 43 dgisselq
                                high_speed = false;
1818 2 dgisselq
                                break;
1819 39 dgisselq
                        case 'S':
1820 34 dgisselq
                                if ((!manual)||(halted))
1821 27 dgisselq
                                        erase();
1822 2 dgisselq
                                manual = true;
1823 39 dgisselq
                                halted = true;
1824 87 dgisselq
                                // if (high_speed)
1825
                                        // halfdelay(1);
1826 43 dgisselq
                                high_speed = false;
1827 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1828
                                tb->m_core->v__DOT__cmd_step = 1;
1829
                                tb->eval();
1830
                                tb->tick();
1831
                                break;
1832
                        case 'T': // 
1833
                                if ((!manual)||(halted))
1834
                                        erase();
1835
                                manual = true;
1836
                                halted = true;
1837 87 dgisselq
                                // if (high_speed)
1838
                                        // halfdelay(1);
1839 43 dgisselq
                                high_speed = false;
1840 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1841
                                tb->m_core->v__DOT__cmd_step = 0;
1842
                                tb->eval();
1843
                                tb->tick();
1844
                                break;
1845
                        case 't':
1846
                                if ((!manual)||(halted))
1847
                                        erase();
1848
                                manual = true;
1849 34 dgisselq
                                halted = false;
1850 87 dgisselq
                                // if (high_speed)
1851
                                        // halfdelay(1);
1852 43 dgisselq
                                high_speed = false;
1853 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1854 76 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1855 27 dgisselq
                //              tb->m_core->v__DOT__cmd_step = 0;
1856 2 dgisselq
                                tb->tick();
1857
                                break;
1858 43 dgisselq
                        case 'u':
1859
                                tb->show_user_timers(true);
1860
                                break;
1861 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1862
                                get_value(tb);
1863
                                break;
1864
                        case    KEY_UP:         tb->cursor_up();        break;
1865
                        case    KEY_DOWN:       tb->cursor_down();      break;
1866
                        case    KEY_LEFT:       tb->cursor_left();      break;
1867
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1868 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1869 34 dgisselq
                        case ERR: case KEY_CLEAR:
1870 2 dgisselq
                        default:
1871
                                if (!manual)
1872
                                        tb->tick();
1873
                        }
1874
 
1875
                        if (manual) {
1876
                                tb->show_state();
1877
                        } else if (halted) {
1878
                                if (tb->dbg_fp)
1879
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1880
                                tb->read_state();
1881
                        } else
1882
                                tb->show_state();
1883
 
1884
                        if (tb->m_core->i_rst)
1885
                                done =true;
1886 43 dgisselq
                        if ((tb->bomb)||(signalled))
1887 2 dgisselq
                                done = true;
1888 27 dgisselq
 
1889
                        if (exit_on_done) {
1890
                                if (tb->test_success())
1891
                                        done = true;
1892
                                if (tb->test_failure())
1893
                                        done = true;
1894
                        }
1895 2 dgisselq
                }
1896 27 dgisselq
                endwin();
1897
        }
1898
#ifdef  MANUAL_STEPPING_MODE
1899
         else { // Manual stepping mode
1900 2 dgisselq
                tb->show_state();
1901
 
1902
                while('q' != tolower(chv = getch())) {
1903
                        tb->tick();
1904
                        tb->show_state();
1905
 
1906
                        if (tb->test_success())
1907
                                break;
1908
                        else if (tb->test_failure())
1909
                                break;
1910 43 dgisselq
                        else if (signalled)
1911
                                break;
1912 2 dgisselq
                }
1913
        }
1914 27 dgisselq
#endif
1915 2 dgisselq
 
1916 43 dgisselq
        printf("\n");
1917 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1918
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1919 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1920 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1921
                printf("Instructions / Clock: %.2f\n",
1922
                        (double)tb->m_core->v__DOT__mic_data
1923
                        / (double)tb->m_core->v__DOT__mtc_data);
1924 36 dgisselq
 
1925
        int     rcode = 0;
1926
        if (tb->bomb) {
1927
                printf("TEST BOMBED\n");
1928
                rcode = -1;
1929
        } else if (tb->test_success()) {
1930 2 dgisselq
                printf("SUCCESS!\n");
1931 36 dgisselq
        } else if (tb->test_failure()) {
1932
                rcode = -2;
1933 2 dgisselq
                printf("TEST FAILED!\n");
1934 36 dgisselq
        } else
1935 27 dgisselq
                printf("User quit\n");
1936 43 dgisselq
        delete tb;
1937 36 dgisselq
        exit(rcode);
1938 2 dgisselq
}
1939
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.