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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 36

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 2 dgisselq
 
41
#include <ctype.h>
42
#include <ncurses.h>
43
 
44
#include "verilated.h"
45
#include "Vzipsystem.h"
46
 
47
#include "testb.h"
48
// #include "twoc.h"
49
// #include "qspiflashsim.h"
50
#include "memsim.h"
51
#include "zopcodes.h"
52
#include "zparser.h"
53
 
54
#define CMD_REG         0
55
#define CMD_DATA        1
56
#define CMD_HALT        (1<<10)
57
#define CMD_STALL       (1<<9)
58
#define CMD_INT         (1<<7)
59
#define CMD_RESET       (1<<6)
60 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
61 2 dgisselq
 
62 34 dgisselq
#define KEY_ESCAPE      27
63
#define KEY_RETURN      10
64 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
65 2 dgisselq
 
66
// No particular "parameters" need definition or redefinition here.
67
class   ZIPPY_TB : public TESTB<Vzipsystem> {
68
public:
69 9 dgisselq
        unsigned long   m_mem_size;
70 2 dgisselq
        MEMSIM          m_mem;
71
        // QSPIFLASHSIM m_flash;
72
        FILE            *dbg_fp;
73
        bool            dbg_flag, bomb;
74 34 dgisselq
        int             m_cursor;
75 2 dgisselq
 
76 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
77 36 dgisselq
                if (true) {
78
                        dbg_fp = fopen("dbg.txt", "w");
79
                        dbg_flag = true;
80
                } else {
81
                        dbg_fp = NULL;
82
                        dbg_flag = false;
83
                }
84 2 dgisselq
                bomb = false;
85 34 dgisselq
                m_cursor = 0;
86 2 dgisselq
        }
87
 
88
        void    reset(void) {
89
                // m_flash.debug(false);
90
                TESTB<Vzipsystem>::reset();
91
        }
92
 
93
        bool    on_tick(void) {
94
                tick();
95
                return true;
96
        }
97
 
98 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
99
                if (c)
100
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
101
                else
102
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
103 2 dgisselq
        }
104
 
105 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
106 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
107 34 dgisselq
                if (c)
108
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
109
                else
110
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
111 2 dgisselq
        }
112
 
113 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
114 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
115 34 dgisselq
                if (c)
116
                        mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
117
                else
118
                        mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
119 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
120
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
121
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
122 34 dgisselq
                        ?'a':((c)?'<':' '));
123 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
124
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
125
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
126 34 dgisselq
                        ?'b':((c)?'<':' '));
127 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
128
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
129 34 dgisselq
                        ?'W':((c)?'<':' '));
130 2 dgisselq
        }
131
 
132
        void    showins(int y, const char *lbl, const int ce, const int valid,
133
                        const int gie, const int stall, const unsigned int pc) {
134
                char    line[80];
135
 
136
                if (ce)
137
                        mvprintw(y, 0, "Ck ");
138
                else
139
                        mvprintw(y, 0, "   ");
140
                if (stall)
141
                        printw("Stl ");
142
                else
143
                        printw("    ");
144
                printw("%s: 0x%08x", lbl, pc);
145
 
146
                if (valid) {
147
                        if (gie) attroff(A_BOLD);
148
                        else    attron(A_BOLD);
149
                        zipi_to_string(m_mem[pc], line);
150 27 dgisselq
                        printw("  %-24s", &line[1]);
151 2 dgisselq
                } else {
152
                        attroff(A_BOLD);
153
                        printw("  (0x%08x)%28s", m_mem[pc],"");
154
                }
155
                attroff(A_BOLD);
156
        }
157
 
158
        void    dbgins(const char *lbl, const int ce, const int valid,
159
                        const int gie, const int stall, const unsigned int pc) {
160
                char    line[80];
161
 
162
                if (!dbg_fp)
163
                        return;
164
 
165
                if (ce)
166
                        fprintf(dbg_fp, "%s Ck ", lbl);
167
                else
168
                        fprintf(dbg_fp, "%s    ", lbl);
169
                if (stall)
170
                        fprintf(dbg_fp, "Stl ");
171
                else
172
                        fprintf(dbg_fp, "    ");
173
                fprintf(dbg_fp, "0x%08x:  ", pc);
174
 
175
                if (valid) {
176
                        zipi_to_string(m_mem[pc], line);
177
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
178
                } else {
179
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
180
                }
181
        }
182
 
183
        void    show_state(void) {
184
                int     ln= 0;
185
 
186
                mvprintw(ln,0, "Peripherals-SS"); ln++;
187 36 dgisselq
                printw(" %s",
188
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
189
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
190
                        );
191 2 dgisselq
                /*
192 36 dgisselq
                printw(" %s%s%s",
193
                        (m_core->v__DOT__thecpu__DOT__ill_err)?"IL":"  ",
194
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
195
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
196
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
197
                        );
198
                */
199
 
200
                /*
201 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
202
                        mvprintw(ln, 17, "%s%s",
203
                                ((m_core->v__DOT__sys_cyc)
204
                                &&(m_core->v__DOT__sys_we)
205
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
206
                                (m_core->v__DOT__trap_int)?"I":" ");
207
                */
208 34 dgisselq
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
209
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
210 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
211 34 dgisselq
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
212 2 dgisselq
 
213
                ln++;
214 34 dgisselq
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
215
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
216
                showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
217
                showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
218 2 dgisselq
 
219
                ln++;
220 34 dgisselq
                showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
221
                showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
222
                showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
223
                showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
224 2 dgisselq
 
225
                ln++;
226
                mvprintw(ln, 40, "%s %s",
227
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
228
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
229
                mvprintw(ln, 40, "%s %s %s 0x%02x",
230
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
231
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
232
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
233
                        (m_core->v__DOT__cmd_addr)&0x3f);
234
                if (m_core->v__DOT__thecpu__DOT__gie)
235
                        attroff(A_BOLD);
236
                else
237
                        attron(A_BOLD);
238
                mvprintw(ln, 0, "Supervisor Registers");
239
                ln++;
240
 
241 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
242
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
243
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
244
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
245 2 dgisselq
 
246 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
247
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
248
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
249
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
250 2 dgisselq
 
251 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
252
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
253
                showreg(ln,40, "sR10", 10, (m_cursor==22));
254
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
255 2 dgisselq
 
256 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
257
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
258 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
259
                        (m_cursor==26)?">":" ",
260
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
261
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
262
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
263
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
264
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
265 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
266
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
267
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
268
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
269 34 dgisselq
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
270 2 dgisselq
                ln++;
271
 
272
                if (m_core->v__DOT__thecpu__DOT__gie)
273
                        attron(A_BOLD);
274
                else
275
                        attroff(A_BOLD);
276
                mvprintw(ln, 0, "User Registers"); ln++;
277 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
278
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
279
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
280
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
281 2 dgisselq
 
282 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
283
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
284
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
285
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
286 2 dgisselq
 
287 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
288
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
289
                showreg(ln,40, "uR10", 26, (m_cursor==38));
290
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
291 2 dgisselq
 
292 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
293
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
294
                mvprintw(ln,40, "uCC :%s%s%s%s%s%s%s%s",
295 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
296
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
297
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
298
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
299 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
300
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
301
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
302
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
303 34 dgisselq
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
304 2 dgisselq
 
305
                attroff(A_BOLD);
306
                ln+=1;
307
 
308 36 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
309 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
310
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
311
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
312
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
313 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
314 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
315
                        m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
316
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
317
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
318 2 dgisselq
                ln++;
319
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
320
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
321
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
322
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
323
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
324
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
325
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
326 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
327 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
328
 
329
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
330 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
331
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
332
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
333
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
334 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
335
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
336
                        (m_core->v__DOT__thecpu__DOT__mem_data),
337
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
338 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
339 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
340
 
341 36 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
342
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
343 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
344
                        (m_core->o_wb_stb)?"STB":"   ",
345
                        (m_core->o_wb_we )?"WE":"  ",
346
                        (m_core->o_wb_addr),
347
                        (m_core->o_wb_data),
348
                        (m_core->i_wb_ack)?"ACK":"   ",
349
                        (m_core->i_wb_stall)?"STL":"   ",
350
                        (m_core->i_wb_data)); ln+=2;
351
 
352
                showins(ln, "I ",
353
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
354
                        m_core->v__DOT__thecpu__DOT__pf_valid,
355
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
356
                        m_core->v__DOT__thecpu__DOT__gie,
357
                        0,
358 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
359
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
360 2 dgisselq
 
361
                showins(ln, "Dc",
362
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
363
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
364
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
365
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
366
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
367
 
368
                showins(ln, "Op",
369
                        m_core->v__DOT__thecpu__DOT__op_ce,
370
                        m_core->v__DOT__thecpu__DOT__opvalid,
371
                        m_core->v__DOT__thecpu__DOT__op_gie,
372
                        m_core->v__DOT__thecpu__DOT__op_stall,
373
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
374
 
375
                showins(ln, "Al",
376
                        m_core->v__DOT__thecpu__DOT__alu_ce,
377
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
378
                        m_core->v__DOT__thecpu__DOT__alu_gie,
379
                        m_core->v__DOT__thecpu__DOT__alu_stall,
380
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
381
 
382 27 dgisselq
                mvprintw(ln-5, 48,"%s %s",
383
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
384
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
385 2 dgisselq
                mvprintw(ln-4, 48,
386
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
387
                printw("(%s:%02x,%x)",
388
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
389
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
390
                        (m_core->v__DOT__thecpu__DOT__op_gie)
391
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
392
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
393
 
394
                printw("(%s%s%s:%02x)",
395
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
396
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
397
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
398
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
399
                /*
400
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
401
                        m_core->v__DOT__thecpu__DOT__dcdI);
402
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
403
                        m_core->v__DOT__thecpu__DOT__opB);
404
                */
405 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
406 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
407 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
408
                        m_core->v__DOT__thecpu__DOT__r_opB);
409
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
410
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
411
                else
412
                        printw("%8s","");
413 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
414 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
415 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
416
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
417
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
418
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
419
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
420
        }
421
 
422
        unsigned int    cmd_read(unsigned int a) {
423
                if (dbg_fp) {
424
                        dbg_flag= true;
425
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
426
                }
427
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
428
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
429
                        ;
430
                unsigned int v = wb_read(CMD_DATA);
431
 
432
                if (dbg_flag)
433
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
434
                                v);
435
                dbg_flag = false;
436
                return v;
437
        }
438
 
439 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
440
                if ((a&0x0f)==0x0f)
441
                        dbg_flag = true;
442
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
443
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
444
                        ;
445
                if (dbg_flag)
446
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
447
                wb_write(CMD_DATA, v);
448
        }
449
 
450 27 dgisselq
        bool    halted(void) {
451
                return (m_core->v__DOT__cmd_halt != 0);
452
        }
453
 
454 2 dgisselq
        void    read_state(void) {
455
                int     ln= 0;
456 34 dgisselq
                bool    gie;
457 2 dgisselq
 
458 34 dgisselq
                if (m_cursor < 0)
459
                        m_cursor = 0;
460
                else if (m_cursor >= 44)
461
                        m_cursor = 43;
462
 
463
                mvprintw(ln,0, "Peripherals-RS");
464
                mvprintw(ln,40,"%-40s", "CPU State: ");
465
                {
466
                        unsigned int v = wb_read(CMD_REG);
467
                        mvprintw(ln,51, "");
468
                        if (v & 0x010000)
469
                                printw("EXT-INT ");
470
                        if ((v & 0x003000) == 0x03000)
471
                                printw("Halted ");
472
                        else if (v & 0x001000)
473
                                printw("Sleeping ");
474
                        else if (v & 0x002000)
475
                                printw("Supervisor Mod ");
476
                        if (v & 0x008000)
477
                                printw("Break-Enabled ");
478
                        if (v & 0x000080)
479
                                printw("PIC Enabled ");
480
                } ln++;
481
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
482
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
483 36 dgisselq
                // showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
484 34 dgisselq
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
485 2 dgisselq
                ln++;
486 34 dgisselq
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
487
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
488
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
489
                showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
490 2 dgisselq
 
491
                ln++;
492 34 dgisselq
                showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
493
                showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
494
                showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
495
                showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
496 2 dgisselq
 
497
                ln++;
498
                ln++;
499
                unsigned int cc = cmd_read(14);
500
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
501
                        m_core->v__DOT__thecpu__DOT__gie);
502 34 dgisselq
                gie = (cc & 0x020);
503
                if (gie)
504 2 dgisselq
                        attroff(A_BOLD);
505
                else
506
                        attron(A_BOLD);
507
                mvprintw(ln, 0, "Supervisor Registers");
508
                ln++;
509
 
510 34 dgisselq
                dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
511
                dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
512
                dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
513
                dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
514 2 dgisselq
 
515 34 dgisselq
                dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
516
                dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
517
                dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
518
                dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
519 2 dgisselq
 
520 34 dgisselq
                dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
521
                dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
522
                dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
523
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
524 2 dgisselq
 
525 34 dgisselq
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
526
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
527 2 dgisselq
 
528 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
529 34 dgisselq
                        (m_cursor==26)?">":" ",
530 36 dgisselq
                        (cc & 0x200)?"TP":"  ",
531
                        (cc & 0x080)?"BK":"  ",
532 34 dgisselq
                        (cc & 0x040)?"ST":"  ",
533
                        (cc & 0x020)?"IE":"  ",
534
                        (cc & 0x010)?"SL":"  ",
535 2 dgisselq
                        (cc&8)?"V":" ",
536
                        (cc&4)?"N":" ",
537
                        (cc&2)?"C":" ",
538
                        (cc&1)?"Z":" ");
539 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
540 2 dgisselq
                ln++;
541
 
542 34 dgisselq
                if (gie)
543 2 dgisselq
                        attron(A_BOLD);
544
                else
545
                        attroff(A_BOLD);
546
                mvprintw(ln, 0, "User Registers"); ln++;
547 34 dgisselq
                dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
548
                dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
549
                dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
550
                dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
551 2 dgisselq
 
552 34 dgisselq
                dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
553
                dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
554
                dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
555
                dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
556 2 dgisselq
 
557 34 dgisselq
                dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
558
                dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
559
                dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
560
                dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
561 2 dgisselq
 
562 34 dgisselq
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
563
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
564 2 dgisselq
                cc = cmd_read(30);
565 34 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
566 36 dgisselq
                        (m_cursor == 42)?'>':' ',
567 34 dgisselq
                        (cc&0x100)?"TP":"  ",
568
                        (cc&0x040)?"ST":"  ",
569
                        (cc&0x020)?"IE":"  ",
570
                        (cc&0x010)?"SL":"  ",
571 2 dgisselq
                        (cc&8)?"V":" ",
572
                        (cc&4)?"N":" ",
573
                        (cc&2)?"C":" ",
574
                        (cc&1)?"Z":" ");
575 34 dgisselq
                dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
576 2 dgisselq
 
577
                attroff(A_BOLD);
578
                ln+=2;
579
 
580
                ln+=3;
581
 
582
                showins(ln, "I ",
583
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
584
                        m_core->v__DOT__thecpu__DOT__pf_valid,
585
                        m_core->v__DOT__thecpu__DOT__gie,
586
                        0,
587
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
588
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
589
 
590
                showins(ln, "Dc",
591
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
592
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
593
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
594
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
595
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
596
 
597
                showins(ln, "Op",
598
                        m_core->v__DOT__thecpu__DOT__op_ce,
599
                        m_core->v__DOT__thecpu__DOT__opvalid,
600
                        m_core->v__DOT__thecpu__DOT__op_gie,
601
                        m_core->v__DOT__thecpu__DOT__op_stall,
602
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
603
 
604
                showins(ln, "Al",
605
                        m_core->v__DOT__thecpu__DOT__alu_ce,
606
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
607
                        m_core->v__DOT__thecpu__DOT__alu_gie,
608
                        m_core->v__DOT__thecpu__DOT__alu_stall,
609
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
610
        }
611
        void    tick(void) {
612
                int gie = m_core->v__DOT__thecpu__DOT__gie;
613
                /*
614
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
615
                                                m_core->o_qspi_sck,
616
                                                m_core->o_qspi_dat);
617
                */
618
 
619 11 dgisselq
                int stb = m_core->o_wb_stb;
620
                if ((m_core->o_wb_addr & (-1<<20))!=1)
621
                        stb = 0;
622
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
623
                        m_core->i_wb_ack = 1;
624 2 dgisselq
 
625
                if ((dbg_flag)&&(dbg_fp)) {
626 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
627 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
628
                                (m_core->i_dbg_stb)?"STB":
629
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
630
                                ((m_core->i_dbg_we)?"WE":"  "),
631
                                (m_core->i_dbg_addr),0,
632
                                m_core->i_dbg_data,
633
                                (m_core->o_dbg_ack)?"ACK":"   ",
634
                                (m_core->o_dbg_stall)?"STALL":"     ",
635
                                (m_core->o_dbg_data),
636
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
637
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
638
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
639
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
640
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
641 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
642
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
643 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
644
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
645
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
646
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
647
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
648
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
649
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
650
                                (m_core->v__DOT__sys_we)?"WE":"  ",
651
                                (m_core->v__DOT__sys_addr),
652
                                (m_core->v__DOT__dbg_addr),
653
                                (m_core->v__DOT__sys_data),
654
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
655
                                (m_core->v__DOT__wb_data));
656
                }
657
 
658
                if (dbg_fp)
659
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
660
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
661
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
662
                                m_core->v__DOT__thecpu__DOT__op_ce,
663
                                m_core->v__DOT__thecpu__DOT__op_pc,
664
                                m_core->v__DOT__thecpu__DOT__dcdA,
665
                                m_core->v__DOT__thecpu__DOT__opR,
666
                                m_core->v__DOT__cmd_halt,
667
                                m_core->v__DOT__cpu_halt,
668
                                m_core->v__DOT__thecpu__DOT__alu_ce,
669
                                m_core->v__DOT__thecpu__DOT__alu_valid,
670
                                m_core->v__DOT__thecpu__DOT__alu_wr,
671
                                m_core->v__DOT__thecpu__DOT__alu_reg,
672
                                m_core->v__DOT__thecpu__DOT__ipc,
673
                                m_core->v__DOT__thecpu__DOT__upc);
674
 
675
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
676
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
677
                                m_core->v__DOT__pic_interrupt,
678
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
679
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
680
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
681
                                m_core->v__DOT__cmd_addr,
682
                                m_core->v__DOT__dbg_idata,
683
                                m_core->v__DOT__thecpu__DOT__master_ce,
684
                                m_core->v__DOT__thecpu__DOT__alu_wr,
685
                                m_core->v__DOT__thecpu__DOT__alu_valid,
686
                                m_core->v__DOT__thecpu__DOT__mem_valid);
687
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
688
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
689
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
690
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
691
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
692
                                m_core->v__DOT__cmd_addr,
693
                                m_core->v__DOT__dbg_idata,
694
                                m_core->v__DOT__thecpu__DOT__master_ce,
695
                                m_core->v__DOT__thecpu__DOT__alu_wr,
696
                                m_core->v__DOT__thecpu__DOT__alu_valid,
697
                                m_core->v__DOT__thecpu__DOT__mem_valid,
698
                                m_core->v__DOT__thecpu__DOT__w_iflags,
699
                                m_core->v__DOT__thecpu__DOT__w_uflags);
700 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
701
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
702 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
703
                                m_core->v__DOT__thecpu__DOT__op_break);
704 36 dgisselq
                } else if ((dbg_fp)&&
705
                                ((m_core->v__DOT__thecpu__DOT__op_break)
706
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
707
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
708
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
709
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
710
                                m_core->v__DOT__thecpu__DOT__break_en,
711
                                m_core->v__DOT__thecpu__DOT__dcd_break,
712
                                m_core->v__DOT__thecpu__DOT__op_break);
713 2 dgisselq
                }
714
 
715 34 dgisselq
                if (dbg_fp) {
716
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
717
                                fprintf(dbg_fp, "\tClear Pipeline\n");
718
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
719
                                fprintf(dbg_fp, "\tNew PC\n");
720
                }
721
 
722 36 dgisselq
                if (dbg_fp)
723
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
724
                if (false) {
725
                        m_core->i_clk = 1;
726
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
727
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
728
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
729
                        eval();
730
                        m_core->i_clk = 0;
731
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
732
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
733
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
734
                        eval();
735
                        m_tickcount++;
736
                } else {
737
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
738
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
739
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
740
                        TESTB<Vzipsystem>::tick();
741
                }
742 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
743
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
744
                                (gie)?"User":"Supervisor",
745
                                (gie)?"Supervisor":"User",
746
                                m_core->v__DOT__thecpu__DOT__ipc,
747
                                m_core->v__DOT__thecpu__DOT__upc,
748
                                m_core->v__DOT__thecpu__DOT__pf_pc);
749
                } if (dbg_fp) {
750
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
751
                                m_core->v__DOT__thecpu__DOT__opvalid,
752
                                m_core->v__DOT__thecpu__DOT__op_gie,
753
                                m_core->v__DOT__thecpu__DOT__op_stall,
754
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
755
                        dbgins("Al - ",
756
                                m_core->v__DOT__thecpu__DOT__alu_ce,
757
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
758
                                m_core->v__DOT__thecpu__DOT__alu_gie,
759
                                m_core->v__DOT__thecpu__DOT__alu_stall,
760
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
761
 
762
                }
763
        }
764
 
765
        bool    test_success(void) {
766
                return ((!m_core->v__DOT__thecpu__DOT__gie)
767
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
768
        }
769
 
770
        bool    test_failure(void) {
771
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
772
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
773 36 dgisselq
                                == 0x2f0f7fff)
774
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
775 2 dgisselq
        }
776
 
777
        void    wb_write(unsigned a, unsigned int v) {
778 36 dgisselq
                int     errcount = 0;
779 2 dgisselq
                mvprintw(0,35, "%40s", "");
780
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
781
                m_core->i_dbg_cyc = 1;
782
                m_core->i_dbg_stb = 1;
783
                m_core->i_dbg_we  = 1;
784
                m_core->i_dbg_addr = a & 1;
785
                m_core->i_dbg_data = v;
786
 
787
                tick();
788 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
789 2 dgisselq
                        tick();
790
 
791
                m_core->i_dbg_stb = 0;
792 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
793 2 dgisselq
                        tick();
794
 
795
                // Release the bus
796
                m_core->i_dbg_cyc = 0;
797
                m_core->i_dbg_stb = 0;
798
                tick();
799
                mvprintw(0,35, "%40s", "");
800
                mvprintw(0,40, "wb_write -- complete");
801 36 dgisselq
 
802
 
803
                if (errcount >= 100)
804
                        bomb = true;
805 2 dgisselq
        }
806
 
807
        unsigned long   wb_read(unsigned a) {
808
                unsigned int    v;
809 36 dgisselq
                int     errcount = 0;
810 2 dgisselq
                mvprintw(0,35, "%40s", "");
811
                mvprintw(0,40, "wb_read(0x%08x)", a);
812
                m_core->i_dbg_cyc = 1;
813
                m_core->i_dbg_stb = 1;
814
                m_core->i_dbg_we  = 0;
815
                m_core->i_dbg_addr = a & 1;
816
 
817
                tick();
818 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
819 2 dgisselq
                        tick();
820
 
821
                m_core->i_dbg_stb = 0;
822 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
823 2 dgisselq
                        tick();
824
                v = m_core->o_dbg_data;
825
 
826
                // Release the bus
827
                m_core->i_dbg_cyc = 0;
828
                m_core->i_dbg_stb = 0;
829
                tick();
830
 
831
                mvprintw(0,35, "%40s", "");
832
                mvprintw(0,40, "wb_read = 0x%08x", v);
833
 
834 36 dgisselq
                if (errcount >= 100)
835
                        bomb = true;
836 2 dgisselq
                return v;
837
        }
838
 
839 34 dgisselq
        void    cursor_up(void) {
840
                if (m_cursor > 3)
841
                        m_cursor -= 4;
842
        } void  cursor_down(void) {
843
                if (m_cursor < 40)
844
                        m_cursor += 4;
845
        } void  cursor_left(void) {
846
                if (m_cursor > 0)
847
                        m_cursor--;
848
                else    m_cursor = 43;
849
        } void  cursor_right(void) {
850
                if (m_cursor < 43)
851
                        m_cursor++;
852
                else    m_cursor = 0;
853
        }
854
 
855
        int     cursor(void) { return m_cursor; }
856 2 dgisselq
};
857
 
858 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
859
        int     wy, wx, ra;
860
        int     c = tb->cursor();
861
 
862
        wx = (c & 0x03) * 20 + 9;
863
        wy = (c>>2);
864
        if (wy >= 3+4)
865
                wy++;
866
        if (wy > 3)
867
                wy += 2;
868
        wy++;
869
 
870
        if (c >= 12)
871
                ra = c - 12;
872
        else
873
                ra = c + 32;
874
 
875
        bool    done = false;
876
        char    str[16];
877
        int     pos = 0; str[pos] = '\0';
878
        while(!done) {
879
                int     chv = getch();
880
                switch(chv) {
881
                case KEY_ESCAPE:
882
                        pos = 0; str[pos] = '\0'; done = true;
883
                        break;
884
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
885
                        done = true;
886
                        break;
887
                case KEY_LEFT: case KEY_BACKSPACE:
888
                        if (pos > 0) pos--;
889
                        break;
890 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
891 34 dgisselq
                case KEY_CLEAR:
892
                        pos = 0;
893
                        break;
894
                case '0': case ' ': str[pos++] = '0'; break;
895
                case '1': str[pos++] = '1'; break;
896
                case '2': str[pos++] = '2'; break;
897
                case '3': str[pos++] = '3'; break;
898
                case '4': str[pos++] = '4'; break;
899
                case '5': str[pos++] = '5'; break;
900
                case '6': str[pos++] = '6'; break;
901
                case '7': str[pos++] = '7'; break;
902
                case '8': str[pos++] = '8'; break;
903
                case '9': str[pos++] = '9'; break;
904
                case 'A': case 'a': str[pos++] = 'A'; break;
905
                case 'B': case 'b': str[pos++] = 'B'; break;
906
                case 'C': case 'c': str[pos++] = 'C'; break;
907
                case 'D': case 'd': str[pos++] = 'D'; break;
908
                case 'E': case 'e': str[pos++] = 'E'; break;
909
                case 'F': case 'f': str[pos++] = 'F'; break;
910
                }
911
 
912
                if (pos > 8)
913
                        pos = 8;
914
                str[pos] = '\0';
915
 
916
                attron(A_NORMAL | A_UNDERLINE);
917
                mvprintw(wy, wx, "%-8s", str);
918
                if (pos > 0) {
919
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
920
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
921
                }
922
                attrset(A_NORMAL);
923
        }
924
 
925
        if (pos > 0) {
926
                int     v;
927
                v = strtoul(str, NULL, 16);
928
                if (!tb->halted()) {
929
                        switch(ra) {
930
                        case 15:
931
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
932
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
933
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
934
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
935
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
936
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
937
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
938
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
939
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
940
                                }
941
                                break;
942
                        case 31:
943
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
944
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
945
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
946
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
947
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
948
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
949
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
950
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
951
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
952
                                }
953
                                break;
954
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
955
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
956 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
957 34 dgisselq
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
958
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
959
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
960
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
961
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
962
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
963
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
964
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
965
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
966
                        default:
967
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
968
                                break;
969
                        }
970
                } else
971
                        tb->cmd_write(ra, v);
972
        }
973
}
974
 
975 27 dgisselq
void    usage(void) {
976
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
977
        printf("\n");
978
        printf("\tWhere testfile.out is an output file from the assembler.\n");
979
        printf("\t-a\tSets the testbench to run automatically without any\n");
980
        printf("\t\tuser interaction.\n");
981
        printf("\n");
982
        printf("\tUser Commands:\n");
983
        printf("\t\tWhen the test bench is run interactively, the following\n");
984
        printf("\t\tkey strokes are recognized:\n");
985
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
986
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
987
        printf("\t\t\tuser intervention.\n");
988
        printf("\t\t\'q\'\tQuit the simulation.\n");
989
        printf("\t\t\'r\'\tReset the processor.\n");
990
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
991
        printf("\t\t\tThis may consume more than one tick.\n");
992
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
993
}
994 2 dgisselq
 
995
int     main(int argc, char **argv) {
996
        Verilated::commandArgs(argc, argv);
997
        ZIPPY_TB        *tb = new ZIPPY_TB();
998 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
999 2 dgisselq
 
1000
        // mem[0x00000] = 0xbe000010; // Halt instruction
1001
        unsigned int mptr = 0;
1002
 
1003 9 dgisselq
        if (argc <= 1) {
1004 27 dgisselq
                usage();
1005
                exit(-1);
1006 9 dgisselq
        } else {
1007
                for(int argn=1; argn<argc; argn++) {
1008 27 dgisselq
                        if (argv[argn][0] == '-') {
1009
                                switch(argv[argn][1]) {
1010
                                case 'a':
1011
                                        autorun = true;
1012
                                        break;
1013
                                case 'e':
1014
                                        exit_on_done = true;
1015
                                        break;
1016
                                case 'h':
1017
                                        usage();
1018
                                        exit(0);
1019
                                        break;
1020 36 dgisselq
                                case 's':
1021
                                        autostep = true;
1022
                                        break;
1023 27 dgisselq
                                default:
1024
                                        usage();
1025
                                        exit(-1);
1026
                                        break;
1027
                                }
1028
                        } else if (access(argv[argn], R_OK)==0) {
1029 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1030
                                if (fp == NULL) {
1031
                                        printf("Cannot open %s\n", argv[argn]);
1032
                                        perror("O/S Err: ");
1033
                                        exit(-1);
1034
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1035
                                fclose(fp);
1036
                        }
1037
                }
1038
        }
1039
 
1040 27 dgisselq
        if (autorun) {
1041
                bool    done = false;
1042 2 dgisselq
 
1043 27 dgisselq
                printf("Running in non-interactive mode\n");
1044
                tb->reset();
1045
                for(int i=0; i<2; i++)
1046
                        tb->tick();
1047
                tb->m_core->v__DOT__cmd_halt = 0;
1048
                while(!done) {
1049
                        tb->tick();
1050
 
1051
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1052
                                // tb->m_core->v__DOT__cmd_halt = 0;
1053
                                // tb->m_core->v__DOT__cmd_step = 0;
1054
 
1055 34 dgisselq
                        /*
1056 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1057
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1058
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1059
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1060 34 dgisselq
                        */
1061 27 dgisselq
 
1062
                        done = (tb->test_success())||(tb->test_failure());
1063
                }
1064 36 dgisselq
        } else if (autostep) {
1065
                bool    done = false;
1066
 
1067
                printf("Running in non-interactive mode, via step commands\n");
1068
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1069
                while(!done) {
1070
                        tb->wb_write(CMD_REG, CMD_STEP);
1071
                        done = (tb->test_success())||(tb->test_failure());
1072
                }
1073 27 dgisselq
        } else { // Interactive
1074
                initscr();
1075
                raw();
1076
                noecho();
1077
                keypad(stdscr, true);
1078
 
1079
                tb->reset();
1080
                for(int i=0; i<2; i++)
1081
                        tb->tick();
1082
                tb->m_core->v__DOT__cmd_halt = 0;
1083
 
1084
                int     chv = 'q';
1085
 
1086 2 dgisselq
                bool    done = false, halted = true, manual = true;
1087
 
1088
                halfdelay(1);
1089 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1090 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1091
                        // tb->show_state();
1092
 
1093
                while(!done) {
1094
                        chv = getch();
1095
                        switch(chv) {
1096
                        case 'h': case 'H':
1097
                                tb->wb_write(CMD_REG, CMD_HALT);
1098
                                if (!halted)
1099
                                        erase();
1100
                                halted = true;
1101
                                break;
1102
                        case 'g': case 'G':
1103
                                tb->wb_write(CMD_REG, 0);
1104
                                if (halted)
1105
                                        erase();
1106
                                halted = false;
1107
                                manual = false;
1108
                                break;
1109
                        case 'q': case 'Q':
1110
                                done = true;
1111
                                break;
1112
                        case 'r': case 'R':
1113 36 dgisselq
                                if (manual)
1114
                                        tb->reset();
1115
                                else
1116
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1117 2 dgisselq
                                halted = true;
1118
                                erase();
1119
                                break;
1120
                        case 's': case 'S':
1121 34 dgisselq
                                if (!halted)
1122 27 dgisselq
                                        erase();
1123 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
1124
                                manual = false;
1125 34 dgisselq
                                halted = true;
1126 2 dgisselq
                                break;
1127
                        case 't': case 'T':
1128 34 dgisselq
                                if ((!manual)||(halted))
1129 27 dgisselq
                                        erase();
1130 2 dgisselq
                                manual = true;
1131 34 dgisselq
                                halted = false;
1132 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1133
                //              tb->m_core->v__DOT__cmd_halt = 0;
1134
                //              tb->m_core->v__DOT__cmd_step = 0;
1135 2 dgisselq
                                tb->tick();
1136
                                break;
1137 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1138
                                get_value(tb);
1139
                                break;
1140
                        case    KEY_UP:         tb->cursor_up();        break;
1141
                        case    KEY_DOWN:       tb->cursor_down();      break;
1142
                        case    KEY_LEFT:       tb->cursor_left();      break;
1143
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1144 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1145 34 dgisselq
                        case ERR: case KEY_CLEAR:
1146 2 dgisselq
                        default:
1147
                                if (!manual)
1148
                                        tb->tick();
1149
                        }
1150
 
1151
                        if (manual) {
1152
                                tb->show_state();
1153
                        } else if (halted) {
1154
                                if (tb->dbg_fp)
1155
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1156
                                tb->read_state();
1157
                        } else
1158
                                tb->show_state();
1159
 
1160
                        if (tb->m_core->i_rst)
1161
                                done =true;
1162
                        if (tb->bomb)
1163
                                done = true;
1164 27 dgisselq
 
1165
                        if (exit_on_done) {
1166
                                if (tb->test_success())
1167
                                        done = true;
1168
                                if (tb->test_failure())
1169
                                        done = true;
1170
                        }
1171 2 dgisselq
                }
1172 27 dgisselq
                endwin();
1173
        }
1174
#ifdef  MANUAL_STEPPING_MODE
1175
         else { // Manual stepping mode
1176 2 dgisselq
                tb->show_state();
1177
 
1178
                while('q' != tolower(chv = getch())) {
1179
                        tb->tick();
1180
                        tb->show_state();
1181
 
1182
                        if (tb->test_success())
1183
                                break;
1184
                        else if (tb->test_failure())
1185
                                break;
1186
                }
1187
        }
1188 27 dgisselq
#endif
1189 2 dgisselq
 
1190 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1191
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1192
        if (tb->m_core->v__DOT__mtc_data != 0)
1193
                printf("Instructions / Clock: %.2f\n",
1194
                        (double)tb->m_core->v__DOT__mic_data
1195
                        / (double)tb->m_core->v__DOT__mtc_data);
1196 36 dgisselq
 
1197
        int     rcode = 0;
1198
        if (tb->bomb) {
1199
                printf("TEST BOMBED\n");
1200
                rcode = -1;
1201
        } else if (tb->test_success()) {
1202 2 dgisselq
                printf("SUCCESS!\n");
1203 36 dgisselq
        } else if (tb->test_failure()) {
1204
                rcode = -2;
1205 2 dgisselq
                printf("TEST FAILED!\n");
1206 36 dgisselq
        } else
1207 27 dgisselq
                printf("User quit\n");
1208 36 dgisselq
        exit(rcode);
1209 2 dgisselq
}
1210
 

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