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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 43

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68
// No particular "parameters" need definition or redefinition here.
69
class   ZIPPY_TB : public TESTB<Vzipsystem> {
70
public:
71 9 dgisselq
        unsigned long   m_mem_size;
72 2 dgisselq
        MEMSIM          m_mem;
73
        // QSPIFLASHSIM m_flash;
74
        FILE            *dbg_fp;
75 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
76 34 dgisselq
        int             m_cursor;
77 2 dgisselq
 
78 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
79 43 dgisselq
                if (false) {
80 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
81
                        dbg_flag = true;
82
                } else {
83
                        dbg_fp = NULL;
84
                        dbg_flag = false;
85
                }
86 2 dgisselq
                bomb = false;
87 34 dgisselq
                m_cursor = 0;
88 43 dgisselq
                m_show_user_timers = false;
89 2 dgisselq
        }
90
 
91
        void    reset(void) {
92
                // m_flash.debug(false);
93
                TESTB<Vzipsystem>::reset();
94
        }
95
 
96
        bool    on_tick(void) {
97
                tick();
98
                return true;
99
        }
100
 
101 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
102
                if (c)
103
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
104
                else
105
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
106 2 dgisselq
        }
107
 
108 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
109 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
110 34 dgisselq
                if (c)
111
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
112
                else
113
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
114 2 dgisselq
        }
115
 
116 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
117 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
118 34 dgisselq
                if (c)
119
                        mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
120
                else
121
                        mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
122 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
123
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
124
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
125 34 dgisselq
                        ?'a':((c)?'<':' '));
126 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
127
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
128
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
129 34 dgisselq
                        ?'b':((c)?'<':' '));
130 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
131
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
132 34 dgisselq
                        ?'W':((c)?'<':' '));
133 2 dgisselq
        }
134
 
135
        void    showins(int y, const char *lbl, const int ce, const int valid,
136
                        const int gie, const int stall, const unsigned int pc) {
137
                char    line[80];
138
 
139
                if (ce)
140
                        mvprintw(y, 0, "Ck ");
141
                else
142
                        mvprintw(y, 0, "   ");
143
                if (stall)
144
                        printw("Stl ");
145
                else
146
                        printw("    ");
147
                printw("%s: 0x%08x", lbl, pc);
148
 
149
                if (valid) {
150
                        if (gie) attroff(A_BOLD);
151
                        else    attron(A_BOLD);
152
                        zipi_to_string(m_mem[pc], line);
153 27 dgisselq
                        printw("  %-24s", &line[1]);
154 2 dgisselq
                } else {
155
                        attroff(A_BOLD);
156
                        printw("  (0x%08x)%28s", m_mem[pc],"");
157
                }
158
                attroff(A_BOLD);
159
        }
160
 
161
        void    dbgins(const char *lbl, const int ce, const int valid,
162
                        const int gie, const int stall, const unsigned int pc) {
163
                char    line[80];
164
 
165
                if (!dbg_fp)
166
                        return;
167
 
168
                if (ce)
169
                        fprintf(dbg_fp, "%s Ck ", lbl);
170
                else
171
                        fprintf(dbg_fp, "%s    ", lbl);
172
                if (stall)
173
                        fprintf(dbg_fp, "Stl ");
174
                else
175
                        fprintf(dbg_fp, "    ");
176
                fprintf(dbg_fp, "0x%08x:  ", pc);
177
 
178
                if (valid) {
179
                        zipi_to_string(m_mem[pc], line);
180
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
181
                } else {
182
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
183
                }
184
        }
185
 
186
        void    show_state(void) {
187
                int     ln= 0;
188
 
189
                mvprintw(ln,0, "Peripherals-SS"); ln++;
190 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
191 36 dgisselq
                printw(" %s",
192
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
193
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
194
                        );
195 39 dgisselq
#endif
196
 
197
#ifdef  OPT_EARLY_BRANCHING
198
                printw(" %s%s",
199 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
200 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
201
#endif
202 36 dgisselq
 
203
                /*
204 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
205
                        mvprintw(ln, 17, "%s%s",
206
                                ((m_core->v__DOT__sys_cyc)
207
                                &&(m_core->v__DOT__sys_we)
208
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
209
                                (m_core->v__DOT__trap_int)?"I":" ");
210
                */
211 34 dgisselq
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
212
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
213 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
214 34 dgisselq
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
215 2 dgisselq
 
216
                ln++;
217 34 dgisselq
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
218
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
219
                showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
220
                showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
221 2 dgisselq
 
222 43 dgisselq
 
223
                if (!m_show_user_timers) {
224
                        ln++;
225
                        showval(ln, 0, "MTSK", m_core->v__DOT__mtc_data, (m_cursor==8));
226
                        showval(ln,20, "MOST", m_core->v__DOT__moc_data, (m_cursor==9));
227
                        showval(ln,40, "MPST", m_core->v__DOT__mpc_data, (m_cursor==10));
228
                        showval(ln,60, "MICT", m_core->v__DOT__mic_data, (m_cursor==11));
229
                } else {
230
                        ln++;
231
                        showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
232
                        showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
233
                        showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
234
                        showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
235
                }
236 2 dgisselq
 
237
                ln++;
238
                mvprintw(ln, 40, "%s %s",
239
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
240
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
241
                mvprintw(ln, 40, "%s %s %s 0x%02x",
242
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
243
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
244
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
245
                        (m_core->v__DOT__cmd_addr)&0x3f);
246
                if (m_core->v__DOT__thecpu__DOT__gie)
247
                        attroff(A_BOLD);
248
                else
249
                        attron(A_BOLD);
250
                mvprintw(ln, 0, "Supervisor Registers");
251
                ln++;
252
 
253 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
254
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
255
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
256
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
257 2 dgisselq
 
258 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
259
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
260
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
261
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
262 2 dgisselq
 
263 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
264
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
265
                showreg(ln,40, "sR10", 10, (m_cursor==22));
266
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
267 2 dgisselq
 
268 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
269
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
270 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
271
                        (m_cursor==26)?">":" ",
272
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
273
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
274
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
275
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
276
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
277 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
278
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
279
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
280
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
281 34 dgisselq
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
282 2 dgisselq
                ln++;
283
 
284
                if (m_core->v__DOT__thecpu__DOT__gie)
285
                        attron(A_BOLD);
286
                else
287
                        attroff(A_BOLD);
288
                mvprintw(ln, 0, "User Registers"); ln++;
289 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
290
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
291
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
292
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
293 2 dgisselq
 
294 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
295
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
296
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
297
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
298 2 dgisselq
 
299 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
300
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
301
                showreg(ln,40, "uR10", 26, (m_cursor==38));
302
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
303 2 dgisselq
 
304 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
305
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
306 43 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
307
                        (m_cursor == 42)?'>':' ',
308 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
309
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
310
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
311
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
312 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
313
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
314
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
315
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
316 34 dgisselq
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
317 2 dgisselq
 
318
                attroff(A_BOLD);
319
                ln+=1;
320
 
321 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
322
        ln+=2;
323
#else
324 36 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
325 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
326
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
327
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
328
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
329 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
330 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
331
                        m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
332
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
333
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
334 2 dgisselq
                ln++;
335
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
336
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
337
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
338
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
339
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
340
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
341
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
342 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
343 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
344 39 dgisselq
#endif
345 2 dgisselq
 
346
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
347 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
348
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
349
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
350
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
351 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
352
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
353
                        (m_core->v__DOT__thecpu__DOT__mem_data),
354
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
355 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
356 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
357
// #define      OPT_PIPELINED_BUS_ACCESS
358
#ifdef  OPT_PIPELINED_BUS_ACCESS
359
                printw(" %x%x%c%c",
360
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
361
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
362
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
363
                        (mem_pipe_stalled())?'S':'-'); ln++;
364
#else
365
                ln++;
366
#endif
367 2 dgisselq
 
368 36 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
369
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
370 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
371
                        (m_core->o_wb_stb)?"STB":"   ",
372
                        (m_core->o_wb_we )?"WE":"  ",
373
                        (m_core->o_wb_addr),
374
                        (m_core->o_wb_data),
375
                        (m_core->i_wb_ack)?"ACK":"   ",
376
                        (m_core->i_wb_stall)?"STL":"   ",
377
                        (m_core->i_wb_data)); ln+=2;
378 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
379
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
380
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
381 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
382
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
383
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
384
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
385
                        (!m_core->v__DOT__thecpu__DOT__mem_stalled),    //1
386 2 dgisselq
 
387 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stalled),
388
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
389
                        (m_core->v__DOT__thecpu__DOT__master_ce),
390
                        (mem_pipe_stalled()),
391
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
392
                        (m_core->v__DOT__thecpu__DOT__mem_busy));
393
                printw(" op_pipe = %d%d%d%d%d(%d|%d)",
394
                        (m_core->v__DOT__thecpu__DOT__dcdvalid),
395
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
396
                        (m_core->v__DOT__thecpu__DOT__dcdM),
397
                        (!((m_core->v__DOT__thecpu__DOT__dcdOp
398
                                ^m_core->v__DOT__thecpu__DOT__opn)&1)),
399
                        (m_core->v__DOT__thecpu__DOT__dcdB
400
                                == m_core->v__DOT__thecpu__DOT__op_B),
401
                        (m_core->v__DOT__thecpu__DOT__r_dcdI
402
                                == m_core->v__DOT__thecpu__DOT__r_opI),
403
                        (m_core->v__DOT__thecpu__DOT__r_dcdI+1
404
                                == m_core->v__DOT__thecpu__DOT__r_opI));
405
                mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
406
                        (m_core->v__DOT__thecpu__DOT__r_dcdI),
407
                        (m_core->v__DOT__thecpu__DOT__r_opI));
408
#endif
409
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
410 43 dgisselq
                printw(" A:%c%c B:%c",
411
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
412
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
413
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-');
414 39 dgisselq
 
415
 
416 2 dgisselq
                showins(ln, "I ",
417
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
418
                        m_core->v__DOT__thecpu__DOT__pf_valid,
419
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
420
                        m_core->v__DOT__thecpu__DOT__gie,
421
                        0,
422 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
423
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
424 2 dgisselq
 
425
                showins(ln, "Dc",
426
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
427
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
428
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
429
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
430
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
431 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
432
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
433
                        mvprintw(ln-1,10,"I");
434
                else
435
#endif
436
                if (m_core->v__DOT__thecpu__DOT__dcdM)
437
                        mvprintw(ln-1,10,"M");
438 2 dgisselq
 
439
                showins(ln, "Op",
440
                        m_core->v__DOT__thecpu__DOT__op_ce,
441
                        m_core->v__DOT__thecpu__DOT__opvalid,
442
                        m_core->v__DOT__thecpu__DOT__op_gie,
443
                        m_core->v__DOT__thecpu__DOT__op_stall,
444 39 dgisselq
                        op_pc()); ln++;
445
#ifdef  OPT_ILLEGAL_INSTRUCTION
446
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
447
                        mvprintw(ln-1,10,"I");
448
                else
449
#endif
450
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
451
                        mvprintw(ln-1,10,"M");
452
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
453
                        mvprintw(ln-1,10,"A");
454 2 dgisselq
 
455
                showins(ln, "Al",
456
                        m_core->v__DOT__thecpu__DOT__alu_ce,
457
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
458
                        m_core->v__DOT__thecpu__DOT__alu_gie,
459
                        m_core->v__DOT__thecpu__DOT__alu_stall,
460 39 dgisselq
                        alu_pc()); ln++;
461
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
462
                        mvprintw(ln-1,10,"W");
463 2 dgisselq
 
464 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
465 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
466
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
467 2 dgisselq
                mvprintw(ln-4, 48,
468
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
469
                printw("(%s:%02x,%x)",
470
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
471
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
472
                        (m_core->v__DOT__thecpu__DOT__op_gie)
473
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
474
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
475
 
476
                printw("(%s%s%s:%02x)",
477
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
478
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
479
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
480
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
481
                /*
482
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
483
                        m_core->v__DOT__thecpu__DOT__dcdI);
484
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
485
                        m_core->v__DOT__thecpu__DOT__opB);
486
                */
487 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
488 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
489 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
490
                        m_core->v__DOT__thecpu__DOT__r_opB);
491
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
492
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
493
                else
494
                        printw("%8s","");
495 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
496 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
497 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
498
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
499
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
500 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
501 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
502
        }
503
 
504 43 dgisselq
        void    show_user_timers(bool v) {
505
                m_show_user_timers = v;
506
        }
507
 
508 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
509
                if (dbg_fp) {
510
                        dbg_flag= true;
511
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
512
                }
513
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
514
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
515
                        ;
516
                unsigned int v = wb_read(CMD_DATA);
517
 
518
                if (dbg_flag)
519
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
520
                                v);
521
                dbg_flag = false;
522
                return v;
523
        }
524
 
525 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
526
                if ((a&0x0f)==0x0f)
527
                        dbg_flag = true;
528
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
529
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
530
                        ;
531
                if (dbg_flag)
532
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
533
                wb_write(CMD_DATA, v);
534
        }
535
 
536 27 dgisselq
        bool    halted(void) {
537
                return (m_core->v__DOT__cmd_halt != 0);
538
        }
539
 
540 2 dgisselq
        void    read_state(void) {
541
                int     ln= 0;
542 34 dgisselq
                bool    gie;
543 2 dgisselq
 
544 34 dgisselq
                if (m_cursor < 0)
545
                        m_cursor = 0;
546
                else if (m_cursor >= 44)
547
                        m_cursor = 43;
548
 
549
                mvprintw(ln,0, "Peripherals-RS");
550
                mvprintw(ln,40,"%-40s", "CPU State: ");
551
                {
552
                        unsigned int v = wb_read(CMD_REG);
553
                        mvprintw(ln,51, "");
554
                        if (v & 0x010000)
555
                                printw("EXT-INT ");
556
                        if ((v & 0x003000) == 0x03000)
557
                                printw("Halted ");
558
                        else if (v & 0x001000)
559
                                printw("Sleeping ");
560
                        else if (v & 0x002000)
561
                                printw("Supervisor Mod ");
562
                        if (v & 0x008000)
563
                                printw("Break-Enabled ");
564
                        if (v & 0x000080)
565
                                printw("PIC Enabled ");
566
                } ln++;
567
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
568
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
569 36 dgisselq
                // showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
570 34 dgisselq
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
571 2 dgisselq
                ln++;
572 34 dgisselq
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
573
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
574
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
575
                showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
576 2 dgisselq
 
577
                ln++;
578 43 dgisselq
                if (!m_show_user_timers) {
579
                        showval(ln, 0, "UTSK", cmd_read(32+8), (m_cursor==8));
580
                        showval(ln,20, "UMST", cmd_read(32+9), (m_cursor==9));
581
                        showval(ln,40, "UPST", cmd_read(32+10), (m_cursor==10));
582
                        showval(ln,60, "UICT", cmd_read(32+11), (m_cursor==11));
583
                } else {
584
                        showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
585
                        showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
586
                        showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
587
                        showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
588
                }
589 2 dgisselq
 
590
                ln++;
591
                ln++;
592
                unsigned int cc = cmd_read(14);
593
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
594
                        m_core->v__DOT__thecpu__DOT__gie);
595 34 dgisselq
                gie = (cc & 0x020);
596
                if (gie)
597 2 dgisselq
                        attroff(A_BOLD);
598
                else
599
                        attron(A_BOLD);
600
                mvprintw(ln, 0, "Supervisor Registers");
601
                ln++;
602
 
603 34 dgisselq
                dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
604
                dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
605
                dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
606
                dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
607 2 dgisselq
 
608 34 dgisselq
                dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
609
                dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
610
                dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
611
                dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
612 2 dgisselq
 
613 34 dgisselq
                dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
614
                dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
615
                dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
616
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
617 2 dgisselq
 
618 34 dgisselq
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
619
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
620 2 dgisselq
 
621 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
622 34 dgisselq
                        (m_cursor==26)?">":" ",
623 36 dgisselq
                        (cc & 0x200)?"TP":"  ",
624
                        (cc & 0x080)?"BK":"  ",
625 34 dgisselq
                        (cc & 0x040)?"ST":"  ",
626
                        (cc & 0x020)?"IE":"  ",
627
                        (cc & 0x010)?"SL":"  ",
628 2 dgisselq
                        (cc&8)?"V":" ",
629
                        (cc&4)?"N":" ",
630
                        (cc&2)?"C":" ",
631
                        (cc&1)?"Z":" ");
632 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
633 2 dgisselq
                ln++;
634
 
635 34 dgisselq
                if (gie)
636 2 dgisselq
                        attron(A_BOLD);
637
                else
638
                        attroff(A_BOLD);
639
                mvprintw(ln, 0, "User Registers"); ln++;
640 34 dgisselq
                dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
641
                dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
642
                dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
643
                dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
644 2 dgisselq
 
645 34 dgisselq
                dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
646
                dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
647
                dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
648
                dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
649 2 dgisselq
 
650 34 dgisselq
                dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
651
                dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
652
                dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
653
                dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
654 2 dgisselq
 
655 34 dgisselq
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
656
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
657 2 dgisselq
                cc = cmd_read(30);
658 34 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
659 36 dgisselq
                        (m_cursor == 42)?'>':' ',
660 34 dgisselq
                        (cc&0x100)?"TP":"  ",
661
                        (cc&0x040)?"ST":"  ",
662
                        (cc&0x020)?"IE":"  ",
663
                        (cc&0x010)?"SL":"  ",
664 2 dgisselq
                        (cc&8)?"V":" ",
665
                        (cc&4)?"N":" ",
666
                        (cc&2)?"C":" ",
667
                        (cc&1)?"Z":" ");
668 34 dgisselq
                dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
669 2 dgisselq
 
670
                attroff(A_BOLD);
671
                ln+=2;
672
 
673
                ln+=3;
674
 
675
                showins(ln, "I ",
676
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
677
                        m_core->v__DOT__thecpu__DOT__pf_valid,
678
                        m_core->v__DOT__thecpu__DOT__gie,
679
                        0,
680
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
681
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
682
 
683
                showins(ln, "Dc",
684
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
685
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
686
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
687
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
688
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
689
 
690
                showins(ln, "Op",
691
                        m_core->v__DOT__thecpu__DOT__op_ce,
692
                        m_core->v__DOT__thecpu__DOT__opvalid,
693
                        m_core->v__DOT__thecpu__DOT__op_gie,
694
                        m_core->v__DOT__thecpu__DOT__op_stall,
695 39 dgisselq
                        op_pc()); ln++;
696 2 dgisselq
 
697
                showins(ln, "Al",
698
                        m_core->v__DOT__thecpu__DOT__alu_ce,
699
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
700
                        m_core->v__DOT__thecpu__DOT__alu_gie,
701
                        m_core->v__DOT__thecpu__DOT__alu_stall,
702 39 dgisselq
                        alu_pc()); ln++;
703 2 dgisselq
        }
704
        void    tick(void) {
705
                int gie = m_core->v__DOT__thecpu__DOT__gie;
706
                /*
707
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
708
                                                m_core->o_qspi_sck,
709
                                                m_core->o_qspi_dat);
710
                */
711
 
712 11 dgisselq
                int stb = m_core->o_wb_stb;
713
                if ((m_core->o_wb_addr & (-1<<20))!=1)
714
                        stb = 0;
715
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
716
                        m_core->i_wb_ack = 1;
717 2 dgisselq
 
718
                if ((dbg_flag)&&(dbg_fp)) {
719 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
720 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
721
                                (m_core->i_dbg_stb)?"STB":
722
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
723
                                ((m_core->i_dbg_we)?"WE":"  "),
724
                                (m_core->i_dbg_addr),0,
725
                                m_core->i_dbg_data,
726
                                (m_core->o_dbg_ack)?"ACK":"   ",
727
                                (m_core->o_dbg_stall)?"STALL":"     ",
728
                                (m_core->o_dbg_data),
729
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
730
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
731
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
732
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
733
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
734 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
735
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
736 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
737
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
738
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
739
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
740
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
741
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
742
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
743
                                (m_core->v__DOT__sys_we)?"WE":"  ",
744
                                (m_core->v__DOT__sys_addr),
745
                                (m_core->v__DOT__dbg_addr),
746
                                (m_core->v__DOT__sys_data),
747
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
748
                                (m_core->v__DOT__wb_data));
749
                }
750
 
751
                if (dbg_fp)
752
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
753
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
754
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
755
                                m_core->v__DOT__thecpu__DOT__op_ce,
756 39 dgisselq
                                op_pc(),
757 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcdA,
758
                                m_core->v__DOT__thecpu__DOT__opR,
759
                                m_core->v__DOT__cmd_halt,
760
                                m_core->v__DOT__cpu_halt,
761
                                m_core->v__DOT__thecpu__DOT__alu_ce,
762
                                m_core->v__DOT__thecpu__DOT__alu_valid,
763
                                m_core->v__DOT__thecpu__DOT__alu_wr,
764
                                m_core->v__DOT__thecpu__DOT__alu_reg,
765
                                m_core->v__DOT__thecpu__DOT__ipc,
766
                                m_core->v__DOT__thecpu__DOT__upc);
767
 
768
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
769
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
770
                                m_core->v__DOT__pic_interrupt,
771
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
772
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
773
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
774
                                m_core->v__DOT__cmd_addr,
775
                                m_core->v__DOT__dbg_idata,
776
                                m_core->v__DOT__thecpu__DOT__master_ce,
777
                                m_core->v__DOT__thecpu__DOT__alu_wr,
778
                                m_core->v__DOT__thecpu__DOT__alu_valid,
779
                                m_core->v__DOT__thecpu__DOT__mem_valid);
780
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
781
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
782
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
783
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
784
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
785
                                m_core->v__DOT__cmd_addr,
786
                                m_core->v__DOT__dbg_idata,
787
                                m_core->v__DOT__thecpu__DOT__master_ce,
788
                                m_core->v__DOT__thecpu__DOT__alu_wr,
789
                                m_core->v__DOT__thecpu__DOT__alu_valid,
790
                                m_core->v__DOT__thecpu__DOT__mem_valid,
791
                                m_core->v__DOT__thecpu__DOT__w_iflags,
792
                                m_core->v__DOT__thecpu__DOT__w_uflags);
793 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
794
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
795 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
796
                                m_core->v__DOT__thecpu__DOT__op_break);
797 36 dgisselq
                } else if ((dbg_fp)&&
798
                                ((m_core->v__DOT__thecpu__DOT__op_break)
799
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
800
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
801
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
802
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
803
                                m_core->v__DOT__thecpu__DOT__break_en,
804
                                m_core->v__DOT__thecpu__DOT__dcd_break,
805
                                m_core->v__DOT__thecpu__DOT__op_break);
806 2 dgisselq
                }
807
 
808 34 dgisselq
                if (dbg_fp) {
809
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
810
                                fprintf(dbg_fp, "\tClear Pipeline\n");
811
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
812
                                fprintf(dbg_fp, "\tNew PC\n");
813
                }
814
 
815 36 dgisselq
                if (dbg_fp)
816
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
817
                if (false) {
818
                        m_core->i_clk = 1;
819
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
820
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
821
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
822
                        eval();
823
                        m_core->i_clk = 0;
824
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
825
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
826
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
827
                        eval();
828
                        m_tickcount++;
829
                } else {
830
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
831
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
832
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
833 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
834
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
835
                                m_core->i_wb_err = 1;
836
                        else
837
                                m_core->i_wb_err = 0;
838 36 dgisselq
                        TESTB<Vzipsystem>::tick();
839
                }
840 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
841
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
842
                                (gie)?"User":"Supervisor",
843
                                (gie)?"Supervisor":"User",
844
                                m_core->v__DOT__thecpu__DOT__ipc,
845
                                m_core->v__DOT__thecpu__DOT__upc,
846
                                m_core->v__DOT__thecpu__DOT__pf_pc);
847
                } if (dbg_fp) {
848
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
849
                                m_core->v__DOT__thecpu__DOT__opvalid,
850
                                m_core->v__DOT__thecpu__DOT__op_gie,
851
                                m_core->v__DOT__thecpu__DOT__op_stall,
852 39 dgisselq
                                op_pc());
853 2 dgisselq
                        dbgins("Al - ",
854
                                m_core->v__DOT__thecpu__DOT__alu_ce,
855
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
856
                                m_core->v__DOT__thecpu__DOT__alu_gie,
857
                                m_core->v__DOT__thecpu__DOT__alu_stall,
858 39 dgisselq
                                alu_pc());
859 2 dgisselq
 
860
                }
861
        }
862
 
863
        bool    test_success(void) {
864
                return ((!m_core->v__DOT__thecpu__DOT__gie)
865
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
866
        }
867
 
868 39 dgisselq
        unsigned        op_pc(void) {
869
                /*
870
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
871
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
872
                        r--;
873
                return r;
874
                */
875
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
876
        }
877
 
878
        unsigned        alu_pc(void) {
879
                /*
880
                unsigned        r = op_pc();
881
                if (m_core->v__DOT__thecpu__DOT__opvalid)
882
                        r--;
883
                return r;
884
                */
885
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
886
        }
887
 
888
#ifdef  OPT_PIPELINED_BUS_ACCESS
889
        int     mem_pipe_stalled(void) {
890
                int     r = 0;
891
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
892
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
893
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
894
                        ||(
895
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
896
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
897
                return r;
898
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
899
        }
900
#endif
901
 
902 2 dgisselq
        bool    test_failure(void) {
903 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
904
                        return 0;
905
                else if (m_core->v__DOT__thecpu__DOT__gie)
906
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x2f0f7fff);
907
                else
908
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x2f0f7fff);
909
                /*
910 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
911 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
912 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
913 43 dgisselq
                */
914 2 dgisselq
        }
915
 
916
        void    wb_write(unsigned a, unsigned int v) {
917 36 dgisselq
                int     errcount = 0;
918 2 dgisselq
                mvprintw(0,35, "%40s", "");
919
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
920
                m_core->i_dbg_cyc = 1;
921
                m_core->i_dbg_stb = 1;
922
                m_core->i_dbg_we  = 1;
923
                m_core->i_dbg_addr = a & 1;
924
                m_core->i_dbg_data = v;
925
 
926
                tick();
927 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
928 2 dgisselq
                        tick();
929
 
930
                m_core->i_dbg_stb = 0;
931 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
932 2 dgisselq
                        tick();
933
 
934
                // Release the bus
935
                m_core->i_dbg_cyc = 0;
936
                m_core->i_dbg_stb = 0;
937
                tick();
938
                mvprintw(0,35, "%40s", "");
939
                mvprintw(0,40, "wb_write -- complete");
940 36 dgisselq
 
941
 
942
                if (errcount >= 100)
943
                        bomb = true;
944 2 dgisselq
        }
945
 
946
        unsigned long   wb_read(unsigned a) {
947
                unsigned int    v;
948 36 dgisselq
                int     errcount = 0;
949 2 dgisselq
                mvprintw(0,35, "%40s", "");
950
                mvprintw(0,40, "wb_read(0x%08x)", a);
951
                m_core->i_dbg_cyc = 1;
952
                m_core->i_dbg_stb = 1;
953
                m_core->i_dbg_we  = 0;
954
                m_core->i_dbg_addr = a & 1;
955
 
956
                tick();
957 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
958 2 dgisselq
                        tick();
959
 
960
                m_core->i_dbg_stb = 0;
961 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
962 2 dgisselq
                        tick();
963
                v = m_core->o_dbg_data;
964
 
965
                // Release the bus
966
                m_core->i_dbg_cyc = 0;
967
                m_core->i_dbg_stb = 0;
968
                tick();
969
 
970
                mvprintw(0,35, "%40s", "");
971
                mvprintw(0,40, "wb_read = 0x%08x", v);
972
 
973 36 dgisselq
                if (errcount >= 100)
974
                        bomb = true;
975 2 dgisselq
                return v;
976
        }
977
 
978 34 dgisselq
        void    cursor_up(void) {
979
                if (m_cursor > 3)
980
                        m_cursor -= 4;
981
        } void  cursor_down(void) {
982
                if (m_cursor < 40)
983
                        m_cursor += 4;
984
        } void  cursor_left(void) {
985
                if (m_cursor > 0)
986
                        m_cursor--;
987
                else    m_cursor = 43;
988
        } void  cursor_right(void) {
989
                if (m_cursor < 43)
990
                        m_cursor++;
991
                else    m_cursor = 0;
992
        }
993
 
994
        int     cursor(void) { return m_cursor; }
995 2 dgisselq
};
996
 
997 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
998
        int     wy, wx, ra;
999
        int     c = tb->cursor();
1000
 
1001
        wx = (c & 0x03) * 20 + 9;
1002
        wy = (c>>2);
1003
        if (wy >= 3+4)
1004
                wy++;
1005
        if (wy > 3)
1006
                wy += 2;
1007
        wy++;
1008
 
1009
        if (c >= 12)
1010
                ra = c - 12;
1011
        else
1012
                ra = c + 32;
1013
 
1014
        bool    done = false;
1015
        char    str[16];
1016
        int     pos = 0; str[pos] = '\0';
1017
        while(!done) {
1018
                int     chv = getch();
1019
                switch(chv) {
1020
                case KEY_ESCAPE:
1021
                        pos = 0; str[pos] = '\0'; done = true;
1022
                        break;
1023
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1024
                        done = true;
1025
                        break;
1026
                case KEY_LEFT: case KEY_BACKSPACE:
1027
                        if (pos > 0) pos--;
1028
                        break;
1029 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1030 34 dgisselq
                case KEY_CLEAR:
1031
                        pos = 0;
1032
                        break;
1033
                case '0': case ' ': str[pos++] = '0'; break;
1034
                case '1': str[pos++] = '1'; break;
1035
                case '2': str[pos++] = '2'; break;
1036
                case '3': str[pos++] = '3'; break;
1037
                case '4': str[pos++] = '4'; break;
1038
                case '5': str[pos++] = '5'; break;
1039
                case '6': str[pos++] = '6'; break;
1040
                case '7': str[pos++] = '7'; break;
1041
                case '8': str[pos++] = '8'; break;
1042
                case '9': str[pos++] = '9'; break;
1043
                case 'A': case 'a': str[pos++] = 'A'; break;
1044
                case 'B': case 'b': str[pos++] = 'B'; break;
1045
                case 'C': case 'c': str[pos++] = 'C'; break;
1046
                case 'D': case 'd': str[pos++] = 'D'; break;
1047
                case 'E': case 'e': str[pos++] = 'E'; break;
1048
                case 'F': case 'f': str[pos++] = 'F'; break;
1049
                }
1050
 
1051
                if (pos > 8)
1052
                        pos = 8;
1053
                str[pos] = '\0';
1054
 
1055
                attron(A_NORMAL | A_UNDERLINE);
1056
                mvprintw(wy, wx, "%-8s", str);
1057
                if (pos > 0) {
1058
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1059
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1060
                }
1061
                attrset(A_NORMAL);
1062
        }
1063
 
1064
        if (pos > 0) {
1065
                int     v;
1066
                v = strtoul(str, NULL, 16);
1067
                if (!tb->halted()) {
1068
                        switch(ra) {
1069
                        case 15:
1070
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1071
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1072
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1073
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1074
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1075
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1076
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1077
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1078
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1079
                                }
1080
                                break;
1081
                        case 31:
1082
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1083
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1084
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1085
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1086
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1087
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1088
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1089
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1090
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1091
                                }
1092
                                break;
1093
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1094
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1095 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1096 34 dgisselq
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
1097
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1098
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1099
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1100
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1101
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1102
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1103
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1104
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1105
                        default:
1106
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1107
                                break;
1108
                        }
1109
                } else
1110
                        tb->cmd_write(ra, v);
1111
        }
1112
}
1113
 
1114 27 dgisselq
void    usage(void) {
1115
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1116
        printf("\n");
1117
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1118
        printf("\t-a\tSets the testbench to run automatically without any\n");
1119
        printf("\t\tuser interaction.\n");
1120
        printf("\n");
1121
        printf("\tUser Commands:\n");
1122
        printf("\t\tWhen the test bench is run interactively, the following\n");
1123
        printf("\t\tkey strokes are recognized:\n");
1124
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1125
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1126
        printf("\t\t\tuser intervention.\n");
1127
        printf("\t\t\'q\'\tQuit the simulation.\n");
1128
        printf("\t\t\'r\'\tReset the processor.\n");
1129
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1130
        printf("\t\t\tThis may consume more than one tick.\n");
1131
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1132
}
1133 2 dgisselq
 
1134 43 dgisselq
bool    signalled = false;
1135
 
1136
void    sigint(int v) {
1137
        signalled = true;
1138
}
1139
 
1140 2 dgisselq
int     main(int argc, char **argv) {
1141
        Verilated::commandArgs(argc, argv);
1142
        ZIPPY_TB        *tb = new ZIPPY_TB();
1143 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1144 2 dgisselq
 
1145
        // mem[0x00000] = 0xbe000010; // Halt instruction
1146
        unsigned int mptr = 0;
1147
 
1148 43 dgisselq
        signal(SIGINT, sigint);
1149
 
1150 9 dgisselq
        if (argc <= 1) {
1151 27 dgisselq
                usage();
1152
                exit(-1);
1153 9 dgisselq
        } else {
1154
                for(int argn=1; argn<argc; argn++) {
1155 27 dgisselq
                        if (argv[argn][0] == '-') {
1156
                                switch(argv[argn][1]) {
1157
                                case 'a':
1158
                                        autorun = true;
1159
                                        break;
1160
                                case 'e':
1161
                                        exit_on_done = true;
1162
                                        break;
1163
                                case 'h':
1164
                                        usage();
1165
                                        exit(0);
1166
                                        break;
1167 36 dgisselq
                                case 's':
1168
                                        autostep = true;
1169
                                        break;
1170 27 dgisselq
                                default:
1171
                                        usage();
1172
                                        exit(-1);
1173
                                        break;
1174
                                }
1175
                        } else if (access(argv[argn], R_OK)==0) {
1176 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1177
                                if (fp == NULL) {
1178
                                        printf("Cannot open %s\n", argv[argn]);
1179
                                        perror("O/S Err: ");
1180
                                        exit(-1);
1181
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1182
                                fclose(fp);
1183
                        }
1184
                }
1185
        }
1186
 
1187 27 dgisselq
        if (autorun) {
1188
                bool    done = false;
1189 2 dgisselq
 
1190 27 dgisselq
                printf("Running in non-interactive mode\n");
1191
                tb->reset();
1192
                for(int i=0; i<2; i++)
1193
                        tb->tick();
1194
                tb->m_core->v__DOT__cmd_halt = 0;
1195
                while(!done) {
1196
                        tb->tick();
1197
 
1198
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1199
                                // tb->m_core->v__DOT__cmd_halt = 0;
1200
                                // tb->m_core->v__DOT__cmd_step = 0;
1201
 
1202 34 dgisselq
                        /*
1203 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1204
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1205
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1206
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1207 34 dgisselq
                        */
1208 27 dgisselq
 
1209
                        done = (tb->test_success())||(tb->test_failure());
1210 43 dgisselq
                        done = done || signalled;
1211 27 dgisselq
                }
1212 36 dgisselq
        } else if (autostep) {
1213
                bool    done = false;
1214
 
1215
                printf("Running in non-interactive mode, via step commands\n");
1216
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1217
                while(!done) {
1218
                        tb->wb_write(CMD_REG, CMD_STEP);
1219
                        done = (tb->test_success())||(tb->test_failure());
1220 43 dgisselq
                        done = done || signalled;
1221 36 dgisselq
                }
1222 27 dgisselq
        } else { // Interactive
1223
                initscr();
1224
                raw();
1225
                noecho();
1226
                keypad(stdscr, true);
1227
 
1228
                tb->reset();
1229
                for(int i=0; i<2; i++)
1230
                        tb->tick();
1231
                tb->m_core->v__DOT__cmd_halt = 0;
1232
 
1233
                int     chv = 'q';
1234
 
1235 43 dgisselq
                bool    done = false, halted = true, manual = true,
1236
                        high_speed = false;
1237 2 dgisselq
 
1238
                halfdelay(1);
1239 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1240 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1241
                        // tb->show_state();
1242
 
1243
                while(!done) {
1244 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1245
                                struct  pollfd  fds[1];
1246
                                fds[0].fd = STDIN_FILENO;
1247
                                fds[0].events = POLLIN;
1248
                                if (poll(fds, 1, 0) > 0)
1249
                                        chv = getch();
1250
                                else
1251
                                        chv = ERR;
1252
                        } else {
1253
                                chv = getch();
1254
                        }
1255 2 dgisselq
                        switch(chv) {
1256
                        case 'h': case 'H':
1257
                                tb->wb_write(CMD_REG, CMD_HALT);
1258
                                if (!halted)
1259
                                        erase();
1260
                                halted = true;
1261
                                break;
1262 43 dgisselq
                        case 'G':
1263
                                high_speed = true;
1264
                        case 'g':
1265 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1266
                                if (halted)
1267
                                        erase();
1268
                                halted = false;
1269
                                manual = false;
1270
                                break;
1271 43 dgisselq
                        case 'm':
1272
                                tb->show_user_timers(false);
1273
                                break;
1274 2 dgisselq
                        case 'q': case 'Q':
1275
                                done = true;
1276
                                break;
1277
                        case 'r': case 'R':
1278 36 dgisselq
                                if (manual)
1279
                                        tb->reset();
1280
                                else
1281
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1282 2 dgisselq
                                halted = true;
1283
                                erase();
1284
                                break;
1285 39 dgisselq
                        case 's':
1286 34 dgisselq
                                if (!halted)
1287 27 dgisselq
                                        erase();
1288 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
1289
                                manual = false;
1290 34 dgisselq
                                halted = true;
1291 43 dgisselq
                                high_speed = false;
1292 2 dgisselq
                                break;
1293 39 dgisselq
                        case 'S':
1294 34 dgisselq
                                if ((!manual)||(halted))
1295 27 dgisselq
                                        erase();
1296 2 dgisselq
                                manual = true;
1297 39 dgisselq
                                halted = true;
1298 43 dgisselq
                                high_speed = false;
1299 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1300
                                tb->m_core->v__DOT__cmd_step = 1;
1301
                                tb->eval();
1302
                                tb->tick();
1303
                                break;
1304
                        case 'T': // 
1305
                                if ((!manual)||(halted))
1306
                                        erase();
1307
                                manual = true;
1308
                                halted = true;
1309 43 dgisselq
                                high_speed = false;
1310 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1311
                                tb->m_core->v__DOT__cmd_step = 0;
1312
                                tb->eval();
1313
                                tb->tick();
1314
                                break;
1315
                        case 't':
1316
                                if ((!manual)||(halted))
1317
                                        erase();
1318
                                manual = true;
1319 34 dgisselq
                                halted = false;
1320 43 dgisselq
                                high_speed = false;
1321 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1322
                //              tb->m_core->v__DOT__cmd_halt = 0;
1323
                //              tb->m_core->v__DOT__cmd_step = 0;
1324 2 dgisselq
                                tb->tick();
1325
                                break;
1326 43 dgisselq
                        case 'u':
1327
                                tb->show_user_timers(true);
1328
                                break;
1329 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1330
                                get_value(tb);
1331
                                break;
1332
                        case    KEY_UP:         tb->cursor_up();        break;
1333
                        case    KEY_DOWN:       tb->cursor_down();      break;
1334
                        case    KEY_LEFT:       tb->cursor_left();      break;
1335
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1336 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1337 34 dgisselq
                        case ERR: case KEY_CLEAR:
1338 2 dgisselq
                        default:
1339
                                if (!manual)
1340
                                        tb->tick();
1341
                        }
1342
 
1343
                        if (manual) {
1344
                                tb->show_state();
1345
                        } else if (halted) {
1346
                                if (tb->dbg_fp)
1347
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1348
                                tb->read_state();
1349
                        } else
1350
                                tb->show_state();
1351
 
1352
                        if (tb->m_core->i_rst)
1353
                                done =true;
1354 43 dgisselq
                        if ((tb->bomb)||(signalled))
1355 2 dgisselq
                                done = true;
1356 27 dgisselq
 
1357
                        if (exit_on_done) {
1358
                                if (tb->test_success())
1359
                                        done = true;
1360
                                if (tb->test_failure())
1361
                                        done = true;
1362
                        }
1363 2 dgisselq
                }
1364 27 dgisselq
                endwin();
1365
        }
1366
#ifdef  MANUAL_STEPPING_MODE
1367
         else { // Manual stepping mode
1368 2 dgisselq
                tb->show_state();
1369
 
1370
                while('q' != tolower(chv = getch())) {
1371
                        tb->tick();
1372
                        tb->show_state();
1373
 
1374
                        if (tb->test_success())
1375
                                break;
1376
                        else if (tb->test_failure())
1377
                                break;
1378 43 dgisselq
                        else if (signalled)
1379
                                break;
1380 2 dgisselq
                }
1381
        }
1382 27 dgisselq
#endif
1383 2 dgisselq
 
1384 43 dgisselq
        printf("\n");
1385 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1386
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1387 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1388 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1389
                printf("Instructions / Clock: %.2f\n",
1390
                        (double)tb->m_core->v__DOT__mic_data
1391
                        / (double)tb->m_core->v__DOT__mtc_data);
1392 36 dgisselq
 
1393
        int     rcode = 0;
1394
        if (tb->bomb) {
1395
                printf("TEST BOMBED\n");
1396
                rcode = -1;
1397
        } else if (tb->test_success()) {
1398 2 dgisselq
                printf("SUCCESS!\n");
1399 36 dgisselq
        } else if (tb->test_failure()) {
1400
                rcode = -2;
1401 2 dgisselq
                printf("TEST FAILED!\n");
1402 36 dgisselq
        } else
1403 27 dgisselq
                printf("User quit\n");
1404 43 dgisselq
        delete tb;
1405 36 dgisselq
        exit(rcode);
1406 2 dgisselq
}
1407
 

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