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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 87

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68 57 dgisselq
#define MAXERR          10000
69
 
70 76 dgisselq
 
71
class   SPARSEMEM {
72
public:
73
        bool    m_valid;
74
        unsigned int    m_a, m_d;
75
};
76
 
77
class   ZIPSTATE {
78
public:
79
        bool            m_valid, m_gie, m_last_pc_valid;
80
        unsigned int    m_sR[16], m_uR[16];
81
        unsigned int    m_p[20];
82
        unsigned int    m_last_pc, m_pc, m_sp;
83
        SPARSEMEM       m_smem[5];
84
        SPARSEMEM       m_imem[5];
85
        ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
86
 
87
        void    step(void) {
88
                m_last_pc_valid = true;
89
                m_last_pc = m_pc;
90
        }
91
};
92
 
93
 
94 2 dgisselq
// No particular "parameters" need definition or redefinition here.
95
class   ZIPPY_TB : public TESTB<Vzipsystem> {
96
public:
97 9 dgisselq
        unsigned long   m_mem_size;
98 2 dgisselq
        MEMSIM          m_mem;
99
        // QSPIFLASHSIM m_flash;
100 58 dgisselq
        FILE            *dbg_fp, *m_profile_fp;
101 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
102 34 dgisselq
        int             m_cursor;
103 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
104 76 dgisselq
        ZIPSTATE        m_state;
105 2 dgisselq
 
106 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
107 76 dgisselq
                if (false) {
108 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
109
                        dbg_flag = true;
110
                } else {
111
                        dbg_fp = NULL;
112
                        dbg_flag = false;
113
                }
114 2 dgisselq
                bomb = false;
115 34 dgisselq
                m_cursor = 0;
116 43 dgisselq
                m_show_user_timers = false;
117 58 dgisselq
 
118
                m_last_instruction_tickcount = 0l;
119
                if (true) {
120
                        m_profile_fp = fopen("pfile.bin","wb");
121
                } else {
122
                        m_profile_fp = NULL;
123
                }
124 2 dgisselq
        }
125
 
126 69 dgisselq
        ~ZIPPY_TB(void) {
127
                if (dbg_fp)
128
                        fclose(dbg_fp);
129
                if (m_profile_fp)
130
                        fclose(m_profile_fp);
131
        }
132
 
133 2 dgisselq
        void    reset(void) {
134
                // m_flash.debug(false);
135
                TESTB<Vzipsystem>::reset();
136
        }
137
 
138
        bool    on_tick(void) {
139
                tick();
140
                return true;
141
        }
142
 
143 76 dgisselq
        void    step(void) {
144
                wb_write(CMD_REG, CMD_STEP);
145
                m_state.step();
146
        }
147
 
148
        void    read_raw_state(void) {
149
                m_state.m_valid = false;
150
                for(int i=0; i<16; i++)
151
                        m_state.m_sR[i] = cmd_read(i);
152
                for(int i=0; i<16; i++)
153
                        m_state.m_uR[i] = cmd_read(i+16);
154
                for(int i=0; i<20; i++)
155
                        m_state.m_p[i]  = cmd_read(i+32);
156
 
157
                m_state.m_gie = (m_state.m_sR[14] & 0x020);
158
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
159
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
160
 
161
                if (m_state.m_last_pc_valid)
162
                        m_state.m_imem[0].m_a = m_state.m_last_pc;
163
                else
164
                        m_state.m_imem[0].m_a = m_state.m_pc - 1;
165
                m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
166
                m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
167
                m_state.m_imem[1].m_a = m_state.m_pc;
168
                m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
169
                m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
170
 
171
                for(int i=1; i<4; i++) {
172
                        if (!m_state.m_imem[i].m_valid) {
173
                                m_state.m_imem[i+1].m_valid = false;
174
                                m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
175
                                continue;
176
                        }
177
                        m_state.m_imem[i+1].m_a = zop_early_branch(
178
                                        m_state.m_imem[i].m_a,
179
                                        m_state.m_imem[i].m_d);
180
                        m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
181
                        m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
182
                }
183
 
184
                m_state.m_smem[0].m_a = m_state.m_sp;
185
                for(int i=1; i<5; i++)
186
                        m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
187
                for(int i=0; i<5; i++) {
188
                        m_state.m_smem[i].m_valid =
189
                                (m_state.m_imem[i].m_a > 0x10000);
190
                        m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
191
                }
192
                m_state.m_valid = true;
193
        }
194
 
195
        void    read_raw_state_cheating(void) {
196
                m_state.m_valid = false;
197
                for(int i=0; i<16; i++)
198
                        m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
199
                m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
200
                m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
201
                for(int i=0; i<16; i++)
202
                        m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
203
                m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
204
                m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__upc;
205
 
206
                m_state.m_gie = (m_state.m_sR[14] & 0x020);
207
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
208
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
209
 
210
                m_state.m_p[0] = m_core->v__DOT__pic_data;
211
                m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
212
                if (!m_show_user_timers) {
213
                        m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
214
                } else {
215
                        m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
216
                }
217
 
218
                m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
219
                m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
220
                m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
221
                m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
222
                m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
223
 
224
                m_state.m_p[ 8] = m_core->v__DOT__utc_data;
225
                m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
226
                m_state.m_p[10] = m_core->v__DOT__upc_data;
227
                m_state.m_p[11] = m_core->v__DOT__uic_data;
228
 
229
                m_state.m_p[12] = m_core->v__DOT__mtc_data;
230
                m_state.m_p[13] = m_core->v__DOT__moc_data;
231
                m_state.m_p[14] = m_core->v__DOT__mpc_data;
232
                m_state.m_p[15] = m_core->v__DOT__mic_data;
233
 
234
        }
235
 
236 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
237
                if (c)
238
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
239
                else
240
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
241 2 dgisselq
        }
242
 
243 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
244 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
245 34 dgisselq
                if (c)
246
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
247
                else
248
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
249 2 dgisselq
        }
250
 
251 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
252 76 dgisselq
                if (r < 16)
253
                        dispreg(y, x, n, m_state.m_sR[r], c);
254 34 dgisselq
                else
255 76 dgisselq
                        dispreg(y, x, n, m_state.m_uR[r-16], c);
256
                move(y,x+17);
257
 
258 69 dgisselq
#ifdef  OPT_PIPELINED
259 76 dgisselq
                addch( ((r == (int)(dcdA()&0x01f))&&(dcdvalid())
260 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
261 34 dgisselq
                        ?'a':((c)?'<':' '));
262 76 dgisselq
                addch( ((r == (int)(dcdB()&0x01f))&&(dcdvalid())
263 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
264 76 dgisselq
                        ?'b':' ');
265 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
266
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
267 76 dgisselq
                        ?'W':' ');
268
#else
269
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
270
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
271 34 dgisselq
                        ?'W':((c)?'<':' '));
272 76 dgisselq
#endif
273 2 dgisselq
        }
274
 
275
        void    showins(int y, const char *lbl, const int ce, const int valid,
276 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
277
                        const bool phase) {
278
                char    la[80], lb[80];
279 2 dgisselq
 
280
                if (ce)
281
                        mvprintw(y, 0, "Ck ");
282
                else
283
                        mvprintw(y, 0, "   ");
284
                if (stall)
285
                        printw("Stl ");
286
                else
287
                        printw("    ");
288
                printw("%s: 0x%08x", lbl, pc);
289
 
290
                if (valid) {
291
                        if (gie) attroff(A_BOLD);
292
                        else    attron(A_BOLD);
293 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
294
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
295
                                printw("  %-24s", la);
296
                        else
297
                                printw("  %-24s", lb);
298 2 dgisselq
                } else {
299
                        attroff(A_BOLD);
300
                        printw("  (0x%08x)%28s", m_mem[pc],"");
301
                }
302
                attroff(A_BOLD);
303
        }
304
 
305
        void    dbgins(const char *lbl, const int ce, const int valid,
306 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
307
                        const bool phase, const bool illegal) {
308
                char    la[80], lb[80];
309 2 dgisselq
 
310
                if (!dbg_fp)
311
                        return;
312
 
313
                if (ce)
314
                        fprintf(dbg_fp, "%s Ck ", lbl);
315
                else
316
                        fprintf(dbg_fp, "%s    ", lbl);
317
                if (stall)
318
                        fprintf(dbg_fp, "Stl ");
319
                else
320
                        fprintf(dbg_fp, "    ");
321
                fprintf(dbg_fp, "0x%08x:  ", pc);
322
 
323
                if (valid) {
324 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
325
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
326
                                fprintf(dbg_fp, "  %-24s", la);
327
                        else
328
                                fprintf(dbg_fp, "  %-24s", lb);
329 2 dgisselq
                } else {
330 76 dgisselq
                        fprintf(dbg_fp, "  (0x%08x)", m_mem[pc]);
331
                } if (illegal)
332
                        fprintf(dbg_fp, " (Illegal)");
333
                fprintf(dbg_fp, "\n");
334 2 dgisselq
        }
335
 
336
        void    show_state(void) {
337
                int     ln= 0;
338
 
339 76 dgisselq
                read_raw_state_cheating();
340
 
341 2 dgisselq
                mvprintw(ln,0, "Peripherals-SS"); ln++;
342 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
343 36 dgisselq
                printw(" %s",
344
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
345
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
346
                        );
347 39 dgisselq
#endif
348
 
349
#ifdef  OPT_EARLY_BRANCHING
350 69 dgisselq
                printw(" %s",
351
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)?"EB":"  ");
352 39 dgisselq
#endif
353 36 dgisselq
 
354
                /*
355 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
356
                        mvprintw(ln, 17, "%s%s",
357
                                ((m_core->v__DOT__sys_cyc)
358
                                &&(m_core->v__DOT__sys_we)
359
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
360
                                (m_core->v__DOT__trap_int)?"I":" ");
361
                */
362 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
363
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
364 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
365 57 dgisselq
 
366
                if (!m_show_user_timers) {
367
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
368
                } else {
369
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
370
                }
371
 
372 76 dgisselq
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
373 2 dgisselq
 
374
                ln++;
375 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
376
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
377
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
378
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
379 2 dgisselq
 
380 43 dgisselq
 
381
                if (!m_show_user_timers) {
382
                        ln++;
383 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
384
                        showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
385
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
386
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
387 43 dgisselq
                } else {
388
                        ln++;
389 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
390
                        showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
391
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
392
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
393 43 dgisselq
                }
394 2 dgisselq
 
395
                ln++;
396
                mvprintw(ln, 40, "%s %s",
397
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
398
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
399 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
400 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
401
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
402
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
403 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
404
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
405
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
406 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
407
                        attroff(A_BOLD);
408
                else
409
                        attron(A_BOLD);
410
                mvprintw(ln, 0, "Supervisor Registers");
411
                ln++;
412
 
413 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
414
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
415
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
416
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
417 2 dgisselq
 
418 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
419
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
420
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
421
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
422 2 dgisselq
 
423 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
424
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
425
                showreg(ln,40, "sR10", 10, (m_cursor==22));
426
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
427 2 dgisselq
 
428 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
429
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
430 76 dgisselq
 
431
                unsigned int cc = m_state.m_sR[14];
432
                if (true) {
433
                        mvprintw(ln,40, "%ssCC : 0x%08x",
434
                                (m_cursor==26)?">":" ", cc);
435
                } else {
436
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
437
                                (m_cursor==26)?">":" ",
438
                                (cc&0x01000)?"FE":"",
439
                                (cc&0x00800)?"DE":"",
440
                                (cc&0x00400)?"BE":"",
441
                                (cc&0x00200)?"TP":"",
442
                                (cc&0x00100)?"IL":"",
443
                                (cc&0x00080)?"BK":"",
444
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
445
                        mvprintw(ln, 54, "%s%s%s%s",
446
                                (cc&8)?"V":" ",
447
                                (cc&4)?"N":" ",
448
                                (cc&2)?"C":" ",
449
                                (cc&1)?"Z":" ");
450
                }
451
                showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
452 69 dgisselq
                mvprintw(ln,60,"%s",
453
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
454
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
455
                                ?"V"
456
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
457
                                &&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
458
                        :" "));
459 2 dgisselq
                ln++;
460
 
461
                if (m_core->v__DOT__thecpu__DOT__gie)
462
                        attron(A_BOLD);
463
                else
464
                        attroff(A_BOLD);
465 69 dgisselq
                mvprintw(ln, 0, "User Registers");
466
                mvprintw(ln, 42, "DCDR=%02x %s%s",
467
                        dcdR(),
468
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
469
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
470
                mvprintw(ln, 62, "OPR =%02x %s%s",
471
                        m_core->v__DOT__thecpu__DOT__opR,
472
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
473
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
474
                ln++;
475 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
476
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
477
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
478
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
479 2 dgisselq
 
480 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
481
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
482
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
483
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
484 2 dgisselq
 
485 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
486
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
487
                showreg(ln,40, "uR10", 26, (m_cursor==38));
488
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
489 2 dgisselq
 
490 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
491
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
492 76 dgisselq
                cc = m_state.m_uR[14];
493
                if (false) {
494
                        mvprintw(ln,40, "%cuCC : 0x%08x",
495
                                (m_cursor == 42)?'>':' ', cc);
496
                } else {
497
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
498
                                (m_cursor == 42)?'>':' ',
499
                                (cc & 0x1000)?"FE":"",
500
                                (cc & 0x0800)?"DE":"",
501
                                (cc & 0x0400)?"BE":"",
502
                                (cc & 0x0200)?"TP":"",
503
                                (cc & 0x0100)?"IL":"",
504
                                (cc & 0x0040)?"ST":"",
505
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
506
                        mvprintw(ln, 54, "%s%s%s%s",
507
                                (cc&8)?"V":" ",
508
                                (cc&4)?"N":" ",
509
                                (cc&2)?"C":" ",
510
                                (cc&1)?"Z":" ");
511
                }
512
                showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
513 69 dgisselq
                mvprintw(ln,60,"%s",
514
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
515
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
516
                                ?"V"
517
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
518
                                &&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
519
                        :" "));
520 2 dgisselq
 
521
                attroff(A_BOLD);
522
                ln+=1;
523
 
524 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
525 69 dgisselq
                ln++;
526
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
527
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
528
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
529
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
530
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
531
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
532
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
533
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
534
                        (m_core->v__DOT__wb_data)); ln++;
535 39 dgisselq
#else
536 69 dgisselq
 
537 76 dgisselq
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
538 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
539
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
540 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
541 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
542
                        m_core->v__DOT__thecpu__DOT__pf_pc,
543
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
544
 
545 2 dgisselq
                ln++;
546
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
547
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
548
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
549
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
550
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
551
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
552
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
553 69 dgisselq
                        (pfstall())?"STL":"   ",
554 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
555 39 dgisselq
#endif
556 2 dgisselq
 
557
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
558 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
559
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
560
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
561
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
562 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
563
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
564
                        (m_core->v__DOT__thecpu__DOT__mem_data),
565
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
566 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
567 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
568
// #define      OPT_PIPELINED_BUS_ACCESS
569
#ifdef  OPT_PIPELINED_BUS_ACCESS
570
                printw(" %x%x%c%c",
571
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
572
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
573
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
574
                        (mem_pipe_stalled())?'S':'-'); ln++;
575
#else
576
                ln++;
577
#endif
578 2 dgisselq
 
579 69 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
580 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
581 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
582
                        (m_core->o_wb_stb)?"STB":"   ",
583
                        (m_core->o_wb_we )?"WE":"  ",
584
                        (m_core->o_wb_addr),
585
                        (m_core->o_wb_data),
586
                        (m_core->i_wb_ack)?"ACK":"   ",
587
                        (m_core->i_wb_stall)?"STL":"   ",
588 69 dgisselq
                        (m_core->i_wb_data),
589
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
590 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
591
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
592
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
593 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
594
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
595
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
596
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
597 58 dgisselq
                        (!mem_stalled()),       //1
598 2 dgisselq
 
599 58 dgisselq
                        (mem_stalled()),
600 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
601
                        (m_core->v__DOT__thecpu__DOT__master_ce),
602
                        (mem_pipe_stalled()),
603
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
604 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
605
                        );
606 76 dgisselq
                printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__dcd_pipe);
607
                // mvprintw(4,4,"r_dcdI = 0x%06x",
608
                        // (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
609 39 dgisselq
#endif
610
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
611 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
612
                printw(" A:%c%c B:%c%c",
613 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
614
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
615 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
616
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
617 69 dgisselq
#else
618
                printw(" A:xx B:xx");
619 57 dgisselq
#endif
620 69 dgisselq
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
621 39 dgisselq
 
622
 
623 2 dgisselq
                showins(ln, "I ",
624 69 dgisselq
#ifdef  OPT_PIPELINED
625 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
626 69 dgisselq
#else
627
                        1,
628
#endif
629 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
630
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
631
                        m_core->v__DOT__thecpu__DOT__gie,
632
                        0,
633 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
634
                        true); ln++;
635 36 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
636 2 dgisselq
 
637
                showins(ln, "Dc",
638 69 dgisselq
                        dcd_ce(), dcdvalid(),
639 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
640 69 dgisselq
#ifdef  OPT_PIPELINED
641 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
642 69 dgisselq
#else
643
                        0,
644
#endif
645 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
646
#ifdef  OPT_VLIW
647
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
648
#else
649
                        false
650
#endif
651
                        ); ln++;
652 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
653
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
654
                        mvprintw(ln-1,10,"I");
655
                else
656
#endif
657
                if (m_core->v__DOT__thecpu__DOT__dcdM)
658
                        mvprintw(ln-1,10,"M");
659 2 dgisselq
 
660
                showins(ln, "Op",
661 69 dgisselq
                        op_ce(),
662 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
663
                        m_core->v__DOT__thecpu__DOT__op_gie,
664
                        m_core->v__DOT__thecpu__DOT__op_stall,
665 76 dgisselq
                        op_pc(),
666
#ifdef  OPT_VLIW
667
                        m_core->v__DOT__thecpu__DOT__r_op_phase
668
#else
669
                        false
670
#endif
671
                        ); ln++;
672 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
673
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
674
                        mvprintw(ln-1,10,"I");
675
                else
676
#endif
677
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
678
                        mvprintw(ln-1,10,"M");
679
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
680
                        mvprintw(ln-1,10,"A");
681 2 dgisselq
 
682
                showins(ln, "Al",
683
                        m_core->v__DOT__thecpu__DOT__alu_ce,
684
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
685
                        m_core->v__DOT__thecpu__DOT__alu_gie,
686 69 dgisselq
#ifdef  OPT_PIPELINED
687 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__alu_stall,
688 69 dgisselq
#else
689
                        0,
690
#endif
691 76 dgisselq
                        alu_pc(),
692
#ifdef  OPT_VLIW
693
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
694
#else
695
                        false
696
#endif
697
                        ); ln++;
698 39 dgisselq
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
699
                        mvprintw(ln-1,10,"W");
700 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
701
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
702
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
703
                        mvprintw(ln-1,10,"v");
704 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
705 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
706
                        mvprintw(ln-1,10,"I");
707 58 dgisselq
#endif
708 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
709
                        // mvprintw(ln-1,10,"i");
710 2 dgisselq
 
711 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
712 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
713
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
714 2 dgisselq
                mvprintw(ln-4, 48,
715
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
716
                printw("(%s:%02x,%x)",
717
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
718
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
719
                        (m_core->v__DOT__thecpu__DOT__op_gie)
720
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
721
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
722
 
723
                printw("(%s%s%s:%02x)",
724
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
725
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
726
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
727
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
728
                /*
729
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
730
                        m_core->v__DOT__thecpu__DOT__dcdI);
731
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
732
                        m_core->v__DOT__thecpu__DOT__opB);
733
                */
734 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
735 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
736 87 dgisselq
                        m_core->v__DOT__thecpu__DOT__opA,
737
                        m_core->v__DOT__thecpu__DOT__opB);
738 27 dgisselq
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
739
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
740
                else
741
                        printw("%8s","");
742 76 dgisselq
                mvprintw(ln-1, 48, "%s%s%s ",
743
                        (m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
744 87 dgisselq
                          :((m_core->v__DOT__thecpu__DOT__doalu__DOT__genblk2__DOT__r_busy)?"a":" "),
745 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"D"
746
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
747
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"F"
748
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
749
                printw("MEM: %s%s %s%s %s %-5s",
750 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
751 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
752
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
753 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
754 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
755 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
756
        }
757
 
758 43 dgisselq
        void    show_user_timers(bool v) {
759
                m_show_user_timers = v;
760
        }
761
 
762 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
763 57 dgisselq
                int     errcount = 0;
764 2 dgisselq
                if (dbg_fp) {
765
                        dbg_flag= true;
766
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
767
                }
768
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
769 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
770
                        errcount++;
771
                if (errcount >= MAXERR) {
772
                        endwin();
773
 
774
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
775
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
776
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
777
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
778
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
779
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
780
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
781 69 dgisselq
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
782
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
783
#ifdef  OPT_PIPELINED
784 57 dgisselq
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
785 69 dgisselq
#endif
786 57 dgisselq
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
787 69 dgisselq
#ifdef  OPT_EARLY_BRANCHING
788
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
789
#endif
790 57 dgisselq
 
791
                        exit(-2);
792
                }
793
 
794
                assert(errcount < MAXERR);
795 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
796
 
797
                if (dbg_flag)
798 76 dgisselq
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a, v);
799 2 dgisselq
                dbg_flag = false;
800
                return v;
801
        }
802
 
803 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
804 57 dgisselq
                int     errcount = 0;
805 34 dgisselq
                if ((a&0x0f)==0x0f)
806
                        dbg_flag = true;
807
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
808 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
809
                        errcount++;
810
                assert(errcount < MAXERR);
811 34 dgisselq
                if (dbg_flag)
812
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
813
                wb_write(CMD_DATA, v);
814
        }
815
 
816 27 dgisselq
        bool    halted(void) {
817
                return (m_core->v__DOT__cmd_halt != 0);
818
        }
819
 
820 2 dgisselq
        void    read_state(void) {
821
                int     ln= 0;
822 34 dgisselq
                bool    gie;
823 2 dgisselq
 
824 76 dgisselq
                read_raw_state();
825 34 dgisselq
                if (m_cursor < 0)
826
                        m_cursor = 0;
827
                else if (m_cursor >= 44)
828
                        m_cursor = 43;
829
 
830
                mvprintw(ln,0, "Peripherals-RS");
831
                mvprintw(ln,40,"%-40s", "CPU State: ");
832
                {
833
                        unsigned int v = wb_read(CMD_REG);
834
                        mvprintw(ln,51, "");
835
                        if (v & 0x010000)
836
                                printw("EXT-INT ");
837
                        if ((v & 0x003000) == 0x03000)
838
                                printw("Halted ");
839
                        else if (v & 0x001000)
840
                                printw("Sleeping ");
841
                        else if (v & 0x002000)
842 76 dgisselq
                                printw("User Mod ");
843 34 dgisselq
                        if (v & 0x008000)
844
                                printw("Break-Enabled ");
845
                        if (v & 0x000080)
846
                                printw("PIC Enabled ");
847
                } ln++;
848 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
849
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
850
                showval(ln,40, "WBUS", m_state.m_p[2], false);
851
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
852 2 dgisselq
                ln++;
853 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
854
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
855
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
856
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
857 2 dgisselq
 
858
                ln++;
859 43 dgisselq
                if (!m_show_user_timers) {
860 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
861
                        showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
862
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
863
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
864 43 dgisselq
                } else {
865 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
866
                        showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
867
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
868
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
869 43 dgisselq
                }
870 2 dgisselq
 
871
                ln++;
872
                ln++;
873 76 dgisselq
                unsigned int cc = m_state.m_sR[14];
874 2 dgisselq
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
875
                        m_core->v__DOT__thecpu__DOT__gie);
876 34 dgisselq
                gie = (cc & 0x020);
877
                if (gie)
878 2 dgisselq
                        attroff(A_BOLD);
879
                else
880
                        attron(A_BOLD);
881
                mvprintw(ln, 0, "Supervisor Registers");
882
                ln++;
883
 
884 76 dgisselq
                dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
885
                dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
886
                dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
887
                dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
888 2 dgisselq
 
889 76 dgisselq
                dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
890
                dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
891
                dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
892
                dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
893 2 dgisselq
 
894 76 dgisselq
                dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
895
                dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
896
                dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
897
                dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
898 2 dgisselq
 
899 76 dgisselq
                dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
900
                dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
901 2 dgisselq
 
902 76 dgisselq
                if (true) {
903
                        mvprintw(ln,40, "%ssCC : 0x%08x",
904
                                (m_cursor==26)?">":" ", cc);
905
                } else {
906
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
907
                                (m_cursor==26)?">":" ",
908
                                (cc&0x01000)?"FE":"",
909
                                (cc&0x00800)?"DE":"",
910
                                (cc&0x00400)?"BE":"",
911
                                (cc&0x00200)?"TP":"",
912
                                (cc&0x00100)?"IL":"",
913
                                (cc&0x00080)?"BK":"",
914
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
915
                        mvprintw(ln, 54, "%s%s%s%s",
916
                                (cc&8)?"V":" ",
917
                                (cc&4)?"N":" ",
918
                                (cc&2)?"C":" ",
919
                                (cc&1)?"Z":" ");
920
                }
921 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
922 2 dgisselq
                ln++;
923
 
924 34 dgisselq
                if (gie)
925 2 dgisselq
                        attron(A_BOLD);
926
                else
927
                        attroff(A_BOLD);
928 69 dgisselq
                mvprintw(ln, 0, "User Registers");
929
                mvprintw(ln, 42, "DCDR=%02x %s",
930
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
931
                mvprintw(ln, 62, "OPR =%02x %s%s",
932
                        m_core->v__DOT__thecpu__DOT__opR,
933
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
934
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
935
                ln++;
936 76 dgisselq
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
937
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
938
                dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
939
                dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
940 2 dgisselq
 
941 76 dgisselq
                dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
942
                dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
943
                dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
944
                dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
945 2 dgisselq
 
946 76 dgisselq
                dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
947
                dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
948
                dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
949
                dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
950 2 dgisselq
 
951 76 dgisselq
                dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
952
                dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
953
                cc = m_state.m_uR[14];
954
                if (false) {
955
                        mvprintw(ln,40, "%cuCC : 0x%08x",
956
                                (m_cursor == 42)?'>':' ', cc);
957
                } else {
958
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
959
                                (m_cursor == 42)?'>':' ',
960
                                (cc & 0x1000)?"FE":"",
961
                                (cc & 0x0800)?"DE":"",
962
                                (cc & 0x0400)?"BE":"",
963
                                (cc & 0x0200)?"TP":"",
964
                                (cc & 0x0100)?"IL":"",
965
                                (cc & 0x0040)?"ST":"",
966
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
967
                        mvprintw(ln, 54, "%s%s%s%s",
968
                                (cc&8)?"V":" ",
969
                                (cc&4)?"N":" ",
970
                                (cc&2)?"C":" ",
971
                                (cc&1)?"Z":" ");
972
                }
973
                dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
974 2 dgisselq
 
975
                attroff(A_BOLD);
976
                ln+=2;
977
 
978
                ln+=3;
979
 
980
                showins(ln, "I ",
981 69 dgisselq
#ifdef  OPT_PIPELINED
982 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
983 69 dgisselq
#else
984
                        1,
985
#endif
986 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
987
                        m_core->v__DOT__thecpu__DOT__gie,
988
                        0,
989 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
990
                        true); ln++;
991 57 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
992 2 dgisselq
 
993
                showins(ln, "Dc",
994 69 dgisselq
                        dcd_ce(), dcdvalid(),
995 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
996 69 dgisselq
#ifdef  OPT_PIPELINED
997 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
998 69 dgisselq
#else
999
                        0,
1000
#endif
1001 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1002
#ifdef  OPT_VLIW
1003
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
1004
#else
1005
                        false
1006
#endif
1007
                        ); ln++;
1008 2 dgisselq
 
1009
                showins(ln, "Op",
1010 69 dgisselq
                        op_ce(),
1011 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
1012
                        m_core->v__DOT__thecpu__DOT__op_gie,
1013
                        m_core->v__DOT__thecpu__DOT__op_stall,
1014 76 dgisselq
                        op_pc(),
1015
#ifdef  OPT_VLIW
1016
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1017
#else
1018
                        false
1019
#endif
1020
                        ); ln++;
1021 2 dgisselq
 
1022
                showins(ln, "Al",
1023
                        m_core->v__DOT__thecpu__DOT__alu_ce,
1024
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1025
                        m_core->v__DOT__thecpu__DOT__alu_gie,
1026 69 dgisselq
#ifdef  OPT_PIPELINED
1027 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__alu_stall,
1028 69 dgisselq
#else
1029
                        0,
1030
#endif
1031 76 dgisselq
                        alu_pc(),
1032
#ifdef  OPT_VLIW
1033
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1034
#else
1035
                        false
1036
#endif
1037
                        ); ln++;
1038 2 dgisselq
        }
1039 69 dgisselq
 
1040 2 dgisselq
        void    tick(void) {
1041
                int gie = m_core->v__DOT__thecpu__DOT__gie;
1042
                /*
1043
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
1044
                                                m_core->o_qspi_sck,
1045
                                                m_core->o_qspi_dat);
1046
                */
1047
 
1048 11 dgisselq
                int stb = m_core->o_wb_stb;
1049
                if ((m_core->o_wb_addr & (-1<<20))!=1)
1050
                        stb = 0;
1051
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
1052
                        m_core->i_wb_ack = 1;
1053 2 dgisselq
 
1054
                if ((dbg_flag)&&(dbg_fp)) {
1055 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
1056 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
1057
                                (m_core->i_dbg_stb)?"STB":
1058
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
1059
                                ((m_core->i_dbg_we)?"WE":"  "),
1060
                                (m_core->i_dbg_addr),0,
1061
                                m_core->i_dbg_data,
1062
                                (m_core->o_dbg_ack)?"ACK":"   ",
1063
                                (m_core->o_dbg_stall)?"STALL":"     ",
1064
                                (m_core->o_dbg_data),
1065
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
1066
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
1067 69 dgisselq
                                (dcdvalid())?"DCDV ":"",
1068 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
1069
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
1070 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
1071
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
1072 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
1073
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
1074
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
1075
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
1076
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
1077
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
1078
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
1079
                                (m_core->v__DOT__sys_we)?"WE":"  ",
1080
                                (m_core->v__DOT__sys_addr),
1081
                                (m_core->v__DOT__dbg_addr),
1082
                                (m_core->v__DOT__sys_data),
1083
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
1084
                                (m_core->v__DOT__wb_data));
1085
                }
1086
 
1087
                if (dbg_fp)
1088
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
1089 69 dgisselq
                                dcd_ce(),
1090 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
1091 69 dgisselq
                                op_ce(),
1092 39 dgisselq
                                op_pc(),
1093 69 dgisselq
                                dcdA()&0x01f,
1094 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opR,
1095
                                m_core->v__DOT__cmd_halt,
1096
                                m_core->v__DOT__cpu_halt,
1097
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1098
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1099
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1100
                                m_core->v__DOT__thecpu__DOT__alu_reg,
1101
                                m_core->v__DOT__thecpu__DOT__ipc,
1102
                                m_core->v__DOT__thecpu__DOT__upc);
1103
 
1104
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
1105
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
1106 69 dgisselq
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
1107 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1108
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1109
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
1110
                                m_core->v__DOT__cmd_addr,
1111
                                m_core->v__DOT__dbg_idata,
1112
                                m_core->v__DOT__thecpu__DOT__master_ce,
1113
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1114
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1115
                                m_core->v__DOT__thecpu__DOT__mem_valid);
1116
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
1117
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
1118
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1119
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1120
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
1121
                                m_core->v__DOT__cmd_addr,
1122
                                m_core->v__DOT__dbg_idata,
1123
                                m_core->v__DOT__thecpu__DOT__master_ce,
1124
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1125
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1126
                                m_core->v__DOT__thecpu__DOT__mem_valid,
1127
                                m_core->v__DOT__thecpu__DOT__w_iflags,
1128
                                m_core->v__DOT__thecpu__DOT__w_uflags);
1129 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
1130
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1131 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
1132
                                m_core->v__DOT__thecpu__DOT__op_break);
1133 36 dgisselq
                } else if ((dbg_fp)&&
1134
                                ((m_core->v__DOT__thecpu__DOT__op_break)
1135 76 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
1136 36 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
1137
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
1138 76 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
1139 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1140
                                m_core->v__DOT__thecpu__DOT__break_en,
1141
                                m_core->v__DOT__thecpu__DOT__dcd_break,
1142 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__op_break,
1143
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
1144 2 dgisselq
                }
1145
 
1146 34 dgisselq
                if (dbg_fp) {
1147
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
1148
                                fprintf(dbg_fp, "\tClear Pipeline\n");
1149
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
1150
                                fprintf(dbg_fp, "\tNew PC\n");
1151
                }
1152
 
1153 36 dgisselq
                if (dbg_fp)
1154
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
1155
                if (false) {
1156
                        m_core->i_clk = 1;
1157
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1158
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1159
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1160
                        eval();
1161
                        m_core->i_clk = 0;
1162
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1163
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1164
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1165
                        eval();
1166
                        m_tickcount++;
1167
                } else {
1168
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1169
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1170
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1171 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
1172
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
1173
                                m_core->i_wb_err = 1;
1174
                        else
1175
                                m_core->i_wb_err = 0;
1176 36 dgisselq
                        TESTB<Vzipsystem>::tick();
1177
                }
1178 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
1179
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
1180
                                (gie)?"User":"Supervisor",
1181
                                (gie)?"Supervisor":"User",
1182
                                m_core->v__DOT__thecpu__DOT__ipc,
1183
                                m_core->v__DOT__thecpu__DOT__upc,
1184
                                m_core->v__DOT__thecpu__DOT__pf_pc);
1185
                } if (dbg_fp) {
1186 76 dgisselq
#ifdef  OPT_TRADITIONAL_PFCACHE
1187
                        fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
1188 69 dgisselq
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
1189
                                m_core->v__DOT__thecpu__DOT__pf_pc,
1190
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_branch_pc,
1191
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)
1192
                                &&(dcdvalid())
1193
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
1194
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
1195
                                m_core->v__DOT__thecpu__DOT__instruction_pc,
1196
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
1197 76 dgisselq
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
1198
                                (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
1199 69 dgisselq
#endif
1200
                        dbgins("Dc - ",
1201
                                dcd_ce(), dcdvalid(),
1202 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
1203 69 dgisselq
#ifdef  OPT_PIPELINED
1204 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
1205 69 dgisselq
#else
1206
                                0,
1207
#endif
1208 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1209
#ifdef  OPT_VLIW
1210
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
1211
#else
1212
                                false,
1213
#endif
1214
#ifdef  OPT_ILLEGAL_INSTRUCTION
1215
                                m_core->v__DOT__thecpu__DOT__dcd_illegal
1216
#else
1217
                                false
1218
#endif
1219
                                );
1220 69 dgisselq
                        dbgins("Op - ",
1221
                                op_ce(),
1222 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opvalid,
1223
                                m_core->v__DOT__thecpu__DOT__op_gie,
1224
                                m_core->v__DOT__thecpu__DOT__op_stall,
1225 76 dgisselq
                                op_pc(),
1226
#ifdef  OPT_VLIW
1227
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
1228
#else
1229
                                false,
1230 57 dgisselq
#endif
1231 76 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
1232
                                m_core->v__DOT__thecpu__DOT__op_illegal
1233
#else
1234
                                false
1235
#endif
1236
                                );
1237 2 dgisselq
                        dbgins("Al - ",
1238
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1239
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1240
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1241 69 dgisselq
#ifdef  OPT_PIPELINED
1242 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1243 69 dgisselq
#else
1244
                                0,
1245
#endif
1246 76 dgisselq
                                alu_pc(),
1247
#ifdef  OPT_VLIW
1248
                                m_core->v__DOT__thecpu__DOT__r_alu_phase,
1249
#else
1250
                                false,
1251
#endif
1252
#ifdef  OPT_ILLEGAL_INSTRUCTION
1253
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
1254
#else
1255
                                false
1256
#endif
1257
                                );
1258 2 dgisselq
 
1259
                }
1260 58 dgisselq
 
1261
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1262
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
1263
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1264
                        if (m_profile_fp) {
1265
                                unsigned buf[2];
1266
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
1267
                                buf[1] = iticks;
1268
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1269
                        }
1270
                        m_last_instruction_tickcount = m_tickcount;
1271
                }
1272 2 dgisselq
        }
1273
 
1274
        bool    test_success(void) {
1275
                return ((!m_core->v__DOT__thecpu__DOT__gie)
1276
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1277
        }
1278
 
1279 39 dgisselq
        unsigned        op_pc(void) {
1280
                /*
1281
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
1282
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
1283
                        r--;
1284
                return r;
1285
                */
1286
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
1287
        }
1288
 
1289 69 dgisselq
        bool    dcd_ce(void) {
1290
#ifdef  OPT_PIPELINED
1291
                return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
1292
#else
1293
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
1294
#endif
1295
        } bool  dcdvalid(void) {
1296
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
1297
        }
1298
        bool    pfstall(void) {
1299
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1300
                        ||(m_core->v__DOT__cpu_stall));
1301
        }
1302
        unsigned        dcdR(void) {
1303
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1304
        }
1305
        unsigned        dcdA(void) {
1306
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1307
        }
1308
        unsigned        dcdB(void) {
1309
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1310
        }
1311
 
1312
        bool    op_ce(void) {
1313
#ifdef  OPT_PIPELINED
1314
                return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
1315
#else
1316
                // return (dcdvalid())&&(opvalid())
1317
                //      &&(m_core->v__DOT__thecpu__DOT__op_stall);
1318
                return  dcdvalid();
1319
#endif
1320
        } bool  opvalid(void) {
1321
                return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
1322
        }
1323
 
1324 58 dgisselq
        bool    mem_busy(void) {
1325
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1326 69 dgisselq
#ifdef  OPT_PIPELINED
1327 58 dgisselq
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1328 69 dgisselq
#else
1329
                return 0;
1330
#endif
1331 58 dgisselq
        }
1332
 
1333
        bool    mem_stalled(void) {
1334
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1335
 
1336
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1337
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1338
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
1339
 
1340 69 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
1341
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1342
                a = mem_pipe_stalled();
1343
                b = (!m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
1344
#else
1345
                a = false;
1346
                b = false;
1347
#endif
1348 58 dgisselq
                d = ((wr_write_pc)||(wr_write_cc));
1349
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1350 69 dgisselq
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1351 58 dgisselq
                        &&d);
1352
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
1353
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1354
        }
1355
 
1356 39 dgisselq
        unsigned        alu_pc(void) {
1357
                /*
1358
                unsigned        r = op_pc();
1359
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1360
                        r--;
1361
                return r;
1362
                */
1363
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
1364
        }
1365
 
1366
#ifdef  OPT_PIPELINED_BUS_ACCESS
1367 69 dgisselq
        bool    mem_pipe_stalled(void) {
1368 39 dgisselq
                int     r = 0;
1369
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
1370
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1371
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1372
                        ||(
1373
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1374
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1375
                return r;
1376
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1377
        }
1378
#endif
1379
 
1380 2 dgisselq
        bool    test_failure(void) {
1381 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1382
                        return 0;
1383
                else if (m_core->v__DOT__thecpu__DOT__gie)
1384 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
1385 43 dgisselq
                else
1386 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
1387 43 dgisselq
                /*
1388 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1389 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1390 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1391 43 dgisselq
                */
1392 2 dgisselq
        }
1393
 
1394
        void    wb_write(unsigned a, unsigned int v) {
1395 36 dgisselq
                int     errcount = 0;
1396 2 dgisselq
                mvprintw(0,35, "%40s", "");
1397
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1398
                m_core->i_dbg_cyc = 1;
1399
                m_core->i_dbg_stb = 1;
1400
                m_core->i_dbg_we  = 1;
1401
                m_core->i_dbg_addr = a & 1;
1402
                m_core->i_dbg_data = v;
1403
 
1404
                tick();
1405 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1406 2 dgisselq
                        tick();
1407
 
1408
                m_core->i_dbg_stb = 0;
1409 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1410 2 dgisselq
                        tick();
1411
 
1412
                // Release the bus
1413
                m_core->i_dbg_cyc = 0;
1414
                m_core->i_dbg_stb = 0;
1415
                tick();
1416
                mvprintw(0,35, "%40s", "");
1417
                mvprintw(0,40, "wb_write -- complete");
1418 36 dgisselq
 
1419
 
1420
                if (errcount >= 100)
1421
                        bomb = true;
1422 2 dgisselq
        }
1423
 
1424
        unsigned long   wb_read(unsigned a) {
1425
                unsigned int    v;
1426 36 dgisselq
                int     errcount = 0;
1427 2 dgisselq
                mvprintw(0,35, "%40s", "");
1428
                mvprintw(0,40, "wb_read(0x%08x)", a);
1429
                m_core->i_dbg_cyc = 1;
1430
                m_core->i_dbg_stb = 1;
1431
                m_core->i_dbg_we  = 0;
1432
                m_core->i_dbg_addr = a & 1;
1433
 
1434
                tick();
1435 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1436 2 dgisselq
                        tick();
1437
 
1438
                m_core->i_dbg_stb = 0;
1439 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1440 2 dgisselq
                        tick();
1441
                v = m_core->o_dbg_data;
1442
 
1443
                // Release the bus
1444
                m_core->i_dbg_cyc = 0;
1445
                m_core->i_dbg_stb = 0;
1446
                tick();
1447
 
1448
                mvprintw(0,35, "%40s", "");
1449
                mvprintw(0,40, "wb_read = 0x%08x", v);
1450
 
1451 36 dgisselq
                if (errcount >= 100)
1452
                        bomb = true;
1453 2 dgisselq
                return v;
1454
        }
1455
 
1456 34 dgisselq
        void    cursor_up(void) {
1457
                if (m_cursor > 3)
1458
                        m_cursor -= 4;
1459
        } void  cursor_down(void) {
1460
                if (m_cursor < 40)
1461
                        m_cursor += 4;
1462
        } void  cursor_left(void) {
1463
                if (m_cursor > 0)
1464
                        m_cursor--;
1465
                else    m_cursor = 43;
1466
        } void  cursor_right(void) {
1467
                if (m_cursor < 43)
1468
                        m_cursor++;
1469
                else    m_cursor = 0;
1470
        }
1471
 
1472
        int     cursor(void) { return m_cursor; }
1473 2 dgisselq
};
1474
 
1475 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1476
        int     wy, wx, ra;
1477
        int     c = tb->cursor();
1478
 
1479
        wx = (c & 0x03) * 20 + 9;
1480
        wy = (c>>2);
1481
        if (wy >= 3+4)
1482
                wy++;
1483
        if (wy > 3)
1484
                wy += 2;
1485
        wy++;
1486
 
1487
        if (c >= 12)
1488
                ra = c - 12;
1489
        else
1490
                ra = c + 32;
1491
 
1492
        bool    done = false;
1493
        char    str[16];
1494
        int     pos = 0; str[pos] = '\0';
1495
        while(!done) {
1496
                int     chv = getch();
1497
                switch(chv) {
1498
                case KEY_ESCAPE:
1499
                        pos = 0; str[pos] = '\0'; done = true;
1500
                        break;
1501
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1502
                        done = true;
1503
                        break;
1504
                case KEY_LEFT: case KEY_BACKSPACE:
1505
                        if (pos > 0) pos--;
1506
                        break;
1507 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1508 34 dgisselq
                case KEY_CLEAR:
1509
                        pos = 0;
1510
                        break;
1511
                case '0': case ' ': str[pos++] = '0'; break;
1512
                case '1': str[pos++] = '1'; break;
1513
                case '2': str[pos++] = '2'; break;
1514
                case '3': str[pos++] = '3'; break;
1515
                case '4': str[pos++] = '4'; break;
1516
                case '5': str[pos++] = '5'; break;
1517
                case '6': str[pos++] = '6'; break;
1518
                case '7': str[pos++] = '7'; break;
1519
                case '8': str[pos++] = '8'; break;
1520
                case '9': str[pos++] = '9'; break;
1521
                case 'A': case 'a': str[pos++] = 'A'; break;
1522
                case 'B': case 'b': str[pos++] = 'B'; break;
1523
                case 'C': case 'c': str[pos++] = 'C'; break;
1524
                case 'D': case 'd': str[pos++] = 'D'; break;
1525
                case 'E': case 'e': str[pos++] = 'E'; break;
1526
                case 'F': case 'f': str[pos++] = 'F'; break;
1527
                }
1528
 
1529
                if (pos > 8)
1530
                        pos = 8;
1531
                str[pos] = '\0';
1532
 
1533
                attron(A_NORMAL | A_UNDERLINE);
1534
                mvprintw(wy, wx, "%-8s", str);
1535
                if (pos > 0) {
1536
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1537
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1538
                }
1539
                attrset(A_NORMAL);
1540
        }
1541
 
1542
        if (pos > 0) {
1543
                int     v;
1544
                v = strtoul(str, NULL, 16);
1545
                if (!tb->halted()) {
1546
                        switch(ra) {
1547
                        case 15:
1548
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1549
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1550
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1551
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1552
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1553
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1554 69 dgisselq
#ifdef  OPT_PIPELINED
1555 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1556 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1557
#endif
1558 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1559
                                }
1560
                                break;
1561
                        case 31:
1562
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1563
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1564
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1565
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1566
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1567
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1568 69 dgisselq
#ifdef  OPT_PIPELINED
1569 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1570 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1571
#endif
1572 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1573
                                }
1574
                                break;
1575
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1576
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1577 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1578 69 dgisselq
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1579 34 dgisselq
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1580
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1581
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1582
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1583
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1584
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1585
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1586
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1587
                        default:
1588
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1589
                                break;
1590
                        }
1591
                } else
1592
                        tb->cmd_write(ra, v);
1593
        }
1594
}
1595
 
1596 27 dgisselq
void    usage(void) {
1597
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1598
        printf("\n");
1599
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1600
        printf("\t-a\tSets the testbench to run automatically without any\n");
1601
        printf("\t\tuser interaction.\n");
1602
        printf("\n");
1603
        printf("\tUser Commands:\n");
1604
        printf("\t\tWhen the test bench is run interactively, the following\n");
1605
        printf("\t\tkey strokes are recognized:\n");
1606
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1607
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1608
        printf("\t\t\tuser intervention.\n");
1609
        printf("\t\t\'q\'\tQuit the simulation.\n");
1610
        printf("\t\t\'r\'\tReset the processor.\n");
1611
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1612
        printf("\t\t\tThis may consume more than one tick.\n");
1613
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1614
}
1615 2 dgisselq
 
1616 43 dgisselq
bool    signalled = false;
1617
 
1618
void    sigint(int v) {
1619
        signalled = true;
1620
}
1621
 
1622 2 dgisselq
int     main(int argc, char **argv) {
1623
        Verilated::commandArgs(argc, argv);
1624
        ZIPPY_TB        *tb = new ZIPPY_TB();
1625 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1626 2 dgisselq
 
1627
        // mem[0x00000] = 0xbe000010; // Halt instruction
1628
        unsigned int mptr = 0;
1629
 
1630 43 dgisselq
        signal(SIGINT, sigint);
1631
 
1632 9 dgisselq
        if (argc <= 1) {
1633 27 dgisselq
                usage();
1634
                exit(-1);
1635 9 dgisselq
        } else {
1636
                for(int argn=1; argn<argc; argn++) {
1637 27 dgisselq
                        if (argv[argn][0] == '-') {
1638
                                switch(argv[argn][1]) {
1639
                                case 'a':
1640
                                        autorun = true;
1641
                                        break;
1642
                                case 'e':
1643
                                        exit_on_done = true;
1644
                                        break;
1645
                                case 'h':
1646
                                        usage();
1647
                                        exit(0);
1648
                                        break;
1649 36 dgisselq
                                case 's':
1650
                                        autostep = true;
1651
                                        break;
1652 27 dgisselq
                                default:
1653
                                        usage();
1654
                                        exit(-1);
1655
                                        break;
1656
                                }
1657
                        } else if (access(argv[argn], R_OK)==0) {
1658 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1659 58 dgisselq
                                int     nr, nv = 0;
1660 9 dgisselq
                                if (fp == NULL) {
1661
                                        printf("Cannot open %s\n", argv[argn]);
1662
                                        perror("O/S Err: ");
1663
                                        exit(-1);
1664 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1665 9 dgisselq
                                fclose(fp);
1666 58 dgisselq
                                mptr+= nr;
1667
                                if (nr == 0) {
1668
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
1669
                                        perror("O/S  Err?:");
1670
                                        exit(-2);
1671
                                } for(int i=0; i<nr; i++) {
1672
                                        if (tb->m_mem[mptr-nr+i])
1673
                                                nv++;
1674
                                } if (nv == 0) {
1675
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
1676
                                        perror("O/S  Err?:");
1677
                                        exit(-2);
1678
                                }
1679
                        } else {
1680
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
1681
                                exit(-2);
1682 9 dgisselq
                        }
1683
                }
1684
        }
1685
 
1686 58 dgisselq
 
1687
        assert(mptr > 0);
1688
 
1689 27 dgisselq
        if (autorun) {
1690
                bool    done = false;
1691 2 dgisselq
 
1692 27 dgisselq
                printf("Running in non-interactive mode\n");
1693
                tb->reset();
1694
                for(int i=0; i<2; i++)
1695
                        tb->tick();
1696
                tb->m_core->v__DOT__cmd_halt = 0;
1697
                while(!done) {
1698
                        tb->tick();
1699
 
1700
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1701
                                // tb->m_core->v__DOT__cmd_halt = 0;
1702
                                // tb->m_core->v__DOT__cmd_step = 0;
1703
 
1704 34 dgisselq
                        /*
1705 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1706
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1707
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1708
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1709 34 dgisselq
                        */
1710 27 dgisselq
 
1711
                        done = (tb->test_success())||(tb->test_failure());
1712 43 dgisselq
                        done = done || signalled;
1713 27 dgisselq
                }
1714 36 dgisselq
        } else if (autostep) {
1715
                bool    done = false;
1716
 
1717
                printf("Running in non-interactive mode, via step commands\n");
1718
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1719
                while(!done) {
1720
                        tb->wb_write(CMD_REG, CMD_STEP);
1721
                        done = (tb->test_success())||(tb->test_failure());
1722 43 dgisselq
                        done = done || signalled;
1723 36 dgisselq
                }
1724 27 dgisselq
        } else { // Interactive
1725
                initscr();
1726
                raw();
1727
                noecho();
1728
                keypad(stdscr, true);
1729
 
1730 69 dgisselq
                // tb->reset();
1731
                // for(int i=0; i<2; i++)
1732
                        // tb->tick();
1733
                tb->m_core->v__DOT__cmd_reset = 1;
1734 27 dgisselq
                tb->m_core->v__DOT__cmd_halt = 0;
1735
 
1736 76 dgisselq
                /*
1737
                // For debugging purposes: do we wish to skip some number of
1738
                // instructions to fast forward to a time of interest??
1739
                for(int i=0; i<0x4d0; i++) {
1740
                        tb->m_core->v__DOT__cmd_halt = 0;
1741
                        tb->tick();
1742
                }
1743
                */
1744
 
1745 27 dgisselq
                int     chv = 'q';
1746
 
1747 43 dgisselq
                bool    done = false, halted = true, manual = true,
1748
                        high_speed = false;
1749 2 dgisselq
 
1750
                halfdelay(1);
1751 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1752 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1753
                        // tb->show_state();
1754
 
1755
                while(!done) {
1756 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1757 87 dgisselq
                                // chv = getch();
1758
 
1759 43 dgisselq
                                struct  pollfd  fds[1];
1760
                                fds[0].fd = STDIN_FILENO;
1761
                                fds[0].events = POLLIN;
1762 87 dgisselq
 
1763 43 dgisselq
                                if (poll(fds, 1, 0) > 0)
1764
                                        chv = getch();
1765
                                else
1766
                                        chv = ERR;
1767 87 dgisselq
 
1768 43 dgisselq
                        } else {
1769
                                chv = getch();
1770
                        }
1771 2 dgisselq
                        switch(chv) {
1772
                        case 'h': case 'H':
1773
                                tb->wb_write(CMD_REG, CMD_HALT);
1774
                                if (!halted)
1775
                                        erase();
1776
                                halted = true;
1777
                                break;
1778 43 dgisselq
                        case 'G':
1779
                                high_speed = true;
1780 87 dgisselq
                                // cbreak();
1781 43 dgisselq
                        case 'g':
1782 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1783
                                if (halted)
1784
                                        erase();
1785
                                halted = false;
1786
                                manual = false;
1787
                                break;
1788 43 dgisselq
                        case 'm':
1789
                                tb->show_user_timers(false);
1790
                                break;
1791 2 dgisselq
                        case 'q': case 'Q':
1792
                                done = true;
1793
                                break;
1794
                        case 'r': case 'R':
1795 36 dgisselq
                                if (manual)
1796
                                        tb->reset();
1797
                                else
1798
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1799 2 dgisselq
                                halted = true;
1800
                                erase();
1801
                                break;
1802 39 dgisselq
                        case 's':
1803 34 dgisselq
                                if (!halted)
1804 27 dgisselq
                                        erase();
1805 76 dgisselq
                                tb->step();
1806 2 dgisselq
                                manual = false;
1807 34 dgisselq
                                halted = true;
1808 87 dgisselq
                                // if (high_speed)
1809
                                        // halfdelay(1);
1810 43 dgisselq
                                high_speed = false;
1811 2 dgisselq
                                break;
1812 39 dgisselq
                        case 'S':
1813 34 dgisselq
                                if ((!manual)||(halted))
1814 27 dgisselq
                                        erase();
1815 2 dgisselq
                                manual = true;
1816 39 dgisselq
                                halted = true;
1817 87 dgisselq
                                // if (high_speed)
1818
                                        // halfdelay(1);
1819 43 dgisselq
                                high_speed = false;
1820 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1821
                                tb->m_core->v__DOT__cmd_step = 1;
1822
                                tb->eval();
1823
                                tb->tick();
1824
                                break;
1825
                        case 'T': // 
1826
                                if ((!manual)||(halted))
1827
                                        erase();
1828
                                manual = true;
1829
                                halted = true;
1830 87 dgisselq
                                // if (high_speed)
1831
                                        // halfdelay(1);
1832 43 dgisselq
                                high_speed = false;
1833 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1834
                                tb->m_core->v__DOT__cmd_step = 0;
1835
                                tb->eval();
1836
                                tb->tick();
1837
                                break;
1838
                        case 't':
1839
                                if ((!manual)||(halted))
1840
                                        erase();
1841
                                manual = true;
1842 34 dgisselq
                                halted = false;
1843 87 dgisselq
                                // if (high_speed)
1844
                                        // halfdelay(1);
1845 43 dgisselq
                                high_speed = false;
1846 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1847 76 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1848 27 dgisselq
                //              tb->m_core->v__DOT__cmd_step = 0;
1849 2 dgisselq
                                tb->tick();
1850
                                break;
1851 43 dgisselq
                        case 'u':
1852
                                tb->show_user_timers(true);
1853
                                break;
1854 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1855
                                get_value(tb);
1856
                                break;
1857
                        case    KEY_UP:         tb->cursor_up();        break;
1858
                        case    KEY_DOWN:       tb->cursor_down();      break;
1859
                        case    KEY_LEFT:       tb->cursor_left();      break;
1860
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1861 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1862 34 dgisselq
                        case ERR: case KEY_CLEAR:
1863 2 dgisselq
                        default:
1864
                                if (!manual)
1865
                                        tb->tick();
1866
                        }
1867
 
1868
                        if (manual) {
1869
                                tb->show_state();
1870
                        } else if (halted) {
1871
                                if (tb->dbg_fp)
1872
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1873
                                tb->read_state();
1874
                        } else
1875
                                tb->show_state();
1876
 
1877
                        if (tb->m_core->i_rst)
1878
                                done =true;
1879 43 dgisselq
                        if ((tb->bomb)||(signalled))
1880 2 dgisselq
                                done = true;
1881 27 dgisselq
 
1882
                        if (exit_on_done) {
1883
                                if (tb->test_success())
1884
                                        done = true;
1885
                                if (tb->test_failure())
1886
                                        done = true;
1887
                        }
1888 2 dgisselq
                }
1889 27 dgisselq
                endwin();
1890
        }
1891
#ifdef  MANUAL_STEPPING_MODE
1892
         else { // Manual stepping mode
1893 2 dgisselq
                tb->show_state();
1894
 
1895
                while('q' != tolower(chv = getch())) {
1896
                        tb->tick();
1897
                        tb->show_state();
1898
 
1899
                        if (tb->test_success())
1900
                                break;
1901
                        else if (tb->test_failure())
1902
                                break;
1903 43 dgisselq
                        else if (signalled)
1904
                                break;
1905 2 dgisselq
                }
1906
        }
1907 27 dgisselq
#endif
1908 2 dgisselq
 
1909 43 dgisselq
        printf("\n");
1910 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1911
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1912 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1913 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1914
                printf("Instructions / Clock: %.2f\n",
1915
                        (double)tb->m_core->v__DOT__mic_data
1916
                        / (double)tb->m_core->v__DOT__mtc_data);
1917 36 dgisselq
 
1918
        int     rcode = 0;
1919
        if (tb->bomb) {
1920
                printf("TEST BOMBED\n");
1921
                rcode = -1;
1922
        } else if (tb->test_success()) {
1923 2 dgisselq
                printf("SUCCESS!\n");
1924 36 dgisselq
        } else if (tb->test_failure()) {
1925
                rcode = -2;
1926 2 dgisselq
                printf("TEST FAILED!\n");
1927 36 dgisselq
        } else
1928 27 dgisselq
                printf("User quit\n");
1929 43 dgisselq
        delete tb;
1930 36 dgisselq
        exit(rcode);
1931 2 dgisselq
}
1932
 

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