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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 9

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 2 dgisselq
 
41
#include <ctype.h>
42
#include <ncurses.h>
43
 
44
#include "verilated.h"
45
#include "Vzipsystem.h"
46
 
47
#include "testb.h"
48
// #include "twoc.h"
49
// #include "qspiflashsim.h"
50
#include "memsim.h"
51
#include "zopcodes.h"
52
#include "zparser.h"
53
 
54
#define CMD_REG         0
55
#define CMD_DATA        1
56
#define CMD_HALT        (1<<10)
57
#define CMD_STALL       (1<<9)
58
#define CMD_STEP        (1<<8)
59
#define CMD_INT         (1<<7)
60
#define CMD_RESET       (1<<6)
61
 
62
 
63
// No particular "parameters" need definition or redefinition here.
64
class   ZIPPY_TB : public TESTB<Vzipsystem> {
65
public:
66 9 dgisselq
        unsigned long   m_mem_size;
67 2 dgisselq
        MEMSIM          m_mem;
68
        // QSPIFLASHSIM m_flash;
69
        FILE            *dbg_fp;
70
        bool            dbg_flag, bomb;
71
 
72 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
73 2 dgisselq
                //dbg_fp = fopen("dbg.txt", "w");
74
                dbg_fp = NULL;
75
                dbg_flag = false;
76
                bomb = false;
77
        }
78
 
79
        void    reset(void) {
80
                // m_flash.debug(false);
81
                TESTB<Vzipsystem>::reset();
82
        }
83
 
84
        bool    on_tick(void) {
85
                tick();
86
                return true;
87
        }
88
 
89
        void    showval(int y, int x, const char *lbl, unsigned int v) {
90
                mvprintw(y,x, "%s: 0x%08x", lbl, v);
91
        }
92
 
93
        void    dispreg(int y, int x, const char *n, unsigned int v) {
94
                // 4,4,8,1 = 17 of 20, +3 = 19
95
                mvprintw(y, x, "%s: 0x%08x", n, v);
96
        }
97
 
98
        void    showreg(int y, int x, const char *n, int r) {
99
                // 4,4,8,1 = 17 of 20, +3 = 19
100
                mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
101
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
102
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
103
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
104
                        ?'a':' ');
105
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
106
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
107
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
108
                        ?'b':' ');
109
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
110
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
111
                        ?'W':' ');
112
        }
113
 
114
        void    showins(int y, const char *lbl, const int ce, const int valid,
115
                        const int gie, const int stall, const unsigned int pc) {
116
                char    line[80];
117
 
118
                if (ce)
119
                        mvprintw(y, 0, "Ck ");
120
                else
121
                        mvprintw(y, 0, "   ");
122
                if (stall)
123
                        printw("Stl ");
124
                else
125
                        printw("    ");
126
                printw("%s: 0x%08x", lbl, pc);
127
 
128
                if (valid) {
129
                        if (gie) attroff(A_BOLD);
130
                        else    attron(A_BOLD);
131
                        zipi_to_string(m_mem[pc], line);
132
                        printw("  %-20s", &line[1]);
133
                } else {
134
                        attroff(A_BOLD);
135
                        printw("  (0x%08x)%28s", m_mem[pc],"");
136
                }
137
                attroff(A_BOLD);
138
        }
139
 
140
        void    dbgins(const char *lbl, const int ce, const int valid,
141
                        const int gie, const int stall, const unsigned int pc) {
142
                char    line[80];
143
 
144
                if (!dbg_fp)
145
                        return;
146
 
147
                if (ce)
148
                        fprintf(dbg_fp, "%s Ck ", lbl);
149
                else
150
                        fprintf(dbg_fp, "%s    ", lbl);
151
                if (stall)
152
                        fprintf(dbg_fp, "Stl ");
153
                else
154
                        fprintf(dbg_fp, "    ");
155
                fprintf(dbg_fp, "0x%08x:  ", pc);
156
 
157
                if (valid) {
158
                        zipi_to_string(m_mem[pc], line);
159
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
160
                } else {
161
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
162
                }
163
        }
164
 
165
        void    show_state(void) {
166
                int     ln= 0;
167
 
168
                mvprintw(ln,0, "Peripherals-SS"); ln++;
169
                /*
170
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
171
                        mvprintw(ln, 17, "%s%s",
172
                                ((m_core->v__DOT__sys_cyc)
173
                                &&(m_core->v__DOT__sys_we)
174
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
175
                                (m_core->v__DOT__trap_int)?"I":" ");
176
                */
177
                showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
178
                showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
179
                showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
180
                showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
181
 
182
                ln++;
183
                showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
184
                showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
185
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
186
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
187
 
188
                ln++;
189
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
190 9 dgisselq
                showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
191 2 dgisselq
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
192 9 dgisselq
                showval(ln,61, "UICT", m_core->v__DOT__uic_data);
193 2 dgisselq
 
194
                ln++;
195
                mvprintw(ln, 40, "%s %s",
196
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
197
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
198
                mvprintw(ln, 40, "%s %s %s 0x%02x",
199
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
200
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
201
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
202
                        (m_core->v__DOT__cmd_addr)&0x3f);
203
                if (m_core->v__DOT__thecpu__DOT__gie)
204
                        attroff(A_BOLD);
205
                else
206
                        attron(A_BOLD);
207
                mvprintw(ln, 0, "Supervisor Registers");
208
                ln++;
209
 
210
                showreg(ln, 1, "sR0 ", 0);
211
                showreg(ln,21, "sR1 ", 1);
212
                showreg(ln,41, "sR2 ", 2);
213
                showreg(ln,61, "sR3 ", 3); ln++;
214
 
215
                showreg(ln, 1, "sR4 ", 4);
216
                showreg(ln,21, "sR5 ", 5);
217
                showreg(ln,41, "sR6 ", 6);
218
                showreg(ln,61, "sR7 ", 7); ln++;
219
 
220
                showreg(ln, 1, "sR8 ",  8);
221
                showreg(ln,21, "sR9 ",  9);
222
                showreg(ln,41, "sR10", 10);
223
                showreg(ln,61, "sR11", 11); ln++;
224
 
225
                showreg(ln, 1, "sR12", 12);
226
                showreg(ln,21, "sSP ", 13);
227
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
228
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
229
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":"   ",
230
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":"   ",
231
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
232
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
233
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
234
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
235
                mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
236
                ln++;
237
 
238
                if (m_core->v__DOT__thecpu__DOT__gie)
239
                        attron(A_BOLD);
240
                else
241
                        attroff(A_BOLD);
242
                mvprintw(ln, 0, "User Registers"); ln++;
243
                showreg(ln, 1, "uR0 ", 16);
244
                showreg(ln,21, "uR1 ", 17);
245
                showreg(ln,41, "uR2 ", 18);
246
                showreg(ln,61, "uR3 ", 19); ln++;
247
 
248
                showreg(ln, 1, "uR4 ", 20);
249
                showreg(ln,21, "uR5 ", 21);
250
                showreg(ln,41, "uR6 ", 22);
251
                showreg(ln,61, "uR7 ", 23); ln++;
252
 
253
                showreg(ln, 1, "uR8 ", 24);
254
                showreg(ln,21, "uR9 ", 25);
255
                showreg(ln,41, "uR10", 26);
256
                showreg(ln,61, "uR11", 27); ln++;
257
 
258
                showreg(ln, 1, "uR12", 28);
259
                showreg(ln,21, "uSP ", 29);
260
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
261
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
262
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":"   ",
263
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":"   ",
264
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
265
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
266
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
267
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
268
                mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
269
 
270
                attroff(A_BOLD);
271
                ln+=1;
272
 
273 4 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
274 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
275
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
276
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
277
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
278 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
279
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
280 2 dgisselq
                ln++;
281
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
282
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
283
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
284
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
285
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
286
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
287
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
288
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
289
                        (m_core->v__DOT__wb_data)); ln++;
290
 
291
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
292
                        (m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":"   ",
293
                        (m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":"   ",
294
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
295
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
296
                        (m_core->v__DOT__thecpu__DOT__mem_data),
297
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
298
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
299
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
300
 
301
                mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
302
                        (m_core->o_wb_cyc)?"CYC":"   ",
303
                        (m_core->o_wb_stb)?"STB":"   ",
304
                        (m_core->o_wb_we )?"WE":"  ",
305
                        (m_core->o_wb_addr),
306
                        (m_core->o_wb_data),
307
                        (m_core->i_wb_ack)?"ACK":"   ",
308
                        (m_core->i_wb_stall)?"STL":"   ",
309
                        (m_core->i_wb_data)); ln+=2;
310
 
311
                showins(ln, "I ",
312
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
313
                        m_core->v__DOT__thecpu__DOT__pf_valid,
314
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
315
                        m_core->v__DOT__thecpu__DOT__gie,
316
                        0,
317
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
318
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
319
 
320
                showins(ln, "Dc",
321
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
322
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
323
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
324
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
325
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
326
 
327
                showins(ln, "Op",
328
                        m_core->v__DOT__thecpu__DOT__op_ce,
329
                        m_core->v__DOT__thecpu__DOT__opvalid,
330
                        m_core->v__DOT__thecpu__DOT__op_gie,
331
                        m_core->v__DOT__thecpu__DOT__op_stall,
332
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
333
 
334
                showins(ln, "Al",
335
                        m_core->v__DOT__thecpu__DOT__alu_ce,
336
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
337
                        m_core->v__DOT__thecpu__DOT__alu_gie,
338
                        m_core->v__DOT__thecpu__DOT__alu_stall,
339
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
340
 
341
                mvprintw(ln-4, 48,
342
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
343
                printw("(%s:%02x,%x)",
344
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
345
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
346
                        (m_core->v__DOT__thecpu__DOT__op_gie)
347
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
348
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
349
 
350
                printw("(%s%s%s:%02x)",
351
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
352
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
353
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
354
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
355
                /*
356
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
357
                        m_core->v__DOT__thecpu__DOT__dcdI);
358
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
359
                        m_core->v__DOT__thecpu__DOT__opB);
360
                */
361
                mvprintw(ln-3, 48, "Op(%x)%8x %8x->%08x",
362
                        m_core->v__DOT__thecpu__DOT__opn,
363
                        m_core->v__DOT__thecpu__DOT__opA,
364
                        m_core->v__DOT__thecpu__DOT__opB,
365
                        m_core->v__DOT__thecpu__DOT__alu_result);
366
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
367
                        (m_core->v__DOT__thecpu__DOT__opM)?"M":" ",
368
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
369
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
370
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
371
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
372
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
373
        }
374
 
375
        unsigned int    cmd_read(unsigned int a) {
376
                if (dbg_fp) {
377
                        dbg_flag= true;
378
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
379
                }
380
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
381
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
382
                        ;
383
                unsigned int v = wb_read(CMD_DATA);
384
 
385
                if (dbg_flag)
386
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
387
                                v);
388
                dbg_flag = false;
389
                return v;
390
        }
391
 
392
        void    read_state(void) {
393
                int     ln= 0;
394
 
395
                mvprintw(ln,0, "Peripherals-RS"); ln++;
396
                showval(ln, 1, "PIC ", cmd_read(32+ 0));
397
                showval(ln,21, "WDT ", cmd_read(32+ 1));
398
                showval(ln,41, "CACH", cmd_read(32+ 2));
399
                showval(ln,61, "PIC2", cmd_read(32+ 3));
400
                ln++;
401
                showval(ln, 1, "TMRA", cmd_read(32+ 4));
402
                showval(ln,21, "TMRB", cmd_read(32+ 5));
403
                showval(ln,41, "TMRC", cmd_read(32+ 6));
404
                showval(ln,61, "JIF ", cmd_read(32+ 7));
405
 
406
                ln++;
407
                showval(ln, 1, "UTSK", cmd_read(32+12));
408
                showval(ln,21, "UMST", cmd_read(32+13));
409
                showval(ln,41, "UPST", cmd_read(32+14));
410
                showval(ln,61, "UAST", cmd_read(32+15));
411
 
412
                ln++;
413
                ln++;
414
                unsigned int cc = cmd_read(14);
415
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
416
                        m_core->v__DOT__thecpu__DOT__gie);
417
                if (cc & 0x020)
418
                        attroff(A_BOLD);
419
                else
420
                        attron(A_BOLD);
421
                mvprintw(ln, 0, "Supervisor Registers");
422
                ln++;
423
 
424
                dispreg(ln, 1, "sR0 ", cmd_read(0));
425
                dispreg(ln,21, "sR1 ", cmd_read(1));
426
                dispreg(ln,41, "sR2 ", cmd_read(2));
427
                dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
428
 
429
                dispreg(ln, 1, "sR4 ", cmd_read(4));
430
                dispreg(ln,21, "sR5 ", cmd_read(5));
431
                dispreg(ln,41, "sR6 ", cmd_read(6));
432
                dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
433
 
434
                dispreg(ln, 1, "sR8 ", cmd_read( 8));
435
                dispreg(ln,21, "sR9 ", cmd_read( 9));
436
                dispreg(ln,41, "sR10", cmd_read(10));
437
                dispreg(ln,61, "sR11", cmd_read(11)); ln++;
438
 
439
                dispreg(ln, 1, "sR12", cmd_read(12));
440
                dispreg(ln,21, "sSP ", cmd_read(13));
441
 
442
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
443
                        (cc & 0x040)?"STP":"   ",
444
                        (cc & 0x020)?"GIE":"   ",
445
                        (cc & 0x010)?"SLP":"   ",
446
                        (cc&8)?"V":" ",
447
                        (cc&4)?"N":" ",
448
                        (cc&2)?"C":" ",
449
                        (cc&1)?"Z":" ");
450
                mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
451
                ln++;
452
 
453
                if (cc & 0x020)
454
                        attron(A_BOLD);
455
                else
456
                        attroff(A_BOLD);
457
                mvprintw(ln, 0, "User Registers"); ln++;
458
                dispreg(ln, 1, "uR0 ", cmd_read(16));
459
                dispreg(ln,21, "uR1 ", cmd_read(17));
460
                dispreg(ln,41, "uR2 ", cmd_read(18));
461
                dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
462
 
463
                dispreg(ln, 1, "uR4 ", cmd_read(20));
464
                dispreg(ln,21, "uR5 ", cmd_read(21));
465
                dispreg(ln,41, "uR6 ", cmd_read(22));
466
                dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
467
 
468
                dispreg(ln, 1, "uR8 ", cmd_read(24));
469
                dispreg(ln,21, "uR9 ", cmd_read(25));
470
                dispreg(ln,41, "uR10", cmd_read(26));
471
                dispreg(ln,61, "uR11", cmd_read(27)); ln++;
472
 
473
                dispreg(ln, 1, "uR12", cmd_read(28));
474
                dispreg(ln,21, "uSP ", cmd_read(29));
475
                cc = cmd_read(30);
476
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
477
                        (cc&0x040)?"STP":"   ",
478
                        (cc&0x020)?"GIE":"   ",
479
                        (cc&0x010)?"SLP":"   ",
480
                        (cc&8)?"V":" ",
481
                        (cc&4)?"N":" ",
482
                        (cc&2)?"C":" ",
483
                        (cc&1)?"Z":" ");
484
                mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
485
 
486
                attroff(A_BOLD);
487
                ln+=2;
488
 
489
                ln+=3;
490
 
491
                showins(ln, "I ",
492
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
493
                        m_core->v__DOT__thecpu__DOT__pf_valid,
494
                        m_core->v__DOT__thecpu__DOT__gie,
495
                        0,
496
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
497
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
498
 
499
                showins(ln, "Dc",
500
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
501
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
502
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
503
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
504
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
505
 
506
                showins(ln, "Op",
507
                        m_core->v__DOT__thecpu__DOT__op_ce,
508
                        m_core->v__DOT__thecpu__DOT__opvalid,
509
                        m_core->v__DOT__thecpu__DOT__op_gie,
510
                        m_core->v__DOT__thecpu__DOT__op_stall,
511
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
512
 
513
                showins(ln, "Al",
514
                        m_core->v__DOT__thecpu__DOT__alu_ce,
515
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
516
                        m_core->v__DOT__thecpu__DOT__alu_gie,
517
                        m_core->v__DOT__thecpu__DOT__alu_stall,
518
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
519
        }
520
        void    tick(void) {
521
                int gie = m_core->v__DOT__thecpu__DOT__gie;
522
                /*
523
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
524
                                                m_core->o_qspi_sck,
525
                                                m_core->o_qspi_dat);
526
                */
527
 
528
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
529
                        m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
530
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
531
 
532
                if ((dbg_flag)&&(dbg_fp)) {
533
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
534
                                (m_core->i_dbg_cyc)?"CYC":"   ",
535
                                (m_core->i_dbg_stb)?"STB":
536
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
537
                                ((m_core->i_dbg_we)?"WE":"  "),
538
                                (m_core->i_dbg_addr),0,
539
                                m_core->i_dbg_data,
540
                                (m_core->o_dbg_ack)?"ACK":"   ",
541
                                (m_core->o_dbg_stall)?"STALL":"     ",
542
                                (m_core->o_dbg_data),
543
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
544
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
545
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
546
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
547
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
548
                                (m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
549
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
550
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
551
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
552
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
553
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
554
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
555
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
556
                                (m_core->v__DOT__sys_we)?"WE":"  ",
557
                                (m_core->v__DOT__sys_addr),
558
                                (m_core->v__DOT__dbg_addr),
559
                                (m_core->v__DOT__sys_data),
560
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
561
                                (m_core->v__DOT__wb_data));
562
                }
563
 
564
                if (dbg_fp)
565
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
566
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
567
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
568
                                m_core->v__DOT__thecpu__DOT__op_ce,
569
                                m_core->v__DOT__thecpu__DOT__op_pc,
570
                                m_core->v__DOT__thecpu__DOT__dcdA,
571
                                m_core->v__DOT__thecpu__DOT__opR,
572
                                m_core->v__DOT__cmd_halt,
573
                                m_core->v__DOT__cpu_halt,
574
                                m_core->v__DOT__thecpu__DOT__alu_ce,
575
                                m_core->v__DOT__thecpu__DOT__alu_valid,
576
                                m_core->v__DOT__thecpu__DOT__alu_wr,
577
                                m_core->v__DOT__thecpu__DOT__alu_reg,
578
                                m_core->v__DOT__thecpu__DOT__ipc,
579
                                m_core->v__DOT__thecpu__DOT__upc);
580
 
581
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
582
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
583
                                m_core->v__DOT__pic_interrupt,
584
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
585
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
586
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
587
                                m_core->v__DOT__cmd_addr,
588
                                m_core->v__DOT__dbg_idata,
589
                                m_core->v__DOT__thecpu__DOT__master_ce,
590
                                m_core->v__DOT__thecpu__DOT__alu_wr,
591
                                m_core->v__DOT__thecpu__DOT__alu_valid,
592
                                m_core->v__DOT__thecpu__DOT__mem_valid);
593
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
594
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
595
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
596
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
597
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
598
                                m_core->v__DOT__cmd_addr,
599
                                m_core->v__DOT__dbg_idata,
600
                                m_core->v__DOT__thecpu__DOT__master_ce,
601
                                m_core->v__DOT__thecpu__DOT__alu_wr,
602
                                m_core->v__DOT__thecpu__DOT__alu_valid,
603
                                m_core->v__DOT__thecpu__DOT__mem_valid,
604
                                m_core->v__DOT__thecpu__DOT__w_iflags,
605
                                m_core->v__DOT__thecpu__DOT__w_uflags);
606
                        fprintf(dbg_fp, "\tbrk=%d,%d\n",
607
                                m_core->v__DOT__thecpu__DOT__break_en,
608
                                m_core->v__DOT__thecpu__DOT__op_break);
609
                }
610
 
611
                TESTB<Vzipsystem>::tick();
612
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
613
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
614
                                (gie)?"User":"Supervisor",
615
                                (gie)?"Supervisor":"User",
616
                                m_core->v__DOT__thecpu__DOT__ipc,
617
                                m_core->v__DOT__thecpu__DOT__upc,
618
                                m_core->v__DOT__thecpu__DOT__pf_pc);
619
                } if (dbg_fp) {
620
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
621
                                m_core->v__DOT__thecpu__DOT__opvalid,
622
                                m_core->v__DOT__thecpu__DOT__op_gie,
623
                                m_core->v__DOT__thecpu__DOT__op_stall,
624
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
625
                        dbgins("Al - ",
626
                                m_core->v__DOT__thecpu__DOT__alu_ce,
627
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
628
                                m_core->v__DOT__thecpu__DOT__alu_gie,
629
                                m_core->v__DOT__thecpu__DOT__alu_stall,
630
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
631
 
632
                }
633
 
634
                if (m_core->v__DOT__cpu_dbg_we) {
635
                        printf("WRITE-ENABLE!!\n");
636
                        bomb = true;
637
                }
638
        }
639
 
640
        bool    test_success(void) {
641
                return ((!m_core->v__DOT__thecpu__DOT__gie)
642
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
643
        }
644
 
645
        bool    test_failure(void) {
646
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
647
                        &&(!m_core->v__DOT__thecpu__DOT__alu_gie)
648
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
649
                                == 0x2f0f7fff));
650
        }
651
 
652
        void    wb_write(unsigned a, unsigned int v) {
653
                mvprintw(0,35, "%40s", "");
654
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
655
                m_core->i_dbg_cyc = 1;
656
                m_core->i_dbg_stb = 1;
657
                m_core->i_dbg_we  = 1;
658
                m_core->i_dbg_addr = a & 1;
659
                m_core->i_dbg_data = v;
660
 
661
                tick();
662
                while(m_core->o_dbg_stall)
663
                        tick();
664
 
665
                m_core->i_dbg_stb = 0;
666
                while(!m_core->o_dbg_ack)
667
                        tick();
668
 
669
                // Release the bus
670
                m_core->i_dbg_cyc = 0;
671
                m_core->i_dbg_stb = 0;
672
                tick();
673
                mvprintw(0,35, "%40s", "");
674
                mvprintw(0,40, "wb_write -- complete");
675
        }
676
 
677
        unsigned long   wb_read(unsigned a) {
678
                unsigned int    v;
679
                mvprintw(0,35, "%40s", "");
680
                mvprintw(0,40, "wb_read(0x%08x)", a);
681
                m_core->i_dbg_cyc = 1;
682
                m_core->i_dbg_stb = 1;
683
                m_core->i_dbg_we  = 0;
684
                m_core->i_dbg_addr = a & 1;
685
 
686
                tick();
687
                while(m_core->o_dbg_stall)
688
                        tick();
689
 
690
                m_core->i_dbg_stb = 0;
691
                while(!m_core->o_dbg_ack)
692
                        tick();
693
                v = m_core->o_dbg_data;
694
 
695
                // Release the bus
696
                m_core->i_dbg_cyc = 0;
697
                m_core->i_dbg_stb = 0;
698
                tick();
699
 
700
                mvprintw(0,35, "%40s", "");
701
                mvprintw(0,40, "wb_read = 0x%08x", v);
702
 
703
                return v;
704
        }
705
 
706
};
707
 
708
 
709
int     main(int argc, char **argv) {
710
        Verilated::commandArgs(argc, argv);
711
        ZIPPY_TB        *tb = new ZIPPY_TB();
712
        ZPARSER         zp;
713
 
714
        printf("uCC = %d\n", (int)zp.ZIP_uCC);
715
        printf("MOV CC,R0 = 0x%08x\n", zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0));
716
                // = 0x200e8000
717
                // Op = 0x2
718
                // Result = 0x0, R0 (Supervisor/default)
719
                // Cond   = 0x0
720
                // BReg   = 0xe (CC)
721
                // BMap   = 1, BReg = uCC
722
                //
723
 
724
        initscr();
725
        raw();
726
        noecho();
727
        keypad(stdscr, true);
728
 
729
        // mem[0x00000] = 0xbe000010; // Halt instruction
730
        unsigned int mptr = 0;
731
 
732 9 dgisselq
        if (argc <= 1) {
733 2 dgisselq
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
734
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); //  1: MOV R0,R1
735
        tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); //  2: MOV $1+R0,R2
736
        tb->m_mem[mptr++] = zp.op_mov(2,zp.ZIP_R0,zp.ZIP_R3); //  3: MOV $2+R0,R3
737
        tb->m_mem[mptr++] = zp.op_mov(0x022, zp.ZIP_R0, zp.ZIP_R4); //  4: MOV $22h+R0,R4
738
        tb->m_mem[mptr++] = zp.op_mov(0x377, zp.ZIP_R0, zp.ZIP_uR5); //  5: MOV $377h+R0,uR5
739
        tb->m_mem[mptr++] = zp.op_noop(); //  6: NOOP
740
        tb->m_mem[mptr++] = zp.op_add(0,zp.ZIP_R2,zp.ZIP_R0); //  7: ADD R2,R0
741
        tb->m_mem[mptr++] = zp.op_add(32,zp.ZIP_R0); //  8: ADD $32,R0
742
        tb->m_mem[mptr++] = zp.op_add(-33,zp.ZIP_R0); //  9: ADD -$33,R0
743
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_Z, zp.ZIP_R0); //  A: NOT.Z R0
744
        tb->m_mem[mptr++] = zp.op_clrf(zp.ZIP_R0); //  B: CLRF R0
745
        tb->m_mem[mptr++] = zp.op_ldi(5,zp.ZIP_R1); //  C: LDI $5,R1
746
        tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R0,zp.ZIP_R1); //  D: CMP R0,R1
747
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_LT, zp.ZIP_R0); //  E: NOT.LT R0
748
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_GE, zp.ZIP_R1); //  F: NOT.GE R1
749
        tb->m_mem[mptr++] = zp.op_lod(-7,zp.ZIP_PC, zp.ZIP_R2); // 10: LOD $-7(PC),R2
750
        tb->m_mem[mptr++] = zp.op_ldihi(0xdead, zp.ZIP_R3); // 11: LODIHI $deadh,R3
751
        tb->m_mem[mptr++] = zp.op_ldilo(0xbeef, zp.ZIP_R3); // 12: LODILO $beefh,R3
752
 
753
        // Let's build a software test bench.
754
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R12);//  0: CLR R12
755
        tb->m_mem[mptr++] = zp.op_ldihi(0xc000,zp.ZIP_R12);
756
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R12,zp.ZIP_uR12);
757
        tb->m_mem[mptr++] = zp.op_mov(10,zp.ZIP_PC,zp.ZIP_uPC);
758
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // Clear R0, and disable ints
759
        tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R12);
760
        tb->m_mem[mptr++] = zp.op_rtu(); //  7: RTU     // Switch to user mode
761
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0); // Check result
762
        tb->m_mem[mptr++] = zp.op_tst(-256,zp.ZIP_R0);
763
        tb->m_mem[mptr++] = zp.op_bnz(1);
764
        tb->m_mem[mptr++] = zp.op_halt();// On SUCCESS
765
        tb->m_mem[mptr++] = zp.op_busy(); // On FAILURE
766
 
767
 
768
        // Now for a series of tests.  If the test fails, call the trap
769
        // interrupt with the test number that failed.  Upon completion,
770
        // call the trap with #0.
771
 
772
        // Now for a series of tests.  If the test fails, call the trap
773
        // interrupt with the test number that failed.  Upon completion,
774
        // call the trap with #0.
775
 
776
        // Test LDI to PC
777
        // Some data registers
778
        tb->m_mem[mptr] = mptr + 5 + 0x0100000; mptr++;
779
        tb->m_mem[mptr++] = zp.op_ldi(0x020,zp.ZIP_CC); //  LDI $GIE,CC
780
        tb->m_mem[mptr++] = zp.op_ldi(0x0200,zp.ZIP_R11); //  LDI $200h,R11
781
        tb->m_mem[mptr++] = zp.op_lod(-4,zp.ZIP_PC,zp.ZIP_PC); //  1: LOD $-3(PC),PC
782
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); //  2: CLR R11
783
        tb->m_mem[mptr++] = zp.op_noop(); //  3: NOOP
784
        tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R11); //  4: CMP $0,R11
785
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_R10); //  5: STO.Z R11,(R12)
786
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_CC); //  5: STO.Z R11,(R12)
787
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  6: ADD $1,R0
788
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  7: ADD $1,R0
789
 
790
        // Let's test whether overflow works
791
        tb->m_mem[mptr++] = zp.op_ldi(0x0300,zp.ZIP_R11); //  0: LDI $3,R11
792
        tb->m_mem[mptr++] = zp.op_ldi(-1,zp.ZIP_R0); //  1: LDI $-1,R0
793
        tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0); //  R0 // R0 = max int
794
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  Should set ovfl
795
        tb->m_mem[mptr++] = zp.op_bv(1); //  4: BV $1+PC
796
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
797
        // Overflow set from subtraction
798
        tb->m_mem[mptr++] = zp.op_ldi(0x0400,zp.ZIP_R11); //  6: LDI $4,R11
799
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); //  7: LDI $1,R0
800 8 dgisselq
        tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0); //  8: ROL $31,R0
801 2 dgisselq
        tb->m_mem[mptr++] = zp.op_sub(1,zp.ZIP_R0); // Should set ovfl
802
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
803
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
804
        // Overflow set from LSR
805
        tb->m_mem[mptr++] = zp.op_ldi(0x0500,zp.ZIP_R11); //  C: LDI $5,R11
806 8 dgisselq
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
807
        tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
808
        tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0);
809
        tb->m_mem[mptr++] = zp.op_bv(1);
810 2 dgisselq
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
811
        // Overflow set from LSL
812 8 dgisselq
        tb->m_mem[mptr++] = zp.op_ldi(0x0600,zp.ZIP_R11);
813
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
814
        tb->m_mem[mptr++] = zp.op_rol(30,zp.ZIP_R0);
815
        tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
816
        tb->m_mem[mptr++] = zp.op_bv(1);
817 2 dgisselq
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
818
        // Overflow set from LSL, negative to positive
819 8 dgisselq
        tb->m_mem[mptr++] = zp.op_ldi(0x0700,zp.ZIP_R11);
820
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
821
        tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
822
        tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
823 2 dgisselq
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
824
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
825
 
826
 
827
        // Test carry
828
        tb->m_mem[mptr++] = zp.op_ldi(0x01000, zp.ZIP_R11); //  0: LDI $16,R11
829
        tb->m_mem[mptr++] = zp.op_ldi(-1, zp.ZIP_R0); //  1: LDI $-1,R0
830
        tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); //  2: ADD $1,R0
831
        tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); //  3: TST $2,CC // Is the carry set?
832
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
833
        // and carry from subtraction
834
        tb->m_mem[mptr++] = zp.op_ldi(0x01100, zp.ZIP_R11); //  0: LDI $17,R11
835
        tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R0); //  1: SUB $1,R0
836
        tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); //  2: TST $2,CC // Is the carry set?
837
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
838
 
839
 
840
 
841
        // Let's try a loop: for i=0; i<5; i++)
842
        //      We'll use R0=i, Immediates for 5
843
        tb->m_mem[mptr++] = zp.op_ldi(0x01200, zp.ZIP_R11); //  0: LDI $18,R11
844
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
845
        tb->m_mem[mptr++] = zp.op_noop();
846
        tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); //  2: R0 = R0 + 1
847
        tb->m_mem[mptr++] = zp.op_cmp(5, zp.ZIP_R0); //  3: CMP $5,R0
848
        tb->m_mem[mptr++] = zp.op_blt(-4); //  4: BLT PC-4
849
        //
850
        // Let's try a reverse loop.  Such loops are usually cheaper to
851
        // implement, and this one is no different: 2 loop instructions 
852
        // (minus setup instructions) vs 3 from before.
853
        // R0 = 5; (from before)
854
        // do {
855
        // } while (R0 > 0);
856
        tb->m_mem[mptr++] = zp.op_ldi(0x01300, zp.ZIP_R11); //  0: LDI $18,R11
857
        tb->m_mem[mptr++] = zp.op_noop(); //  5: NOOP
858
        tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0); //  6: R0 = R0 - 1
859
        tb->m_mem[mptr++] = zp.op_bgt(-3); //  7: BGT PC-3
860
        // How about the same thing with a >= comparison?
861
        // R1 = 5; // Need to do this explicitly
862
        // do {
863
        // } while(R1 >= 0);
864
        tb->m_mem[mptr++] = zp.op_ldi(0x01400, zp.ZIP_R11); //  0: LDI $18,R11
865
        tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R1);
866
        tb->m_mem[mptr++] = zp.op_noop();
867
        tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R1);
868
        tb->m_mem[mptr++] = zp.op_bge(-3);
869
 
870
        // Let's try the reverse loop again, only this time we'll store our
871
        // loop variable in memory.
872
        // R0 = 5; (from before)
873
        // do {
874
        // } while (R0 > 0);
875
        tb->m_mem[mptr++] = zp.op_ldi(0x01500, zp.ZIP_R11); //  0: LDI $18,R11
876
        tb->m_mem[mptr++] = zp.op_bra(1); // Give us a memory location
877
        tb->m_mem[mptr++] = 5; // Loop five times
878
        tb->m_mem[mptr++] = zp.op_mov(-2, zp.ZIP_PC, zp.ZIP_R1); // Get var adr
879
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R2);
880
        tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R0);
881
        tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R1);
882
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R2);
883
        tb->m_mem[mptr++] = zp.op_add(14,zp.ZIP_R0);
884
        tb->m_mem[mptr++] = zp.op_lod(0,zp.ZIP_R1,zp.ZIP_R0);
885
        tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0);
886
        tb->m_mem[mptr++] = zp.op_bgt(-6);
887
        tb->m_mem[mptr++] = zp.op_cmp( 5, zp.ZIP_R2);
888
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_NZ, 0, zp.ZIP_R11, zp.ZIP_CC);
889
 
890
        // Return success / Test the trap interrupt
891
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); //  0: CLR R11
892
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R11, zp.ZIP_CC);
893
        tb->m_mem[mptr++] = zp.op_noop(); //  2: NOOP // Give it a chance to take
894
        tb->m_mem[mptr++] = zp.op_noop(); //  3: NOOP // effect
895
 
896
        // Go into an infinite loop if the trap fails
897
        // Permanent loop instruction -- a busy halt if you will
898
        tb->m_mem[mptr++] = zp.op_busy(); //  4: BRA PC-1
899
 
900
        // And, in case we miss a halt ...
901
        tb->m_mem[mptr++] = zp.op_halt(); // HALT
902
 
903 9 dgisselq
        } else {
904
                for(int argn=1; argn<argc; argn++) {
905
                        if (access(argv[argn], R_OK)==0) {
906
                                FILE *fp = fopen(argv[argn], "r");
907
                                if (fp == NULL) {
908
                                        printf("Cannot open %s\n", argv[argn]);
909
                                        perror("O/S Err: ");
910
                                        exit(-1);
911
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
912
                                fclose(fp);
913
                        }
914
                }
915
        }
916
 
917 2 dgisselq
        tb->reset();
918
        int     chv = 'q';
919
        const   bool    live_debug_mode = true;
920
 
921
        if (live_debug_mode) {
922
                bool    done = false, halted = true, manual = true;
923
 
924
                halfdelay(1);
925
                tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
926
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
927
                        // tb->show_state();
928
 
929
                while(!done) {
930
                        chv = getch();
931
                        switch(chv) {
932
                        case 'h': case 'H':
933
                                tb->wb_write(CMD_REG, CMD_HALT);
934
                                if (!halted)
935
                                        erase();
936
                                halted = true;
937
                                break;
938
                        case 'g': case 'G':
939
                                tb->wb_write(CMD_REG, 0);
940
                                if (halted)
941
                                        erase();
942
                                halted = false;
943
                                manual = false;
944
                                break;
945
                        case 'q': case 'Q':
946
                                done = true;
947
                                break;
948
                        case 'r': case 'R':
949
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
950
                                halted = true;
951
                                erase();
952
                                break;
953
                        case 's': case 'S':
954
                                tb->wb_write(CMD_REG, CMD_STEP);
955
                                manual = false;
956
                                break;
957
                        case 't': case 'T':
958
                                manual = true;
959
                                tb->tick();
960
                                break;
961
                        case ERR:
962
                        default:
963
                                if (!manual)
964
                                        tb->tick();
965
                        }
966
 
967
                        if (manual) {
968
                                tb->show_state();
969
                        } else if (halted) {
970
                                if (tb->dbg_fp)
971
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
972
                                tb->read_state();
973
                        } else
974
                                tb->show_state();
975
 
976
                        if (tb->m_core->i_rst)
977
                                done =true;
978
                        if (tb->bomb)
979
                                done = true;
980
                }
981
 
982
        } else { // Manual stepping mode
983
                tb->show_state();
984
 
985
                while('q' != tolower(chv = getch())) {
986
                        tb->tick();
987
                        tb->show_state();
988
 
989
                        if (tb->test_success())
990
                                break;
991
                        else if (tb->test_failure())
992
                                break;
993
                }
994
        }
995
 
996
        endwin();
997
 
998
        if (tb->test_success())
999
                printf("SUCCESS!\n");
1000
        else if (tb->test_failure())
1001
                printf("TEST FAILED!\n");
1002
        else if (chv == 'q')
1003
                printf("chv = %c\n", chv);
1004
        exit(0);
1005
}
1006
 

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