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[/] [zipcpu/] [trunk/] [bench/] [formal/] [abs_mpy.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    abs_mpy.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This code has been modified from the mpyop.v file so as to
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//              abstract the multiply that formal methods struggle so hard to
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//      deal with.  It also simplifies the interface so that (if enabled)
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//      the multiply will return in 1-6 clocks, rather than the specified
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//      number for the given architecture.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  abs_mpy(i_clk,i_reset, i_stb, i_op, i_a, i_b, o_valid, o_busy, o_result, o_hi);
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        // The following parameter selects which multiply algorithm we use.
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        // Timing performance is strictly dependent upon it.
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        parameter       IMPLEMENT_MPY = 1;
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        parameter       MAXDELAY = 3;
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        input   wire            i_clk, i_reset, i_stb;
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        input   wire    [1:0]    i_op; // 2'b00=MPY, 2'b10=MPYUHI, 2'b11=MPYSHI
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        input   wire    [31:0]   i_a, i_b;
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        output  reg             o_valid; // True if we'll be valid on the next clock;
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        output  wire            o_busy; // The multiply is busy if true
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        output  wire    [63:0]   o_result; // Where we dump the multiply result
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        output  reg             o_hi;   // Return the high half of the multiply
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`define ASSERT  assert
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// i_stb instead of this_is_a_multiply_op
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// o_result
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// o_busy
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// o_done
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        generate
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        if (IMPLEMENT_MPY == 0)
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        begin // No multiply support.
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                assign  o_result   = 64'h00;
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                assign  o_busy     = 1'b0;
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                always @(*)
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                        o_valid    = i_stb;
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                always @(*) o_hi = 1'b0; // Not needed
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        end else begin // Our single clock option (no extra clocks)
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                (* anyseq *) reg        [2:0]    next_delay_to_valid;
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                (* anyseq *) reg        [63:0]   any_result;
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                assign  o_result = any_result;
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                reg     [2:0]    delay_to_valid;
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                reg             r_busy;
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                always @(*)
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                assume((MAXDELAY == 0)
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                        ||(next_delay_to_valid < MAXDELAY));
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                // always @(*)
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                // if (IMPLEMENT_MPY == 1)
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                        // assume(next_delay_to_valid == 0);
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                always @(*)
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                if (IMPLEMENT_MPY>0)
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                        assume(next_delay_to_valid == IMPLEMENT_MPY-1);
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                initial delay_to_valid = 3'h0;
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                always @(posedge i_clk)
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                if (i_reset)
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                        delay_to_valid <= 0;
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                else if ((i_stb)&&(next_delay_to_valid != 0))
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                        delay_to_valid <= next_delay_to_valid;
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                else if (delay_to_valid > 0)
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                        delay_to_valid <= delay_to_valid - 1'b1;
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                initial r_busy = 1'b0;
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                always @(posedge i_clk)
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                if (i_reset)
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                        r_busy <= 1'b0;
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                else if (i_stb)
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                        r_busy <= (next_delay_to_valid != 0);
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                else if (r_busy)
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                        r_busy <= (delay_to_valid != 3'h1);
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                initial o_valid = 0;
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                always @(posedge i_clk)
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                if (i_reset)
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                        o_valid <= 1'b0;
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                else if ((i_stb)&&(next_delay_to_valid == 0))
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                        o_valid <= 1'b1;
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                else
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                        o_valid <= (o_busy)&&(delay_to_valid == 3'h1);
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                always @(posedge i_clk)
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                if (i_stb)
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                        o_hi <= i_op[1];
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                assign  o_busy = r_busy;
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        end
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        endgenerate // All possible multiply results have been determined
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endmodule

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