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[/] [zipcpu/] [trunk/] [bench/] [formal/] [div.gtkw] - Blame information for rev 209

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Line No. Rev Author Line
1 209 dgisselq
[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Sat Aug 11 16:11:56 2018
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[*]
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[dumpfile] "/home/dan/jericho/work/rnd/zipcpu/trunk/bench/formal/div.vcd"
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[dumpfile_mtime] "Sat Aug 11 15:44:52 2018"
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[dumpfile_size] 3746
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[savefile] "/home/dan/jericho/work/rnd/zipcpu/trunk/sim/verilator/div_tb.gtkw"
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[timestart] 0
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[size] 1698 819
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[pos] -1 -1
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*-4.333802 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 270
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[signals_width] 220
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[sst_expanded] 1
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[sst_vpaned_height] 221
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@28
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smt_clock
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div.i_clk
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div.i_reset
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@200
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-
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@28
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[color] 2
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div.i_wr
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[color] 2
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div.i_signed
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@22
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[color] 2
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div.i_numerator[31:0]
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[color] 2
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div.i_denominator[31:0]
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@200
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-
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@28
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[color] 3
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div.o_busy
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[color] 3
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div.o_valid
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@22
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[color] 3
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div.o_flags[3:0]
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[color] 3
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div.o_quotient[31:0]
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@28
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[color] 3
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div.o_err
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@200
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-
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@22
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div.r_bit[4:0]
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@28
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div.pre_sign
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div.r_busy
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div.r_sign
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@29
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div.last_bit
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@22
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div.diff[32:0]
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div.r_dividend[62:0]
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div.r_divisor[31:0]
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@28
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div.r_c
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div.r_z
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div.w_n
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div.zero_divisor
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@22
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div.f_bits_set[32:0]
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[pattern_trace] 1
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[pattern_trace] 0

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