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[/] [zipcpu/] [trunk/] [bench/] [formal/] [idecode.gtkw] - Blame information for rev 209

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Line No. Rev Author Line
1 209 dgisselq
[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Sun Dec  2 03:08:39 2018
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[*]
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[dumpfile] "(null)"
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[savefile] "/home/dan/bizcopy/zipcpu/bench/formal/idecode.gtkw"
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[timestart] 0
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[size] 1665 600
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[pos] -1 -1
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*-3.760617 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 270
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[signals_width] 230
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[sst_expanded] 1
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[sst_vpaned_height] 143
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@28
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idecode.i_ce
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idecode.i_clk
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idecode.i_gie
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idecode.i_pf_valid
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idecode.i_illegal
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@22
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idecode.i_instruction[31:0]
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idecode.i_pc[25:0]
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@28
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idecode.i_reset
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idecode.i_stalled
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@22
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idecode.iword[30:0]
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@200
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-
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@29
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idecode.o_valid
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@22
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idecode.o_dcdA[6:0]
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idecode.o_dcdB[6:0]
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@28
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idecode.o_ALU
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idecode.o_DV
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idecode.o_FP
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@22
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idecode.o_I[31:0]
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@28
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idecode.o_M
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@22
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idecode.o_branch_pc[25:0]
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@28
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idecode.o_break
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@22
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idecode.o_cond[3:0]
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@28
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idecode.o_early_branch
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idecode.o_early_branch_stb
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idecode.o_illegal
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idecode.o_ljmp
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idecode.o_lock
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@22
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idecode.o_op[3:0]
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idecode.o_pc[25:0]
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@28
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idecode.o_phase
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idecode.o_pipe
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@22
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idecode.o_preA[4:0]
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idecode.o_preB[4:0]
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@28
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idecode.o_rA
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idecode.o_rB
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idecode.o_sim
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@22
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idecode.o_sim_immv[22:0]
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@28
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idecode.o_wF
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idecode.o_wR
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idecode.o_zI
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@22
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idecode.f_hidden_state[31:0]
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idecode.f_insn_word[31:0]
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@28
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idecode.f_last_insn
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idecode.f_new_insn
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idecode.f_past_valid
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@22
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idecode.f_result[127:0]
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idecode.f_this_pipe_I[20:0]
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@28
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idecode.fc_ALU
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idecode.fc_DV
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idecode.fc_FP
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@22
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idecode.fc_I[31:0]
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@28
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idecode.fc_M
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idecode.fc_break
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@22
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idecode.fc_cond[3:0]
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idecode.fc_dcdA[6:0]
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idecode.fc_dcdB[6:0]
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idecode.fc_dcdR[6:0]
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@28
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idecode.fc_illegal
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idecode.fc_lock
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@22
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idecode.fc_op[3:0]
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@28
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idecode.fc_rA
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idecode.fc_rB
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idecode.fc_sim
108
@22
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idecode.fc_sim_immv[22:0]
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@28
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idecode.fc_wF
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idecode.fc_wR
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idecode.pf_valid
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@22
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idecode.possibly_unused[5:0]
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idecode.r_I[22:0]
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@28
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idecode.r_valid
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idecode.w_ALU
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@22
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idecode.w_I[22:0]
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@28
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idecode.w_Iz
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idecode.w_add
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idecode.w_break
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idecode.w_brev
127
@22
128
idecode.w_cis_op[4:0]
129
@28
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idecode.w_cmptst
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@22
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idecode.w_cond[3:0]
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idecode.w_dcdA[4:0]
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@28
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idecode.w_dcdA_cc
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idecode.w_dcdA_pc
137
@22
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idecode.w_dcdB[4:0]
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@28
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idecode.w_dcdB_cc
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idecode.w_dcdB_pc
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@22
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idecode.w_dcdR[4:0]
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@28
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idecode.w_dcdR_cc
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idecode.w_dcdR_pc
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idecode.w_div
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idecode.w_fpu
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@22
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idecode.w_fullI[22:0]
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@28
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idecode.w_ldi
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idecode.w_ldilo
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idecode.w_ljmp
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idecode.w_ljmp_dly
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idecode.w_lock
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idecode.w_mem
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idecode.w_mov
159
idecode.w_mpy
160
idecode.w_noop
161
@22
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idecode.w_op[4:0]
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@28
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idecode.w_rA
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idecode.w_rB
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idecode.w_sim
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idecode.w_special
168
idecode.w_sto
169
idecode.w_wF
170
idecode.w_wR
171
idecode.w_wR_n
172
[pattern_trace] 1
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[pattern_trace] 0

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