URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [formal/] [idecode.gtkw] - Blame information for rev 209

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[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Sun Dec  2 03:08:39 2018
[*]
[dumpfile] "(null)"
[savefile] "/home/dan/bizcopy/zipcpu/bench/formal/idecode.gtkw"
[timestart] 0
[size] 1665 600
[pos] -1 -1
*-3.760617 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 270
[signals_width] 230
[sst_expanded] 1
[sst_vpaned_height] 143
@28
idecode.i_ce
idecode.i_clk
idecode.i_gie
idecode.i_pf_valid
idecode.i_illegal
@22
idecode.i_instruction[31:0]
idecode.i_pc[25:0]
@28
idecode.i_reset
idecode.i_stalled
@22
idecode.iword[30:0]
@200
-
@29
idecode.o_valid
@22
idecode.o_dcdA[6:0]
idecode.o_dcdB[6:0]
@28
idecode.o_ALU
idecode.o_DV
idecode.o_FP
@22
idecode.o_I[31:0]
@28
idecode.o_M
@22
idecode.o_branch_pc[25:0]
@28
idecode.o_break
@22
idecode.o_cond[3:0]
@28
idecode.o_early_branch
idecode.o_early_branch_stb
idecode.o_illegal
idecode.o_ljmp
idecode.o_lock
@22
idecode.o_op[3:0]
idecode.o_pc[25:0]
@28
idecode.o_phase
idecode.o_pipe
@22
idecode.o_preA[4:0]
idecode.o_preB[4:0]
@28
idecode.o_rA
idecode.o_rB
idecode.o_sim
@22
idecode.o_sim_immv[22:0]
@28
idecode.o_wF
idecode.o_wR
idecode.o_zI
@22
idecode.f_hidden_state[31:0]
idecode.f_insn_word[31:0]
@28
idecode.f_last_insn
idecode.f_new_insn
idecode.f_past_valid
@22
idecode.f_result[127:0]
idecode.f_this_pipe_I[20:0]
@28
idecode.fc_ALU
idecode.fc_DV
idecode.fc_FP
@22
idecode.fc_I[31:0]
@28
idecode.fc_M
idecode.fc_break
@22
idecode.fc_cond[3:0]
idecode.fc_dcdA[6:0]
idecode.fc_dcdB[6:0]
idecode.fc_dcdR[6:0]
@28
idecode.fc_illegal
idecode.fc_lock
@22
idecode.fc_op[3:0]
@28
idecode.fc_rA
idecode.fc_rB
idecode.fc_sim
@22
idecode.fc_sim_immv[22:0]
@28
idecode.fc_wF
idecode.fc_wR
idecode.pf_valid
@22
idecode.possibly_unused[5:0]
idecode.r_I[22:0]
@28
idecode.r_valid
idecode.w_ALU
@22
idecode.w_I[22:0]
@28
idecode.w_Iz
idecode.w_add
idecode.w_break
idecode.w_brev
@22
idecode.w_cis_op[4:0]
@28
idecode.w_cmptst
@22
idecode.w_cond[3:0]
idecode.w_dcdA[4:0]
@28
idecode.w_dcdA_cc
idecode.w_dcdA_pc
@22
idecode.w_dcdB[4:0]
@28
idecode.w_dcdB_cc
idecode.w_dcdB_pc
@22
idecode.w_dcdR[4:0]
@28
idecode.w_dcdR_cc
idecode.w_dcdR_pc
idecode.w_div
idecode.w_fpu
@22
idecode.w_fullI[22:0]
@28
idecode.w_ldi
idecode.w_ldilo
idecode.w_ljmp
idecode.w_ljmp_dly
idecode.w_lock
idecode.w_mem
idecode.w_mov
idecode.w_mpy
idecode.w_noop
@22
idecode.w_op[4:0]
@28
idecode.w_rA
idecode.w_rB
idecode.w_sim
idecode.w_special
idecode.w_sto
idecode.w_wF
idecode.w_wR
idecode.w_wR_n
[pattern_trace] 1
[pattern_trace] 0

Line No.	Rev	Author	Line
1	209	dgisselq	`[*]`
2			`[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI`
3			`[*] Sun Dec 2 03:08:39 2018`
4			`[*]`
5			`[dumpfile] "(null)"`
6			`[savefile] "/home/dan/bizcopy/zipcpu/bench/formal/idecode.gtkw"`
7			`[timestart] 0`
8			`[size] 1665 600`
9			`[pos] -1 -1`
10			`*-3.760617 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1`
11			`[sst_width] 270`
12			`[signals_width] 230`
13			`[sst_expanded] 1`
14			`[sst_vpaned_height] 143`
15			`@28`
16			`idecode.i_ce`
17			`idecode.i_clk`
18			`idecode.i_gie`
19			`idecode.i_pf_valid`
20			`idecode.i_illegal`
21			`@22`
22			`idecode.i_instruction[31:0]`
23			`idecode.i_pc[25:0]`
24			`@28`
25			`idecode.i_reset`
26			`idecode.i_stalled`
27			`@22`
28			`idecode.iword[30:0]`
29			`@200`
30			`-`
31			`@29`
32			`idecode.o_valid`
33			`@22`
34			`idecode.o_dcdA[6:0]`
35			`idecode.o_dcdB[6:0]`
36			`@28`
37			`idecode.o_ALU`
38			`idecode.o_DV`
39			`idecode.o_FP`
40			`@22`
41			`idecode.o_I[31:0]`
42			`@28`
43			`idecode.o_M`
44			`@22`
45			`idecode.o_branch_pc[25:0]`
46			`@28`
47			`idecode.o_break`
48			`@22`
49			`idecode.o_cond[3:0]`
50			`@28`
51			`idecode.o_early_branch`
52			`idecode.o_early_branch_stb`
53			`idecode.o_illegal`
54			`idecode.o_ljmp`
55			`idecode.o_lock`
56			`@22`
57			`idecode.o_op[3:0]`
58			`idecode.o_pc[25:0]`
59			`@28`
60			`idecode.o_phase`
61			`idecode.o_pipe`
62			`@22`
63			`idecode.o_preA[4:0]`
64			`idecode.o_preB[4:0]`
65			`@28`
66			`idecode.o_rA`
67			`idecode.o_rB`
68			`idecode.o_sim`
69			`@22`
70			`idecode.o_sim_immv[22:0]`
71			`@28`
72			`idecode.o_wF`
73			`idecode.o_wR`
74			`idecode.o_zI`
75			`@22`
76			`idecode.f_hidden_state[31:0]`
77			`idecode.f_insn_word[31:0]`
78			`@28`
79			`idecode.f_last_insn`
80			`idecode.f_new_insn`
81			`idecode.f_past_valid`
82			`@22`
83			`idecode.f_result[127:0]`
84			`idecode.f_this_pipe_I[20:0]`
85			`@28`
86			`idecode.fc_ALU`
87			`idecode.fc_DV`
88			`idecode.fc_FP`
89			`@22`
90			`idecode.fc_I[31:0]`
91			`@28`
92			`idecode.fc_M`
93			`idecode.fc_break`
94			`@22`
95			`idecode.fc_cond[3:0]`
96			`idecode.fc_dcdA[6:0]`
97			`idecode.fc_dcdB[6:0]`
98			`idecode.fc_dcdR[6:0]`
99			`@28`
100			`idecode.fc_illegal`
101			`idecode.fc_lock`
102			`@22`
103			`idecode.fc_op[3:0]`
104			`@28`
105			`idecode.fc_rA`
106			`idecode.fc_rB`
107			`idecode.fc_sim`
108			`@22`
109			`idecode.fc_sim_immv[22:0]`
110			`@28`
111			`idecode.fc_wF`
112			`idecode.fc_wR`
113			`idecode.pf_valid`
114			`@22`
115			`idecode.possibly_unused[5:0]`
116			`idecode.r_I[22:0]`
117			`@28`
118			`idecode.r_valid`
119			`idecode.w_ALU`
120			`@22`
121			`idecode.w_I[22:0]`
122			`@28`
123			`idecode.w_Iz`
124			`idecode.w_add`
125			`idecode.w_break`
126			`idecode.w_brev`
127			`@22`
128			`idecode.w_cis_op[4:0]`
129			`@28`
130			`idecode.w_cmptst`
131			`@22`
132			`idecode.w_cond[3:0]`
133			`idecode.w_dcdA[4:0]`
134			`@28`
135			`idecode.w_dcdA_cc`
136			`idecode.w_dcdA_pc`
137			`@22`
138			`idecode.w_dcdB[4:0]`
139			`@28`
140			`idecode.w_dcdB_cc`
141			`idecode.w_dcdB_pc`
142			`@22`
143			`idecode.w_dcdR[4:0]`
144			`@28`
145			`idecode.w_dcdR_cc`
146			`idecode.w_dcdR_pc`
147			`idecode.w_div`
148			`idecode.w_fpu`
149			`@22`
150			`idecode.w_fullI[22:0]`
151			`@28`
152			`idecode.w_ldi`
153			`idecode.w_ldilo`
154			`idecode.w_ljmp`
155			`idecode.w_ljmp_dly`
156			`idecode.w_lock`
157			`idecode.w_mem`
158			`idecode.w_mov`
159			`idecode.w_mpy`
160			`idecode.w_noop`
161			`@22`
162			`idecode.w_op[4:0]`
163			`@28`
164			`idecode.w_rA`
165			`idecode.w_rB`
166			`idecode.w_sim`
167			`idecode.w_special`
168			`idecode.w_sto`
169			`idecode.w_wF`
170			`idecode.w_wR`
171			`idecode.w_wR_n`
172			`[pattern_trace] 1`
173			`[pattern_trace] 0`

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Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [formal/] [idecode.gtkw] - Blame information for rev 209