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[/] [zipcpu/] [trunk/] [bench/] [formal/] [zipcpu.gtkw] - Blame information for rev 209

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Line No. Rev Author Line
1 209 dgisselq
[*]
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[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
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[*] Wed May  9 22:36:52 2018
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[*]
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[dumpfile] "(null)"
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[savefile] "/home/dan/work/rnd/zipcpu/trunk/bench/formal/zipcpu.gtkw"
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[timestart] 0
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[size] 1221 600
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[pos] -1 -1
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*-6.814017 90 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] zipcpu.
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[treeopen] zipcpu.instruction_decoder.
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[sst_width] 196
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[signals_width] 222
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[sst_expanded] 1
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[sst_vpaned_height] 155
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@c00200
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-External Inputs
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@28
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[color] 2
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zipcpu.i_reset
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[color] 2
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zipcpu.i_clear_pf_cache
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[color] 2
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zipcpu.i_clk
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[color] 2
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zipcpu.i_halt
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@22
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[color] 2
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zipcpu.i_dbg_data[31:0]
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[color] 2
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zipcpu.i_dbg_reg[4:0]
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@28
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[color] 2
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zipcpu.i_dbg_we
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@22
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[color] 2
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zipcpu.ipc[31:0]
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@28
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[color] 2
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zipcpu.i_interrupt
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@1401200
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-External Inputs
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@c00200
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-CE
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@28
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zipcpu.dcd_ce
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zipcpu.op_ce
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zipcpu.master_ce
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zipcpu.adf_ce_unconditional
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zipcpu.alu_ce
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zipcpu.div_ce
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zipcpu.fpu_ce
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zipcpu.mem_ce
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@1401200
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-CE
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@c00200
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-Valid
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@28
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zipcpu.pf_valid
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zipcpu.dcd_valid
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zipcpu.w_op_valid
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zipcpu.op_valid
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zipcpu.op_valid_alu
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zipcpu.op_valid_div
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zipcpu.op_valid_fpu
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zipcpu.op_valid_mem
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zipcpu.div_valid
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zipcpu.alu_valid
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zipcpu.mem_valid
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zipcpu.mem_pc_valid
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zipcpu.alu_pc_valid
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@1401200
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-Valid
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@c00200
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-Stall
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@28
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zipcpu.pf_stalled
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zipcpu.dcd_A_stall
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zipcpu.dcd_B_stall
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zipcpu.dcd_F_stall
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zipcpu.dcd_stalled
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zipcpu.op_stall
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zipcpu.master_stall
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zipcpu.alu_stall
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zipcpu.mem_pipe_stalled
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zipcpu.mem_stalled
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zipcpu.alu_sreg_stall
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@1401200
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-Stall
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@c00200
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-Busy
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@28
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zipcpu.alu_busy
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zipcpu.mem_busy
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zipcpu.mem_rdbusy
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zipcpu.div_busy
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@1401200
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-Busy
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@c00200
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-f_instruction
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@28
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zipcpu.f_const_gie
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@22
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zipcpu.f_const_insn[31:0]
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zipcpu.f_const_addr[31:0]
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@28
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zipcpu.f_const_phase
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zipcpu.f_const_illegal
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@1401200
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-f_instruction
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@c00200
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-f_instruction_decoded
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@28
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zipcpu.fc_ALU
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zipcpu.fc_DV
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zipcpu.fc_FP
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zipcpu.fc_M
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zipcpu.fc_illegal
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@22
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zipcpu.fc_op[3:0]
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@28
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zipcpu.fc_wF
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zipcpu.fc_wR
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zipcpu.fc_rA
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@22
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zipcpu.fc_Aid[6:0]
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@28
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zipcpu.fc_rB
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@22
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zipcpu.fc_Bid[6:0]
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zipcpu.fc_I[31:0]
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zipcpu.fc_cond[3:0]
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@28
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zipcpu.fc_lock
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zipcpu.fc_break
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zipcpu.fc_sim
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@22
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zipcpu.fc_sim_immv[22:0]
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@1401200
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-f_instruction_decoded
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@c00200
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-f_insn_flags
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@28
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zipcpu.f_pf_insn
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zipcpu.f_pre_dcd_insn
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zipcpu.f_dcd_insn
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zipcpu.f_op_insn
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@1401200
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-f_insn_flags
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@c00200
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-Prefetch
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@28
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zipcpu.pf_new_pc
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zipcpu.pf_stalled
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zipcpu.pf_valid
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@22
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zipcpu.pf_pc[31:0]
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zipcpu.pf_instruction[31:0]
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@28
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zipcpu.pf_illegal
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@1401200
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-Prefetch
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@22
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zipcpu.op_opn[3:0]
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zipcpu.op_Aid[4:0]
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zipcpu.op_Bid[4:0]
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@28
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zipcpu.f_op_branch
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zipcpu.dcd_early_branch
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zipcpu.dcd_early_branch_stb
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@22
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zipcpu.dcd_opn[3:0]
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@28
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zipcpu.instruction_decoder.w_noop
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zipcpu.instruction_decoder.w_special
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zipcpu.instruction_decoder.w_cis_ljmp
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zipcpu.instruction_decoder.w_div
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@22
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zipcpu.instruction_decoder.w_cis_op[4:0]
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@28
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zipcpu.instruction_decoder.w_cmptst
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zipcpu.instruction_decoder.o_illegal
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@22
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zipcpu.instruction_decoder.w_dcdA[4:0]
186
@28
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zipcpu.dcd_illegal
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zipcpu.op_illegal
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zipcpu.alu_illegal
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zipcpu.pending_sreg_write
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zipcpu.clear_pipeline
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zipcpu.op_wR
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zipcpu.set_cond
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zipcpu.alu_wR
195
zipcpu.dcd_gie
196
zipcpu.gie
197
zipcpu.ill_err_i
198
zipcpu.alu_illegal
199
zipcpu.clear_pipeline
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zipcpu.new_pc
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zipcpu.pf_new_pc
202
zipcpu.wr_reg_ce
203
@22
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zipcpu.wr_reg_id[4:0]
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[pattern_trace] 1
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[pattern_trace] 0

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