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[/] [zipcpu/] [trunk/] [bench/] [rtl/] [memdev.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    memdev.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This file is really simple: it creates an on-chip memory,
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//              accessible via the wishbone bus, that can be used in this
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//      project.  The memory has single cycle pipeline access, although the
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//      memory pipeline here still costs a cycle and there may be other cycles
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//      lost between the ZipCPU (or whatever is the master of the bus) and this,
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//      thus costing more cycles in access.  Either way, operations can be
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//      pipelined for single cycle access on subsequent transactions.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module  memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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                o_wb_ack, o_wb_stall, o_wb_data);
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        parameter       LGMEMSZ=15, DW=32, EXTRACLOCK= 0;
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        localparam      AW = LGMEMSZ - 2;
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        input   wire                    i_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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        input   wire    [(AW-1):0]       i_wb_addr;
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        input   wire    [(DW-1):0]       i_wb_data;
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        input   wire    [(DW/8-1):0]     i_wb_sel;
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(DW-1):0]       o_wb_data;
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        wire                    w_wstb, w_stb;
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        wire    [(DW-1):0]       w_data;
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        wire    [(AW-1):0]       w_addr;
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        wire    [(DW/8-1):0]     w_sel;
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        generate
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        if (EXTRACLOCK == 0)
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        begin
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                assign  w_wstb = (i_wb_stb)&&(i_wb_we);
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                assign  w_stb  = i_wb_stb;
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                assign  w_addr = i_wb_addr;
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                assign  w_data = i_wb_data;
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                assign  w_sel  = i_wb_sel;
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        end else begin
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                reg             last_wstb, last_stb;
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                always @(posedge i_clk)
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                        last_wstb <= (i_wb_stb)&&(i_wb_we);
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                always @(posedge i_clk)
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                        last_stb <= (i_wb_stb);
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                reg     [(AW-1):0]       last_addr;
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                reg     [(DW-1):0]       last_data;
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                reg     [(DW/8-1):0]     last_sel;
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                always @(posedge i_clk)
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                        last_data <= i_wb_data;
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                always @(posedge i_clk)
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                        last_addr <= i_wb_addr;
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                always @(posedge i_clk)
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                        last_sel <= i_wb_sel;
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                assign  w_wstb = last_wstb;
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                assign  w_stb  = last_stb;
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                assign  w_addr = last_addr;
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                assign  w_data = last_data;
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                assign  w_sel  = last_sel;
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        end endgenerate
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        reg     [(DW-1):0]       mem     [0:((1<<AW)-1)];
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        always @(posedge i_clk)
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                o_wb_data <= mem[w_addr];
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        always @(posedge i_clk)
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        begin
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                if ((w_wstb)&&(w_sel[3]))
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                        mem[w_addr][31:24] <= w_data[31:24];
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                if ((w_wstb)&&(w_sel[2]))
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                        mem[w_addr][23:16] <= w_data[23:16];
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                if ((w_wstb)&&(w_sel[1]))
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                        mem[w_addr][15: 8] <= w_data[15:8];
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                if ((w_wstb)&&(w_sel[0]))
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                        mem[w_addr][ 7: 0] <= w_data[7:0];
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        end
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        always @(posedge i_clk)
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                o_wb_ack <= (w_stb);
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        assign  o_wb_stall = 1'b0;
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        // verilator lint_off UNUSED
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        wire    unused;
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        assign unused = i_wb_cyc;
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        // verilator lint_on UNUSED
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endmodule

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