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[/] [zipcpu/] [trunk/] [bench/] [zipsim.ld] - Blame information for rev 204

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1 204 dgisselq
/*******************************************************************************
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*
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* Filename:     zipsim.ld
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*
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* Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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*
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* Purpose:      This script provides a description of the memory on the Arty,
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*               for the purposes of where to place programs in memory during
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*               linking.
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*
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* Creator:      Dan Gisselquist, Ph.D.
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*               Gisselquist Technology, LLC
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*
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********************************************************************************
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*
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* Copyright (C) 2017, Gisselquist Technology, LLC
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*
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* This program is free software (firmware): you can redistribute it and/or
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* modify it under the terms of  the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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* target there if the PDF file isn't present.)  If not, see
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*  for a copy.
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*
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* License:      GPL, v3, as defined and found on www.gnu.org,
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*               http://www.gnu.org/licenses/gpl.html
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*
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*
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*******************************************************************************/
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ENTRY(_start)
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MEMORY
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{
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        flash  (wx) : ORIGIN = 0x01000000, LENGTH = 0x01000000 /* 2^24 =  16MB */
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        sdram  (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000000 /* 2^28 = 256MB */
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}
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_flash  = ORIGIN(flash);
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_blkram = 0;
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_sdram  = ORIGIN(sdram);
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_top_of_stack = ORIGIN(sdram) + LENGTH(sdram) - 4;
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SECTIONS
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{
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        .rocode ORIGIN(flash) : {
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                _boot_address = .;
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                *(.start)
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                } > flash
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        _kernel_image_start = . ;
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        _kernel_image_end = . ;
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        _sdram_image_start = . ;
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        .ramcode ORIGIN(sdram) : {
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                *(.kernel)
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                *(.text.startup)
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                *(.text)
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                *(.rodata*) *(.strings)
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                *(.data) *(COMMON)
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                }> sdram AT> flash
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        _sdram_image_end = . ;
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        .bss : {
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                *(.bss)
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                _bss_image_end = . ;
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                } > sdram
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        _top_of_heap = .;
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}

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