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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename:    spec.tex
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%%
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%% Project:     ZipCPU -- a small, lightweight, RISC CPU soft core
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%%
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%% Purpose:     This LaTeX file contains all of the documentation/description
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%%              currently provided with this ZipCPU soft core.  It supersedes
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%%              any information about the instruction set or CPUs found
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%%              elsewhere.  It's not nearly as interesting, though, as the PDF
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%%              file it creates, so I'd recommend reading that before diving
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%%              into this file.  You should be able to find the PDF file in
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%%              the SVN distribution together with this PDF file and a copy of
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%%              the GPL-3.0 license this file is distributed under.  If not,
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%%              just type 'make' in the doc directory and it (should) build
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%%              without a problem.
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%%
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%%
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%% Creator:     Dan Gisselquist
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%%              Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of  the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program.  (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.)  If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License:     GPL, v3, as defined and found on www.gnu.org,
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%%              http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%
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%
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%
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% From TI about DSPs vs FPGAs:
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%       www.ti.com/general/docs/video/foldersGallery.tsp?bkg=gray
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%       &gpn=35145&familyid=1622&keyMatch=DSP Breaktime Episode Three
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%       &tisearch=Search-EN-Everything&DCMP=leadership
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%       &HQS=ep-pro-dsp-leadership-problog-150518-v-en
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%
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%       FPGA's are annoyingly faster, cheaper, and not quite as power hungry
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%       as they used to be.
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%
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%       Why would you choose DSPs over FPGAs?  If you care about size,
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%       if you care about power, or happen to have a complicated algorithm
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%       that just isn't simply doing the same thing over and over
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%
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%       For complex algorithms that change over time.  Each have their strengths
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%       sometimes you can use both.
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%
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%       "No assembly required" -- TI tools all C programming, very GUI based
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%       environment, very little optimization by hand ...
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%
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%
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% The FPGA's Achille's heel: Reconfigurability.  It is very difficult, although
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% I'm sure major vendors will tell you not impossible, to reconfigure an FPGA
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% based upon the need to process time-sensitive data.  If you need one of two
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% algorithms, both which will fit on the FPGA individually but not together,
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% switching between them on the fly is next to impossible, whereas switching
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% algorithm within a CPU is not difficult at all.  For example, imagine
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% receiving a packet and needing to apply one of two data algorithms on the
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% packet before sending it back out, and needing to do so fast.  If both
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% algorithms don't fit in memory, where does the packet go when you need to
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% swap one algorithm out for the other?  And what is the cost of that "context"
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% swap?
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%
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%
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\documentclass{gqtekspec}
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\usepackage{import}
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\usepackage{bytefield}  % Install via apt-get install texlive-science
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% \graphicspath{{../gfx}}
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\project{ZipCPU}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~1.0}
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\definecolor{webred}{rgb}{0.5,0,0}
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\definecolor{webgreen}{rgb}{0,0.4,0}
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\hypersetup{
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        ps2pdf,
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        pdfpagelabels,
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        hypertexnames,
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        pdfauthor={Dan Gisselquist},
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        pdfsubject={ZipCPU},
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        anchorcolor= black,
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        colorlinks = true,
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        linkcolor  = webred,
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        citecolor  = webgreen
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}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\titlepage
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of  the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with this program.  If not, see \hbox{$<$http://www.gnu.org/licenses/$>$} for
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a copy.
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\end{license}
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\begin{revisionhistory}
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1.0 & 11/4/2016 & Gisselquist & Major rewrite,
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                        includes compiler info\\\hline
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0.91& 7/16/2016 & Gisselquist & Described three more CC bits\\\hline
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0.9 & 4/20/2016 & Gisselquist & Modified ISA: LDIHI replaced with MPY,
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        MPYU and MPYS replaced with MPYUHI, and MPYSHI respectively.  LOCK
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        instruction now permits an intermediate ALU operation. \\\hline
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0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
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0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
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0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
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0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
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0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
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0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline
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0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline
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\end{revisionhistory}
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% Revision History
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% Table of Contents, named Contents
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\tableofcontents
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\listoffigures
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\listoftables
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\begin{preface}
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Many people have asked me why I am building the ZipCPU. ARM processors are
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good and effective.  Xilinx makes and markets Microblaze, Altera Nios, and both
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have better toolsets than the ZipCPU will ever have. OpenRISC is also
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available, RISC--V may be replacing it. Why build a new processor?
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The easiest, most obvious answer is the simple one: Because I can.
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There's more to it though. There's a lot of things that I would like to do with
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a processor, and I want to be able to do them in a vendor independent fashion.
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First, I would like to be able to place this processor inside an FPGA.  Without
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paying royalties, ARM is out of the question.  I would then like to be able to
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generate Verilog code, both for the processor and the system it sits within,
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that can run equivalently on both Xilinx, Altera, and Lattice chips, and that
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can be easily ported from one manufacturer's chipsets to another. Even more,
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before purchasing a chip or a board, I would like to know that my soft core
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works. I would like to build a test bench to test components with, and
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Verilator is my chosen test bench. This forces me to use all Verilog, and it
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prevents me from using any proprietary cores. For this reason, Microblaze and
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Nios are out of the question.
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Why not OpenRISC? Because the ZipCPU has different goals.  OpenRISC is designed
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to be a full featured CPU.  The ZipCPU was designed to be a simple, resource
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friendly, CPU.  The result is that it is easy to get a ZipCPU program running
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on bare hardware for a special purpose application--such as what FPGAs were
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designed for, but getting a full featured
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Linux distribution running on the ZipCPU may just be beyond my grasp.  Further,
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the OpenRISC ISA is very complex, defining over 200~instructions--even though
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it has never been fully implemented.  The ZipCPU on the other hand has only
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a small handful of instructions, and all but the Floating Point instructions
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have already been fully implemented.
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My final reason is that I'm building the ZipCPU as a learning experience. The
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ZipCPU has allowed me to learn a lot about how CPUs work on a very micro
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level. For the first time, I am beginning to understand many of the Computer
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Architecture lessons from years ago.
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182
To summarize: Because I can, because it is open source, because it is light
183
weight, and as an exercise in learning.
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185
\end{preface}
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187
\chapter{Introduction}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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The goal of the ZipCPU was to be a very simple CPU.   You might think of it as
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a poor man's alternative to the OpenRISC architecture.  You might also think of
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it as an Open Source microcontroller.
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For this reason, all instructions have been designed to be as simple as
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possible, and the base instructions are all designed to be executed in one
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instruction cycle per instruction, barring pipeline stalls.\footnote{The
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exceptions to this rule are the multiply, divide, and load/store instructions.
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Once the floating point unit is built, I anticipate these will also be
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exceptions to this rule.}  Indeed, even the bus has been simplified to a
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constant 32-bit width, with no option for more or less.  This has resulted in
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the choice to drop push and pop instructions, pre-increment and post-decrement
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addressing modes, the integrated memory management unit (MMU), and
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more.\footnote{A not--so integrated MMU is currently under development.}
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For those who like buzz words, the ZipCPU is:
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\begin{itemize}
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\item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits,
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                instructions are 32-bits wide, etc.  Indeed, the ``byte size''
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                for this processor, as per the C--language definition of a
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                ``byte'' being the smallest addressable unit, is 32--bits.
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\item A RISC CPU.  There is no microcode for executing instructions.  All
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        instructions are designed to be completed in one clock cycle.
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\item A Load/Store architecture.  (Only load and store instructions
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                can access memory.)
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\item Wishbone compliant.  All peripherals are accessed just like
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                memory across this bus.
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\item A Von-Neumann architecture.  The instructions and data share a
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                common bus.
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\item A pipelined architecture, having stages for {\bf Prefetch},
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        {\bf Decode}, {\bf Read-Operand}, a combined stage containing
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        the {\bf ALU}, {\bf Memory}, {\bf Divide}, and {\bf Floating Point}
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        units, and then the final {\bf Write-back} stage.
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                See Fig.~\ref{fig:cpu}
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\begin{figure}\begin{center}
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\includegraphics[width=3.5in]{../gfx/cpu.eps}
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\caption{ZipCPU internal pipeline architecture}\label{fig:cpu}
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\end{center}\end{figure}
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                for a diagram of this structure.
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\item Completely open source, licensed under the GPL.\footnote{Should you
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        need a copy of the ZipCPU licensed under other terms, please
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        contact me.}
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\end{itemize}
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The ZipCPU also has one very unique feature: the ability to do pipelined loads
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and stores.  This allows the CPU to access on-chip memory at one access per
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clock, minus any stalls for the initial access.
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\section{Characteristics of a SwiC}
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This section might also be called {\em the ZipCPU philosophy}.  It discusses
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the basis for the ZipCPU design decisions, and why a low logic count CPU
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is or can be a good thing.
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Many other FPGA processors have been defined to be good Systems on a Chip, or
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SoC's.  The entire goal of such designs, then, is to provide an interface
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to the processor and its external environment.  This is not the case with the
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ZipCPU.  Instead, we shall define a new concept, that of a soft core internal to
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an FPGA, as a ``System within a Chip,'' or a SwiC.  SwiCs have some very
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unique properties internal to them that have influenced the design of the
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ZipCPU.  Among these are the bus, memory, and available peripherals.
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Many other approaches to soft core CPU's employ a Harvard architecture.
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This allows these other CPU's to have two separate bus structures: one for the
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program fetch, and the other for the memory.  Indeed, Xilinx's proprietary
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Microblaze processor
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goes so far as to support four busses: two for cacheable memory, and two for
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peripherals, with each of those split between instructions and data.  The
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ZipCPU on the other hand is fairly unique in its approach because it uses a
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Von Neumann architecture, requiring only one bus within any FPGA.  This
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structure was chosen for its simplicity.  Having only the one bus helps to
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minimize real-estate, logic, and the number of wires that need to be passed
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back and forth, while maintaining a high clock speed.  The disadvantage is
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that both prefetch and memory access units need to contend for time on the
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same bus.
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Soft core's within an FPGA have an additional characteristic regarding
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memory access: it is slow.  While memory on chip may be accessed at a single
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cycle per access, small FPGA's often have only a limited amount of memory on
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chip.  Going off chip, however, is expensive.  Two examples will prove this
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point.  On
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the XuLA2 board, Flash can be accessed at 128~cycles per 32--bit word,
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or 64~cycles per subsequent word in a pipelined architecture.  Likewise, the
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SDRAM chip on the XuLA2 board allows a 6~cycle access for a write, 10~cycles
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per read, and 2~cycles for any subsequent pipelined access read or write.
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Either way you look at it, this memory access will be slow and this doesn't
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account for any logic delays should the bus implementation logic get
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complicated.
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As may be noticed from the above discussion about memory speed, a second
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characteristic of memory is sequential memory accesses may be optimized for
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minimal delays (pipelined), and that pipelined memory access is faster than
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non--pipelined access.  Therefore, a SwiC soft core should support pipelined
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operations, but it should also allow a higher priority subsystem to get access
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to the bus (no starvation).
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As a further characteristic of SwiC memory options, on-chip cache's are
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expensive.  If you want to have a minimum of logic, cache logic may not be
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the highest on the priority list.  Any SwiC capable processor must be able
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to either be built without caches, or to scale up or down the logic required
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by any cache.
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In sum, memory is slow.  While one processor on one FPGA may be able to fill
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its pipeline, the same processor on another FPGA may struggle to get more than
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one instruction at a time into the pipeline.  Any SwiC must be able to deal
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with both cases: fast and slow memories.
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A final characteristic of SwiC's within FPGA's is the peripherals.
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Specifically, FPGA's are highly reconfigurable.  Soft peripherals can easily
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be created on chip to support the SwiC if necessary.  As an example, a simple
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30-bit peripheral could easily support reversing 30-bit numbers: a read from
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the peripheral returns its bit--reversed address.  This is cheap within an
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FPGA, but expensive in instructions.  Reading from another 16--bit peripheral
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might calculate a sine function, where the 16--bit address internal to the
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peripheral was the angle of the sine wave.
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Indeed, anything that must be done fast within an FPGA is likely to already
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be done--elsewhere in the fabric.  Further, the application designer gets to
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choose what tasks are so important they need fabric dedicated to them, and which
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ones can be done more slowly in a CPU.  This leaves the CPU with the simple role
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of solely handling sequential tasks, and tasks that need a lot of state.
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This means that the SwiC needs to live within a very unique environment,
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separate and different from the traditional SoC.  That isn't to say that a
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SwiC cannot be turned into a SoC, just that this SwiC has not been designed
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for that purpose.  Indeed, some of the best examples of the ZipCPU are
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System on a Chip examples.
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\section{Scope}\label{sec:limits}
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The ZipCPU is itself nothing more than a CPU that can be placed within a
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larger design.  It is not a System on a Chip, but it can be used to create
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a system on a chip.  As a result, this document will not discuss more than a
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small handful of CPU--related peripherals, as the actual peripherals used
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within a design will vary from one design to the next.  Further, because
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control access will vary from one environment to the next, this document will
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not discuss any host control programs, leaving those to be discussed and defined
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together with the environments the ZipCPU is placed within.
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\chapter{CPU Architecture}\label{chap:arch}
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This chapter describes the general architecture of the ZipCPU.  It first
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discusses
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the configuration options to the CPU and then breaks into two threads. These
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last two threads are a discussion of the internals of the ZipCPU, such as its
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instruction set architecture and the details and consequences of it, and then
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the external architecture describing how the ZipCPU fits into the systems
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surrounding it, and what those systems must do to support it.  Specifically,
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the external architecture section will discuss both the ZipSystem, the
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peripherals provided by it, as well as the debug interface.
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\section{Build Options/defines}\label{ssec:build-options}
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One problem with a simple goal such as being light on logic, is that some
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architectures have some needs, others have other needs.  What is light logic
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in some architectures might consume all the available logic in others.
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As an example, the CMod~S6 board built by Digilent uses a very spare Xilinx
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Spartan~6 LX4 FPGA.  This FPGA doesn't have enough look up tables (LUTs) to
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support pipelined mode, whereas another project running on a XuLA2 LX25 board
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made by Xess, having a Spartan~6 LX25 on board, has more than enough logic
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to support a pipelined mode.   Very quickly it becomes clear that LUTs can be
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traded for performance.
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To make this possible, the ZipCPU has both a configuration file as well as a
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set of parameters that it can be built with.  Often, those parameters can
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override the configuration file, but not all configuration file changes can
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be overridden.  Several options are available within the configuration file,
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such as making the Zip CPU pipelined or not, able to handle a faster clock
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with more stalls or a slower clock with no stalls, etc.
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The {\tt cpudefs.v} file encapsulates those control options.  It contains a
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series of {\tt `define} statements that can either be commented or left
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active.  If active, the option is considered to be in effect.  The number of
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LUTs the Zip CPU uses varies dramatically with the options defined in this file.
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This section will outline the various configuration options captured by this
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file.
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The first couple of options control the Zip CPU instruction set, and how
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it handles various instructions within the set:
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{\tt OPT\_MULTIPLY} controls whether or not the multiply is built and included
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in the ALU by default, and if it is which of several multiply options is
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selected.  Unlike many of the defines that follow within {\tt cpudefs.v} that
374
are either defined or not, this option requires a value.  A value of zero means
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no multiply support, whereas a value of one, two, or three, means that a
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multiply will be included that takes one, two, or three clock cycles to
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complete.  The option, however, only controls the default value that the
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{\tt IMPLEMENT\_MPY} parameter to the CPU, having the same interpretation, is
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given.  Because this is just the default value, it can easily be overridden
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upon instantiation.  If the {\tt IMPLEMENT\_MPY} parameter is set to zero,
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then any attempt to execute a multiply instruction will cause an illegal
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instruction exception.
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{\tt OPT\_DIVIDE} controls whether or not the divide instruction is built and
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included into the ZipCPU by default.  Set this option and the
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{\tt IMPLEMENT\_DIVIDE} parameter will have a default value of one, meaning that
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unless it is overridden with zero, the divide unit will be included.    If the
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divide is not included, then any attempt to use a divide instruction will
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create an illegal instruction exception that will send the CPU into supervisor
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mode.
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{\tt OPT\_IMPLEMENT\_FPU} will (one day) control whether or not the floating
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point unit (once I have one) is built and included into the ZipCPU by default.
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This option sets the {\tt IMPLEMENT\_FPU} parameter to one, so alternatively
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it can be set and adjusted upon instantiation.  If the floating point unit is
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not included then, as with the multiply and divide, any floating point
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instruction will result in an illegal instruction exception that will send the
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CPU into supervisor mode.
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{\tt OPT\_SINGLE\_FETCH} controls whether or not the prefetch has a cache, and
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whether or not it can issue one instruction per clock.  When set, the
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prefetch has no cache, and only one instruction is fetched at any given time.
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This effectively sets the CPU so that only one instruction is ever
404
in the pipeline at a time, and hence you may think of this as a ``no
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pipeline'' option.  However, since the pipeline uses so much area on the FPGA,
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this is an important option to use in trimming down used logic if necessary.
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Hence, it needs to be maintained for that purpose.  Be aware, though, setting
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this option will disable all pipelining, and therefore will drop your
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performance by a factor of 8x or even more.
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I recommend only defining or enabling this option if you {\em need} to,
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such as if area is tight and speed isn't as important.  Otherwise, leave the
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option undefined since the pipelined options have a much better speed
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performance.
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The next several options are pipeline optimization options.  They make no
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sense in a single instruction fetch mode, hence they are all disabled if
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{\tt OPT\_SINGLE\_FETCH} is defined.
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{\tt OPT\_PIPELINED} is the natural result and opposite of using the single
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instruction fetch unit.  It is an internal parameter that doesn't need user
422
adjustment, but if you look through the {\tt cpudefs.v} file you may see
423
and notice it.  If you have not set the {\tt OPT\_SINGLE\_FETCH} parameter,
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{\tt cpudefs.v} will set the {\tt OPT\_PIPELINED} option.  This is more for
425
readability than anything else, since {\tt OPT\_PIPELINED} makes more
426
intuitive readability sense than {\tt OPT\_SINGLE\_FETCH}.  In other words,
427
define or comment out {\tt OPT\_SINGLE\_FETCH}, and let {\tt OPT\_PIPELINED} be
428
taken care of automatically.
429 68 dgisselq
 
430 199 dgisselq
Assuming you have chosen not to define {\tt OPT\_SINGLE\_FETCH},
431
{\tt OPT\_TRADITIONAL\_PFCACHE} allows you to switch between one of two
432
prefetch cache modules.  If enabled (recommended), a more traditional cache
433
will be implemented in the CPU.  This more traditional cache reduces
434
the stall count tremendously over the alternative pipeline cache, and its
435
LUT usage is quite competitive.  As there is little downside to defining
436
this option if pipelining is enabled, I would recommend including it.
437 21 dgisselq
 
438 199 dgisselq
The alternative prefetch and cache, sometimes called the pipeline cache, tries
439
to read instructions ahead of where they are needed, while maintaining what it
440
has read in a cache.  That cache is cleared anytime you jump outside of its
441
window, and it often competes with the CPU for access to the bus.  These
442
two characteristics make this alternative bus often less than optimal.
443 21 dgisselq
 
444
 
445 199 dgisselq
{\tt OPT\_EARLY\_BRANCHING} is an attempt to execute a {\tt BRA} (branch or
446
jump) statement as early
447
in the pipeline as possible, to avoid as many pipeline stalls on a branch as
448
possible.  As an example, if you have {\tt OPT\_TRADITIONAL\_PFCACHE} defined
449
as well, then branches within the cache will only cost a single stall cycle.
450
Indeed, using early branching, a {\tt BRA} instruction can be used as the
451
compiler's branch prediction optimizer: {\tt BRA}'s barely stall, while
452
branches on conditions will always suffer about 6~stall cycles.  Setting
453
this option causes the parameter, {\tt EARLY\_BRANCHING}, to be set to one,
454
so it can be overridden upon instantiation.
455 21 dgisselq
 
456 199 dgisselq
Given the performance benefits achieved by early branching, setting this flag
457
is highly recommended.
458 21 dgisselq
 
459 199 dgisselq
{\tt OPT\_PIPELINED\_BUS\_ACCESS} controls whether or not {\tt LOD}/{\tt STO}
460
instructions can take advantage of the pipelined wishbone bus.  To be
461
eligible, the operations to be pipelined must be adjacent, must be all
462
{\tt LOD}s or all {\tt STO}s, and the addresses must all use the same base
463
address register and either have identical immediate offsets, or immediate
464
offsets that increase by one for each instruction.  Further, the
465
{\tt LOD}/{\tt STO} string of instructions must all have the same conditional
466
(if any).  Currently, this approach and benefit is most effectively used
467
when saving registers to or restoring registers from the stack at the
468
beginning/end of a procedure, when using assembly optimized programs, or
469
when doing a context swap.
470 24 dgisselq
 
471 199 dgisselq
I recommend setting this flag, for performance reasons, especially if your
472
wishbone bus implementation can handle pipelined bus accesses.  The logic
473
impact of this setting is minimal, the performance impact can be significant.
474
 
475
{\tt OPT\_VLIW} includes within the instruction set the Very Long Instruction
476
Word packing, which packs up to two instructions within each instruction word.
477
Non--packed instructions will still execute as normal, this just enables the
478
decoding and running of packed instructions.
479
 
480
The two next options, {\tt INCLUDE\_DMA\_CONTROLLER} and
481
{\tt INCLUDE\_ACCOUNTING\_COUNTERS}
482
control whether the DMA controller is included in the ZipSystem, and
483
whether or not the eight accounting timers are also included.  Set these to
484
include the respective peripherals, comment them out not to.  These only
485
affect the ZipSystem implementation, and not any ZipBones implementations.
486
 
487
Finally, if you find yourself needing to debug the core and specifically needing
488
to get a trace from the core to find out why something specifically failed,
489
you may find it useful to define {\tt DEBUG\_SCOPE}.  This will add a 32--bit
490
debug output from the core, as the last argument to the core, to the ZipSystem,
491
or even to ZipBones.  The actual definition and composition of this debugging
492
bit--field changes from one implementation to the next, depending upon needs
493
and necessities, so please look at the code at the bottom of {\tt zipcpu.v}
494
for more details.
495
 
496
That ends our discussion of CPU options, but there remain several implementation
497
parameters that can be defined with the CPU as well.  Some of these, such as
498
{\tt IMPLEMENT\_MPY}, {\tt IMPLEMENT\_DIVIDE}, {\tt IMPLEMENT\_FPU}, and
499
{\tt EARLY\_BRANCHING} have already been discussed. The remainder shall be
500
discussed quickly here.
501
 
502
The {\tt RESET\_ADDRESS} parameter controls what address the CPU attempts to
503
fetch its first instruction from upon any CPU reset.  The default value is
504
not likely to be particularly useful, so overriding the default is recommended
505
for every implementation.
506
 
507
The {\tt ADDRESS\_WIDTH} parameter can be used to trim down the width of
508
addresses used by the CPU.  For example, although the Wishbone Bus definition
509
used by the CPU  has 32--address lines, particular implementations may have
510
fewer.  By setting this value to the actual number of wires in the address
511
bus, some logic can be spared within the CPU.  The default is a 32--bit wide
512
bus.
513
 
514
The {\tt LGICACHE} parameter specifies the log base two of the instruction
515
cache size.  If no instruction cache is used, this option has no effect.
516
Otherwise it sets the size of the instruction cache to be
517
$2^{\mbox{\tiny\tt LGICACHE}}$ words.  The traditional prefetch cache, if used,
518
will split this cache size into up to thirty two separate cache lines.
519
 
520
The {\tt IMPLEMENT\_LOCK} parameter controls whether or not the {\tt LOCK}
521
instruction is implemented.  If set to zero, the {\tt LOCK} instruction will
522
cause an illegal instruction exception, otherwise it will be implemented if
523
pipelining is enabled.
524
 
525
Other parameters are defined within the ZipSystem parent module, and affect
526
the performance of the system as a whole.
527
 
528
The {\tt START\_HALTED} parameter, if set to non--zero, will cause the
529
CPU to be halted upon startup.  This is useful for debugging, since it prevents
530
the CPU from doing anything without supervision.  Of course, once all pieces
531
of your design are in place and proven, you'll probably want to set this to
532
zero.
533
 
534
The {\tt EXTERNAL\_INTERRUPTS} parameter controls the number of interrupt
535
wires coming into the CPU.  This number must be between one and sixteen,
536
or if the performance counters are disabled, between one and twenty four.
537
 
538
\section{Internal Architecture}\label{sec:internals}
539
 
540
This section discusses the general architecture of the CPU itself, separated
541
from its environment.  As such, it focuses on the instruction set layout
542
and how those instructions are implemented.
543
 
544
\subsection{Register Set}
545
 
546
Fundamental to the understanding of the ZipCPU is its register set, and the
547
performance model associated with it.
548
The ZipCPU register set contains two sets of sixteen 32-bit registers, a
549
supervisor and a user set as shown in Fig.~\ref{fig:regset}.
550 24 dgisselq
\begin{figure}\begin{center}
551 199 dgisselq
\begin{tabular}{|c|c|c|c|c|}
552
\multicolumn{2}{c}{Supervisor Register Set} &
553
        \multicolumn{1}{c}{} &
554
        \multicolumn{2}{c}{User Register Set} \\
555
\multicolumn{2}{c}{\#'s 0-15} & \multicolumn{1}{c}{} &
556
        \multicolumn{2}{c}{\#'s 16-31} \\\hline\hline
557
sR0(LR) & sR8   && uR0(LR) &    uR8     \\\cline{1-2}\cline{4-5}
558
sR1     & sR9   && uR1  &       uR9     \\\cline{1-2}\cline{4-5}
559
sR2     & sR10  && uR2  &       uR10    \\\cline{1-2}\cline{4-5}
560
sR3     & sR11  && uR3  &       uR11    \\\cline{1-2}\cline{4-5}
561
sR4     & sR12(FP)&& uR4&       uR12(FP)\\\cline{1-2}\cline{4-5}
562
sR5     & sSP   && uR5  &       uSP     \\\cline{1-2}\cline{4-5}
563
sR6     & sCC   && uR6  &       uCC     \\\cline{1-2}\cline{4-5}
564
sR7     & sPC   && uR7  &       uPC     \\\hline\hline
565
\multicolumn{2}{c}{Interrupts Disabled} &
566
        \multicolumn{1}{c}{} &
567
        \multicolumn{2}{c}{Interrupts Enabled} \\
568
\end{tabular}
569
\caption{ZipCPU Register File}\label{fig:regset}
570 24 dgisselq
\end{center}\end{figure}
571 199 dgisselq
The supervisor set is used when interrupts are disabled, whereas the user set
572
is used any time interrupts are enabled.  This choice makes it easy to set up
573
a working context upon any interrupt, as the supervisor register set remains
574
what it was when interrupts were enabled.  This sets up one of two modes
575
the CPU can run within: a {\em supervisor mode}, which runs with interrupts
576
disabled using the supervisor register set, and {\em user mode}, which runs
577
with interrupts enabled using the user register set.
578 21 dgisselq
 
579 199 dgisselq
This separation is so fundamental to the CPU that it is impossible to enable
580
interrupts without switching to the user register set.   Further, on any
581
interrupt, exception, or trap, the CPU simply clears the pipeline and switches
582
instruction sets.
583
 
584
In each register set, the Program Counter (PC) is register 15, whereas
585
the status register (SR) or condition code register (CC) is register 14.  All
586
other registers are identical in their hardware functionality.\footnote{Jumps
587
to {\tt R0}, an instruction used to implement a return from a subroutine, may
588
be optimized in the future within the early branch logic.} By convention, the
589
stack pointer is register 13 and noted as (SP)--although there is nothing
590
special about this register other than this convention.  Also by convention, if
591
the compiler needs a frame pointer it will be placed into register~12, and may
592
be abbreviated by FP.  Finally, by convention, R0 will hold a subroutine's
593
return address, sometimes called the link register (LR).
594
 
595
When the CPU is in supervisor mode, instructions can access both register sets
596
via the {\tt MOV} instruction, whereas when the CPU is in user mode, {\tt MOV}
597
instructions will only offer access to user registers.  We'll discuss this
598
further in subsection.~\ref{sec:isa-mov}.
599
 
600
\subsection{The Status Register, CC}
601
The status register (CC) is special, and bears further mention.  As shown in
602 36 dgisselq
Fig.~\ref{tbl:cc-register},
603
\begin{table}\begin{center}
604
\begin{bitlist}
605 167 dgisselq
31\ldots 23 & R & Reserved for future uses\\\hline
606 199 dgisselq
22\ldots 16 & R/W & Reserved for future uses\\\hline
607
15 & R & Reserved for MMU exceptions\\\hline
608
14 & W & Clear I-Cache command, always reads zero\\\hline
609 167 dgisselq
13 & R & VLIW instruction phase (1 for first half)\\\hline
610 69 dgisselq
12 & R & (Reserved for) Floating Point Exception\\\hline
611
11 & R & Division by Zero Exception\\\hline
612
10 & R & Bus-Error Flag\\\hline
613 167 dgisselq
9 & R & Trap Flag (or user interrupt).  Cleared on return to userspace.\\\hline
614 68 dgisselq
8 & R & Illegal Instruction Flag\\\hline
615 167 dgisselq
7 & R/W & Break--Enable (sCC), or user break (uCC)\\\hline
616 36 dgisselq
6 & R/W & Step\\\hline
617
5 & R/W & Global Interrupt Enable (GIE)\\\hline
618
4 & R/W & Sleep.  When GIE is also set, the CPU waits for an interrupt.\\\hline
619
3 & R/W & Overflow\\\hline
620
2 & R/W & Negative.  The sign bit was set as a result of the last ALU instruction.\\\hline
621
1 & R/W & Carry\\\hline
622
 
623
\end{bitlist}
624
\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
625
\end{center}\end{table}
626 199 dgisselq
the lower sixteen bits of the status register form a set of CPU state and
627
condition codes.  The other bits are reserved for future uses.
628 21 dgisselq
 
629 33 dgisselq
Of the condition codes, the bottom four bits are the current flags:
630 21 dgisselq
                Zero (Z),
631
                Carry (C),
632
                Negative (N),
633
                and Overflow (V).
634 199 dgisselq
These flags maintain their usual definition from other CPUs that use them, for
635
all but the shift right instructions.  On those instructions that set the flags,
636
these flags will be set based upon the output of certain instructions.  If the
637
result is zero, the Z (zero) flag will be set.  If the high order bit is set,
638
the N (negative) flag will be set.  If the instruction caused a bit to fall off
639
the end, the carry bit will be set.  In comparisons, this is equivalent to a
640
less--than unsigned comparison.  Finally, if the instruction causes a signed
641
integer overflow, the V (overflow) flag will be set afterwards.
642 21 dgisselq
 
643 199 dgisselq
We'll walk through the next many bits of the status register in order from
644
least significant to most significant.
645
 
646
\begin{enumerate}
647
        \setcounter{enumi}{3}
648
\item The next bit is a sleep bit.  Set this bit to one to disable instruction
649 69 dgisselq
        execution and place the CPU to sleep, or to zero to keep the pipeline
650
        running.  Setting this bit will cause the CPU to wait for an interrupt
651
        (if interrupts are enabled), or to completely halt (if interrupts are
652 199 dgisselq
        disabled).  This leads to the {\tt WAIT} and {\tt HALT} opcodes
653
        which will be discussed more later.  In order to prevent users from
654
        halting the CPU, only the supervisor is allowed to both put the CPU to
655
        sleep and disable interrupts.  Any user attempt to do so will simply
656
        result in a switch to supervisor mode.
657 33 dgisselq
 
658 199 dgisselq
\item The sixth bit is a global interrupt enable bit (GIE).  This bit also
659
        forms the top, or fifth, bit of any register address.  When this
660 32 dgisselq
        sixth bit is a `1' interrupts will be enabled, else disabled.  When
661 21 dgisselq
        interrupts are disabled, the CPU will be in supervisor mode, otherwise
662
        it is in user mode.  Thus, to execute a context switch, one only
663
        need enable or disable interrupts.  (When an interrupt line goes
664
        high, interrupts will automatically be disabled, as the CPU goes
665 32 dgisselq
        and deals with its context switch.)  Special logic has been added to
666
        keep the user mode from setting the sleep register and clearing the
667
        GIE register at the same time, with clearing the GIE register taking
668
        precedence.
669 21 dgisselq
 
670 199 dgisselq
        Whenever read, the supervisor CC register will always have this bit
671
        cleared, whereas the user CC register will always have this bit set.
672
 
673
\item The seventh bit is a step bit in the user CC register, and zero in the
674
        supervisor CC director.  This bit can only be set from supervisor
675
        mode.  After setting this bit, should the supervisor mode process switch
676
        to user mode, it would then accomplish one instruction in user mode
677
        before returning to supervisor mode.  This bit has no effect
678 69 dgisselq
        on the CPU while in supervisor mode.
679 21 dgisselq
 
680
        This functionality was added to enable a userspace debugger
681
        functionality on a user process, working through supervisor mode
682
        of course.
683
 
684 199 dgisselq
        The CPU can be stepped in supervisor mode.  Doing so requires the
685
        CPU debug functionality, not the step bit.
686 21 dgisselq
 
687
 
688 199 dgisselq
\item The eighth bit is a break enable bit.  When applied to the supervisor CC
689
        register, this controls whether a break instruction in user mode will
690
        halt the processor for an external debugger (break enabled), or
691
        whether the break instruction will simply send send the CPU into
692
        interrupt mode.  This bit can only be set within supervisor mode.
693
        However, when applied to the user CC register, from supervisor mode,
694
        this bit will indicate whether or not the reason the CPU entered
695
        supervisor mode was from a break instruction or not.  This break
696
        reason bit is automatically cleared upon any transition to user mode,
697
        although it can also be cleared by the supervisor writing to the
698
        user CC register.
699 32 dgisselq
 
700 199 dgisselq
        Encountering a break in supervisor mode will halt the CPU independent
701
        of the break enable bit.
702 21 dgisselq
 
703 199 dgisselq
        This functionality was added to enable a debugger to set and manage
704
        breakpoints in a user mode process.
705 21 dgisselq
 
706 199 dgisselq
\item The ninth bit is an illegal instruction bit.  When the CPU tries to
707
        execute either a non-existent instruction, or an instruction from
708
        an address that produces a bus error, the CPU will (if implemented)
709
        switch to supervisor mode while setting this bit.  The bit will
710
        automatically be cleared upon any return to user mode.
711 21 dgisselq
 
712 199 dgisselq
\item The tenth bit is a trap bit.  It is set whenever the user requests a
713
        soft interrupt, and cleared on any return to userspace command.  This
714
        allows the supervisor, in supervisor mode, to determine whether it got
715
        to supervisor mode from a trap, from an external interrupt or both.
716 167 dgisselq
 
717 199 dgisselq
\item The eleventh bit is a bus error flag.  If the user program encountered
718
        a bus error, this bit will be set in the user CC register and the CPU
719
        will switch to supervisor mode.  The bit may be cleared by the
720
        supervisor, otherwise it is automatically cleared upon any return to
721
        user mode.  If the supervisor encounters a bus error, this bit will be
722
        set in the supervisor CC register and the CPU will halt.  In that
723
        case, either a CPU reset or a write to the supervisor CC register will
724
        clear this register.
725 167 dgisselq
 
726 199 dgisselq
\item The twelfth bit is a division by zero exception flag.  This operates
727
        in a fashion similar to the bus error flag.  If the user attempts
728
        to use the divide instruction with a zero denominator, the system
729
        will switch to supervisor mode and set this bit in the user CC
730
        register.  The bit is automatically cleared upon any return to user
731
        mode, although it can also be manually cleared by the supervisor.  In
732
        a similar fashion, if the supervisor attempts to execute a divide by
733
        zero, the CPU will halt and set the zero exception flag in the
734
        supervisor's CC register.  This will automatically be cleared upon any
735
        CPU reset, or it may be manually cleared by the external debugger
736
        writing to this register.
737 167 dgisselq
 
738 199 dgisselq
\item The thirteenth bit will operate in a similar fashion to both the bus
739
        error and division by zero flags, only it will be set upon a (yet to
740
        be determined) floating point error.
741 167 dgisselq
 
742 199 dgisselq
\item In the case of VLIW instructions, if an exception occurs after the first
743
        instruction but before the second, the fourteenth bit of the CC register
744
        will be set to indicate this fact.
745
 
746
\item The fifteenth bit references a clear cache bit.  The supervisor may
747
        write a one to this bit in order to clear the CPU instruction cache.
748
        The bit always reads as a zero.
749
 
750
\item Last, but not least, the sixteenth bit is reserved for a page not found
751
        memory exception to be created by the memory management unit.
752
 
753
\end{enumerate}
754
 
755 167 dgisselq
Some of the upper bits have been temporarily assigned to indicate CPU
756
capabilities.  This is not a permanent feature, as these upper bits officially
757
remain reserved.
758
 
759 199 dgisselq
\subsection{Instruction Format}\label{sec:isa-fmt}
760
All ZipCPU instructions fit in one of the formats shown in
761 69 dgisselq
Fig.~\ref{fig:iset-format}.
762
\begin{figure}\begin{center}
763
\begin{bytefield}[endianness=big]{32}
764
\bitheader{0-31}\\
765
\begin{leftwordgroup}{Standard}\bitbox{1}{0}\bitbox{4}{DR}
766
                \bitbox[lrt]{5}{OpCode}
767
                \bitbox[lrt]{3}{Cnd}
768
                \bitbox{1}{0}
769
                \bitbox{18}{18-bit Signed Immediate} \\
770
\bitbox{1}{0}\bitbox{4}{DR}
771
                \bitbox[lrb]{5}{}
772
                \bitbox[lrb]{3}{}
773
                \bitbox{1}{1}
774
                \bitbox{4}{BR}
775
                \bitbox{14}{14-bit Signed Immediate}\end{leftwordgroup} \\
776
\begin{leftwordgroup}{MOV}\bitbox{1}{0}\bitbox{4}{DR}
777
                \bitbox[lrt]{5}{5'hf}
778
                \bitbox[lrt]{3}{Cnd}
779
                \bitbox{1}{A}
780
                \bitbox{4}{BR}
781
                \bitbox{1}{B}
782
                \bitbox{13}{13-bit Signed Immediate}\end{leftwordgroup} \\
783
\begin{leftwordgroup}{LDI}\bitbox{1}{0}\bitbox{4}{DR}
784
                \bitbox{4}{4'hb}
785
                \bitbox{23}{23-bit Signed Immediate}\end{leftwordgroup} \\
786
\begin{leftwordgroup}{NOOP}\bitbox{1}{0}\bitbox{3}{3'h7}
787
                \bitbox{1}{}
788
                \bitbox{2}{11}
789
                \bitbox{3}{xxx}
790
                \bitbox{22}{Ignored}
791
                \end{leftwordgroup} \\
792
\begin{leftwordgroup}{VLIW}\bitbox{1}{1}\bitbox[lrt]{4}{DR}
793
                \bitbox[lrt]{5}{OpCode}
794
                \bitbox[lrt]{3}{Cnd}
795
                \bitbox{1}{0}
796
                \bitbox{4}{Imm.}
797
                \bitbox{14}{---} \\
798
\bitbox{1}{1}\bitbox[lr]{4}{}
799
                \bitbox[lrb]{5}{}
800
                \bitbox[lr]{3}{}
801
                \bitbox{1}{1}
802
                \bitbox{4}{BR}
803
                \bitbox{14}{---}        \\
804
\bitbox{1}{1}\bitbox[lrb]{4}{}
805
                \bitbox{4}{4'hb}
806
                \bitbox{1}{}
807
                \bitbox[lrb]{3}{}
808
                \bitbox{5}{5'b Imm}
809
                \bitbox{14}{---}        \\
810
\bitbox{1}{1}\bitbox{9}{---}
811
                \bitbox[lrt]{3}{Cnd}
812
                \bitbox{5}{---}
813
                \bitbox[lrt]{4}{DR}
814
                \bitbox[lrt]{5}{OpCode}
815
                \bitbox{1}{0}
816
                \bitbox{4}{Imm}
817
                \\
818
\bitbox{1}{1}\bitbox{9}{---}
819
                \bitbox[lr]{3}{}
820
                \bitbox{5}{---}
821
                \bitbox[lr]{4}{}
822
                \bitbox[lrb]{5}{}
823
                \bitbox{1}{1}
824
                \bitbox{4}{Reg} \\
825
\bitbox{1}{1}\bitbox{9}{---}
826
                \bitbox[lrb]{3}{}
827
                \bitbox{5}{---}
828
                \bitbox[lrb]{4}{}
829
                \bitbox{4}{4'hb}
830
                \bitbox{1}{}
831
                \bitbox{5}{5'b Imm}
832
                \end{leftwordgroup} \\
833
\end{bytefield}
834
\caption{Zip Instruction Set Format}\label{fig:iset-format}
835
\end{center}\end{figure}
836
The basic format is that some operation, defined by the OpCode, is applied
837
if a condition, Cnd, is true in order to produce a result which is placed in
838 199 dgisselq
the destination register (DR).  There are three basic exceptions to this
839
model.  The first is the {\tt MOV} instruction, which steals bits~13 and~18
840
to allow supervisor access to user registers.  The second is the load 23--bit
841
signed immediate instruction ({\tt LDI}), in that it accepts no conditions and
842
uses only a 4-bit opcode.  The last exception is the {\tt NOOP} instruction
843
group, containing the {\tt NOOP}, {\tt BREAK}, and {\tt LOCK} opcodes.  These
844
instructions ignore their register and immediate settings.\footnote{A future
845
version of the CPU may repurpose the immediate bits within the {\tt NOOP}
846
instruction to be simulator commands, while the immediate/register bits within
847
the {\tt BREAK} instruction may be used by the debugger for whatever purpose
848
it chooses to use them for--such as a breakpoint table index.}
849 69 dgisselq
 
850 199 dgisselq
The ZipCPU also supports a very long instruction word (VLIW) set of
851
instructions.  These aren't truly VLIW instructions in the sense that the CPU
852
still only issues one instruction at a time, but they do pack two instructions
853
into a single instuction word.  The number of bits used by the immediate field
854
are adjusted to make space for these instruction words.  Other than instruction
855
format, the only basic difference between VLIW and normal instructions is that
856
the CPU will not switch to interrupt mode in between the two instructions,
857
unless an exception is generated by the first instruction.  Likewise a new job
858
given to the assembler is that of automatically packing as many instructions as
859
possible into the VLIW format.
860 69 dgisselq
 
861 199 dgisselq
The disassembler will represent VLIW instructions by placing a vertical bar
862
between the two components, but still leaving them on the same line.
863 69 dgisselq
 
864 199 dgisselq
\subsection{Instruction OpCodes}\label{sec:isa-opcodes}
865 69 dgisselq
With a 5--bit opcode field, there are 32--possible instructions as shown in
866
Tbl.~\ref{tbl:iset-opcodes}.
867
\begin{table}\begin{center}
868
\begin{tabular}{|l|l|l|c|} \hline \rowcolor[gray]{0.85}
869
OpCode & & Instruction &Sets CC \\\hline\hline
870 199 dgisselq
5'h00 & {\tt SUB} & Subtract &   \\\cline{1-3}
871
5'h01 & {\tt AND} & Bitwise And &   \\\cline{1-3}
872
5'h02 & {\tt ADD} & Add two numbers &   \\\cline{1-3}
873
5'h03 & {\tt OR}  & Bitwise Or & Y \\\cline{1-3}
874
5'h04 & {\tt XOR} & Bitwise Exclusive Or &   \\\cline{1-3}
875
5'h05 & {\tt LSR} & Logical Shift Right &   \\\cline{1-3}
876
5'h06 & {\tt LSL} & Logical Shift Left &   \\\cline{1-3}
877
5'h07 & {\tt ASR} & Arithmetic Shift Right &   \\\hline
878
5'h08 & {\tt MPY} & 32x32 bit multiply & Y \\\hline
879
5'h09 & {\tt LDILO} & Load Immediate Low & N\\\hline
880
5'h0a & {\tt MPYUHI} & Upper 32 of 64 bits from an unsigned 32x32 multiply &  \\\cline{1-3}
881
5'h0b & {\tt MPYSHI} & Upper 32 of 64 bits from a signed 32x32 multiply & Y \\\cline{1-3}
882
5'h0c & {\tt BREV} & Bit Reverse B operand into result&  \\\cline{1-3}
883
5'h0d & {\tt POPC}& Population Count &  \\\cline{1-3}
884
5'h0e & {\tt ROL} & Rotate Ra left by OpB bits&   \\\hline
885
5'h0f & {\tt MOV} & Move OpB into Ra & N \\\hline
886
5'h10 & {\tt CMP} & Compare (Ra-OpB) to zero & Y \\\cline{1-3}
887
5'h11 & {\tt TST} & Test (AND w/o setting result) &   \\\hline
888
5'h12 & {\tt LOD} & Load Ra from memory (OpB) & N \\\cline{1-3}
889
5'h13 & {\tt STO} & Store Ra into memory at (OpB) &  \\\hline\hline
890
5'h14 & {\tt DIVU} & Divide, unsigned & Y \\\cline{1-3}
891
5'h15 & {\tt DIVS} & Divide, signed &  \\\hline\hline
892
5'h16/7 & {\tt LDI} & Load 23--bit signed immediate & N \\\hline\hline
893
5'h18 & {\tt FPADD} & Floating point add &  \\\cline{1-3}
894
5'h19 & {\tt FPSUB} & Floating point subtract &   \\\cline{1-3}
895
5'h1a & {\tt FPMPY} & Floating point multiply & Y \\\cline{1-3}
896
5'h1b & {\tt FPDIV} & Floating point divide &   \\\cline{1-3}
897
5'h1c & {\tt FPI2F} & Convert integer to floating point &   \\\cline{1-3}
898
5'h1d & {\tt FPF2I} & Convert floating point to integer &   \\\hline
899 69 dgisselq
5'h1e & & {\em Reserved for future use} &\\\hline
900
5'h1f & & {\em Reserved for future use} &\\\hline
901 199 dgisselq
5'h18 & & \hbox to 0.5in{\tt NOOP}  (A-register = PC)&\\\cline{1-3}
902
5'h19 & & \hbox to 0.5in{\tt BREAK} (A-register = PC)& N\\\cline{1-3}
903
5'h1a & & \hbox to 0.5in{\tt LOCK}  (A-register = PC)&\\\hline
904 39 dgisselq
\end{tabular}
905 199 dgisselq
\caption{ZipCPU OpCodes}\label{tbl:iset-opcodes}
906 39 dgisselq
\end{center}\end{table}
907 69 dgisselq
%
908 199 dgisselq
Of these opcodes, {\tt ROL} and {\tt POPC} are experimental and may be
909
replaced in future revisions.  (If you have a reason to like or wish to keep
910
these opcodes, please contact me.  If you know of alternatives that might be
911
better, please let me know as well.)  There is also room for six more
912
register-less instructions in the {\tt NOOP} instruction space,
913
and two floating point instruction opcodes have been reserved for future use.
914 39 dgisselq
 
915 199 dgisselq
\subsection{Conditional Instructions}\label{sec:isa-cond}
916 69 dgisselq
Most, although not quite all, instructions may be conditionally executed.
917
The 23--bit load immediate instruction, together with the {\tt NOOP},
918 199 dgisselq
{\tt BREAK}, and {\tt LOCK} instructions are the exceptions to this rule.
919
All other instructions may be conditionally executed.
920 69 dgisselq
 
921
From the four condition code flags, eight conditions are defined for standard
922
instructions.  These are shown in Tbl.~\ref{tbl:conditions}.
923
\begin{table}\begin{center}
924 21 dgisselq
\begin{tabular}{l|l|l}
925 199 dgisselq
Code & Mnemonic & Condition \\\hline
926 21 dgisselq
3'h0 & None & Always execute the instruction \\
927 199 dgisselq
3'h1 & {\tt .LT}& Less than ('N' set) \\
928 69 dgisselq
3'h2 & {\tt .Z} & Only execute when 'Z' is set \\
929 199 dgisselq
3'h3 & {\tt .NZ}& Only execute when 'Z' is not set \\
930
3'h4 & {\tt .GT}& Greater than ('N' not set, 'Z' not set) \\
931
3'h5 & {\tt .GE}& Greater than or equal ('N' not set, 'Z' irrelevant) \\
932 139 dgisselq
3'h6 & {\tt .C} & Carry set (Also known as less-than unsigned) \\
933 21 dgisselq
3'h7 & {\tt .V} & Overflow set\\
934
\end{tabular}
935
\caption{Conditions for conditional operand execution}\label{tbl:conditions}
936 69 dgisselq
\end{center}\end{table}
937
There is no condition code for less than or equal, not C or not V---there
938 199 dgisselq
just wasn't enough space in 3--bits.  Ways of handling non--supported
939
conditions are discussed in Sec.~\ref{sec:in-mcond}.
940 21 dgisselq
 
941 199 dgisselq
With the exception of \hbox{\tt CMP} and \hbox{\tt TST} instructions,
942
conditionally executed instructions will not further adjust the condition codes.
943
Conditional \hbox{\tt CMP} or \hbox{\tt TST} instructions will adjust conditions
944
whenever they are executed.  In this way, multiple conditions may be evaluated
945
without branches, creating a sort of logical and--but only if all the conditions
946
are the same.  For example, to do something if \hbox{\tt R0} is one and
947
\hbox{\tt R1} is two, one might try code such as Tbl.~\ref{tbl:dbl-condition}.
948 68 dgisselq
\begin{table}\begin{center}
949
\begin{tabular}{l}
950
        {\tt CMP 1,R0} \\
951 199 dgisselq
        {\em ; Condition codes are now set based upon R0-1} \\
952 68 dgisselq
        {\tt CMP.Z 2,R1} \\
953 199 dgisselq
        {\em ; If R0 $\neq$ 1, conditions are unchanged, {\tt Z} is still false.} \\
954
        {\em ; If R0 $=$ 1, conditions are now set based upon R1-2.} \\
955
        {\em ; Now some instruction could be done based upon the conjunction} \\
956
        {\em ; of both conditions.} \\
957
        {\em ; While we use the example of a {\tt STO}, it could easily be any
958
                instruction.} \\
959 68 dgisselq
        {\tt STO.Z R0,(R2)} \\
960
\end{tabular}
961
\caption{An example of a double conditional}\label{tbl:dbl-condition}
962
\end{center}\end{table}
963 36 dgisselq
 
964 199 dgisselq
The real utility of conditionally executed instructions is that, unlike
965
conditional branches, conditionally executed instructions will not stall
966
the bus if they are not executed.
967
 
968 69 dgisselq
In the case of VLIW instructions, only four conditions are defined as shown
969
in Tbl.~\ref{tbl:vliw-conditions}.
970
\begin{table}\begin{center}
971
\begin{tabular}{l|l|l}
972 199 dgisselq
Code & Mnemonic & Condition \\\hline
973 69 dgisselq
2'h0 & None & Always execute the instruction \\
974
2'h1 & {\tt .LT} & Less than ('N' set) \\
975
2'h2 & {\tt .Z} & Only execute when 'Z' is set \\
976
2'h3 & {\tt .NZ} & Only execute when 'Z' is not set \\
977
\end{tabular}
978
\caption{VLIW Conditions}\label{tbl:vliw-conditions}
979
\end{center}\end{table}
980 199 dgisselq
Further, the first bit of the three is given a special meaning: If the first
981
bit is set, the conditions apply to the second half of the instruction,
982
otherwise the conditions will only apply to the first half of a conditional
983
instruction.  Of course, the other conditions are still available by mingling
984
the non--VLIW instructions with VLIW instructions.
985 68 dgisselq
 
986 199 dgisselq
\subsection{Modifying Conditions}\label{sec:in-mcond}
987
A quick look at the list of conditions supported by the ZipCPU and listed
988
in Tbl.~\ref{tbl:conditions} reveals that the ZipCPU does not have a full set
989 139 dgisselq
of conditions.  In particular, only one explicit unsigned condition is
990
supported.  Therefore, Tbl.~\ref{tbl:creating-conditions}
991
\begin{table}\begin{center}
992
\begin{tabular}{|l|l|l|}\hline
993
Original & Modified & Name \\\hline\hline
994
\parbox[t]{1.5in}{\tt CMP Rx,Ry\\BLE label} % If Ry <= Rx -> Ry < Rx+1
995
        & \parbox[t]{1.5in}{\tt CMP 1+Rx,Ry\\BLT label}
996
        & Less-than or equal (signed, {\tt Z} or {\tt N} set)\\[4mm]\hline
997
\parbox[t]{1.5in}{\tt CMP Rx,Ry\\BLEU label}
998
        & \parbox[t]{1.5in}{\tt CMP 1+Rx,Ry\\BC label}
999
        & Less-than or equal unsigned \\[4mm]\hline
1000
\parbox[t]{1.5in}{\tt CMP Rx,Ry\\BGTU label}    % if (Ry > Rx) -> Rx < Ry
1001
        & \parbox[t]{1.5in}{\tt CMP Ry,Rx\\BC label}
1002
        & Greater-than unsigned \\[4mm]\hline
1003
\parbox[t]{1.5in}{\tt CMP Rx,Ry\\BGEU label}    % if (Ry >= Rx) -> Rx <= Ry -> Rx < Ry+1
1004
        & \parbox[t]{1.5in}{\tt CMP 1+Ry,Rx\\BC label}
1005
        & Greater-than equal unsigned \\[4mm]\hline
1006
\parbox[t]{1.5in}{\tt CMP A+Rx,Ry\\BGEU label} % if (Ry >= A+Rx)-> A+Rx <= Ry -> Rx < Ry+1-A
1007
        & \parbox[t]{1.5in}{\tt CMP (1-A)+Ry,Rx\\BC label}
1008
        & Greater-than equal unsigned (with offset)\\[4mm]\hline
1009
\parbox[t]{1.5in}{\tt CMP A,Ry\\BGEU label} % if (Ry >= A+Rx)-> A+Rx <= Ry -> Rx < Ry+1-A
1010
        & \parbox[t]{1.5in}{\tt LDI (A-1),Rx\\CMP Ry,Rx\\BC label}
1011
        & Greater-than equal comparison with a constant\\[4mm]\hline
1012
\end{tabular}
1013
\caption{Modifying conditions}\label{tbl:creating-conditions}
1014
\end{center}\end{table}
1015
shows examples of how these unsupported conditions can be created
1016
simply by adjusting the compare instruction, for no extra cost in clocks.
1017
Of course, if the compare originally had an immediate within it, that immediate
1018 199 dgisselq
would need to be loaded into a register in order to do make some of these
1019
adjustments.  That case is shown as the last case above.
1020 139 dgisselq
 
1021 199 dgisselq
Many of these alternate conditions are chosen by the compiler implementation.
1022 21 dgisselq
 
1023 199 dgisselq
Users should be aware of any signed overflow that might take place within the
1024
modified conditions, especially when numbers close to the limit are used.
1025 21 dgisselq
 
1026
 
1027 199 dgisselq
\subsection{Operand B}\label{sec:isa-opb}
1028
Many instruction forms have a 19-bit source ``Operand B'', or OpB for short,
1029
associated with them.  This ``Operand B'' is shown in
1030
Fig.~\ref{fig:iset-format} as part of the standard instructions.  An Operand B
1031
is either equal to a register plus a 14--bit signed immediate offset, or an
1032
18--bit signed immediate offset by itself.  This value is encoded as shown in
1033
Tbl.~\ref{tbl:opb}.
1034
\begin{table}\begin{center}
1035
\begin{bytefield}[endianness=big]{19}
1036
\bitheader{0-18}  \\
1037
\bitbox{1}{0}\bitbox{18}{18-bit Signed Immediate} \\
1038
\bitbox{1}{1}\bitbox{4}{Reg}\bitbox{14}{14-bit Signed Immediate}
1039
\end{bytefield}
1040
\caption{Bit allocation for Operand B}\label{tbl:opb}
1041
\end{center}\end{table}
1042
This format represents a deviation from many other RISC architectures that use
1043
{\tt R0} to represent zero, such as OpenRISC and RISC-V.  Here, instead, we use
1044
a bit within the instruction to note whether or not an immediate is used.
1045
The result is that ZipCPU instructions can encode larger immediates within their
1046
instruction space.
1047 139 dgisselq
 
1048 199 dgisselq
In those cases where a fourteen or eighteen bit immediate doesn't make sense,
1049
such as for {\tt LDILO}, the extra bits associated with the immediate are
1050
simply ignored.  (This rule does not apply to the shift instructions,
1051
{\tt ASR}, {\tt LSR}, and {\tt LSL}--which all use all of their immediate bits.)
1052
 
1053
VLIW instructions still use the same operand B as regular instructions, only
1054
there was no room for any instruction plus immediate addressing.  Therefore,
1055
VLIW instructions have either
1056
a register or a 4--bit signed immediate as their operand B.  The only exception
1057
is the load immediate instruction, which permits a 5--bit signed operand
1058
B.\footnote{Although the space exists to extend this VLIW load immediate
1059
instruction to six bits, the 5--bit limit was chosen to simplify the
1060
disassembler.  This may change in the future.}
1061
 
1062
\subsection{Address Modes}\label{sec:isa-addr}
1063
The ZipCPU supports two addressing modes: register plus immediate, and
1064
immediate addressing.  Addresses are encoded in the same fashion as
1065
Operand B's, discussed above.
1066
 
1067
The VLIW instruction set only offers register addressing.
1068
 
1069
\subsection{Move Operands}\label{sec:isa-mov}
1070
The previous set of operands would be perfect and complete, save only that the
1071
CPU needs access to non--supervisory registers while in supervisory mode.  The
1072
MOV instruction has been modified to fit that purpose.  The two bits,
1073
shown as {\tt A} and {\tt B} in Fig.~\ref{fig:iset-format} above, are designed
1074
to contain the high order bit of the 5--bit register index.  If the {\tt B}
1075
bit is a `1', the source operand comes from the user register set.  If the
1076
{\tt A} bit is a `1', the destination operand is in the user register set.  A
1077
zero bit indicates the current register set.
1078
 
1079
This encoding has been chosen to keep the compiler simple.  For the most part,
1080
the extra bits are quietly set to zero by the compiler.  Assembly instructions,
1081
or particular built--in instructions, can be used to get access to these
1082
cross register set move instructions.
1083
 
1084
Further, the {\tt MOV} instruction lacks the full OpB capability to use a
1085
register or a register plus immediate as a source, since a load immediate
1086
instruction already exists.  As a result, all moves come from a register plus a
1087
potential offset.
1088
 
1089
\subsection{Multiply Operations}\label{sec:isa-mpy}
1090
 
1091
The ZipCPU supports three separate 32x32-bit multiply
1092 139 dgisselq
instructions: {\tt MPY}, {\tt MPYUHI}, and {\tt MPYSHI}.  The first of these
1093
produces the low 32-bits of a 32x32-bit multiply result.  The second two
1094
produce the upper 32-bits.  The first, {\tt MPYUHI}, produces the upper 32-bits
1095 199 dgisselq
assuming the multiply was unsigned, whereas {\tt MPYSHI} assumes it was signed.
1096
Each multiply instruction is independent of every other in execution, although
1097
the compiler is likely to use them in a dependent fashion.
1098 139 dgisselq
 
1099 199 dgisselq
In an effort to maintain a fast clock speed, all three of these multiplies
1100
have been slowed down in logic.  Thus, depending upon the setting of
1101
{\tt OPT\_MULTIPLY} within {\tt cpudefs.v}, or the corresponding
1102
{\tt IMPLEMENT\_MPY} parameter that may override it, the multiply instructions
1103
will either 1)~cause an ILLEGAL instruction error ({\tt OPT\_MULTIPLY=0}, or
1104
no multiply support), 2)~take one additional clock ({\tt OPT\_MULTIPLY=2}),
1105
or 3)~take two additional clock cycles ({\tt OPT\_MULTIPLY=3}).\footnote{Support
1106
also exists for a one clock multiply (no clock slowdown), or a four clock
1107
multiply, and I am anticipating supporting a much longer multiply for FPGA
1108
architectures with no accelerated hardware multiply support.}
1109 139 dgisselq
 
1110 199 dgisselq
\subsection{Divide Unit}
1111
The ZipCPU also has an optional divide unit which can be built alongside the
1112
ALU.  This divide unit provides the ZipCPU with another two instructions that
1113 69 dgisselq
cannot be executed in a single cycle: {\tt DIVS}, or signed divide, and
1114
{\tt DIVU}, the unsigned divide.  These are both 32--bit divide instructions,
1115
dividing one 32--bit number by another.  In this case, the Operand B field,
1116
whether it be register or register plus immediate, constitutes the denominator,
1117
whereas the numerator is given by the other register.
1118 21 dgisselq
 
1119 199 dgisselq
As with the multiply, the divide instructions are also a multi--clock
1120
instructions.  While the divide is running, the ALU, any memory loads, and the
1121
floating point unit (if installed) will be idle.  Once the divide completes,
1122
other units may continue.
1123 21 dgisselq
 
1124 199 dgisselq
Of course, any divide instruction can result in a division by zero exception.
1125
If this happens the CPU will either suddenly transition from user mode to
1126
supervisor mode, or it will halt if the CPU is already in supervisor mode.  Upon
1127
exception, the divide by zero bit will be set in the CC register.  In the
1128
case of a user mode divide by zero, this will be cleared by any return to user
1129
mode command.  The supervisor bit may be cleared either by a reboot or by the
1130
external debugger.
1131 32 dgisselq
 
1132 199 dgisselq
\subsection{NOOP, BREAK, and Bus LOCK Instruction}
1133 139 dgisselq
Three instructions within the opcode list in Tbl.~\ref{tbl:iset-opcodes}, are
1134 199 dgisselq
somewhat special.  These are the {\tt NOOP}, {\tt BREAK}, and bus {\tt LOCK}
1135 139 dgisselq
instructions.  These are encoded according to
1136 199 dgisselq
Fig.~\ref{fig:iset-noop}.
1137 69 dgisselq
\begin{figure}\begin{center}
1138
\begin{bytefield}[endianness=big]{32}
1139
\bitheader{0-31}\\
1140
\begin{leftwordgroup}{NOOP}
1141
\bitbox{1}{0}\bitbox{3}{3'h7}\bitbox{1}{}
1142 199 dgisselq
        \bitbox{2}{11}\bitbox{3}{000}\bitbox{22}{Reserved for Simulator} \\
1143 69 dgisselq
\bitbox{1}{1}\bitbox{3}{3'h7}\bitbox{1}{}
1144 139 dgisselq
        \bitbox{2}{11}\bitbox{3}{000}\bitbox{22}{---} \\
1145 69 dgisselq
\bitbox{1}{1}\bitbox{9}{---}\bitbox{3}{---}\bitbox{5}{---}
1146
        \bitbox{3}{3'h7}\bitbox{1}{}\bitbox{2}{11}\bitbox{3}{001}
1147 199 dgisselq
        \bitbox{5}{Rsrvd}
1148 69 dgisselq
                \end{leftwordgroup} \\
1149
\begin{leftwordgroup}{BREAK}
1150
\bitbox{1}{0}\bitbox{3}{3'h7}
1151 199 dgisselq
                \bitbox{1}{}\bitbox{2}{11}\bitbox{3}{001}\bitbox{22}{Reserved for debugger}
1152 69 dgisselq
                \end{leftwordgroup} \\
1153
\begin{leftwordgroup}{LOCK}
1154
\bitbox{1}{0}\bitbox{3}{3'h7}
1155 139 dgisselq
                \bitbox{1}{}\bitbox{2}{11}\bitbox{3}{010}\bitbox{22}{Ignored}
1156 69 dgisselq
                \end{leftwordgroup} \\
1157
\end{bytefield}
1158
\caption{NOOP/Break/LOCK Instruction Format}\label{fig:iset-noop}
1159
\end{center}\end{figure}
1160 32 dgisselq
 
1161 69 dgisselq
The {\tt NOOP} instruction is just that: an instruction that does not perform
1162 199 dgisselq
any operation.  While many other instructions, such as a move from a register
1163
to itself, could also fit this role, only the NOOP instruction guarantees
1164
that it will not stall waiting for a register to be available.   For this
1165
reason, it gets its own place in the instruction set.  Bits 21--0 of this
1166
instruction are reserved for commands which may be given to a simulator, such
1167
as simulator exit, should the code be run from a simulator.  However, such
1168
simulation codes have not yet been defined.
1169 32 dgisselq
 
1170 69 dgisselq
The {\tt BREAK} instruction is useful for creating a debug instruction that
1171
will halt the CPU without executing.  If in user mode, depending upon the
1172
setting of the break enable bit, it will either switch to supervisor mode or
1173 199 dgisselq
halt the CPU--depending upon where the user wishes to do his debugging.  The
1174
lower 22~bits of this instruction are likewise reserved for the debuggers
1175
use.
1176 21 dgisselq
 
1177 139 dgisselq
Finally, the {\tt LOCK} instruction was added in order to provide for
1178 199 dgisselq
atomic operations.  The {\tt LOCK} instruction only works when the CPU is
1179
configured for pipeline mode.  It works by stalling the ALU pipeline stack
1180
until all prior stages are filled, and then it guarantees that once a bus
1181
cycle is started, the wishbone {\tt CYC} line will remain asserted until the
1182
LOCK is deasserted.  This allows the execution of three instructions, one
1183
memory (ex. {\tt LOD}), one ALU (ex. {\tt ADD}), and another memory instruction
1184
(ex. {\tt STO}), to take place in an unbreakable fashion.  Example uses of this
1185
capability include an atomic increment, such as {\tt LOCK}, {\tt LOD (Rx),Ry},
1186
{\tt ADD \#,Ry}, and then {\tt STO Ry,(Rx)}, or even a two instruction pair
1187
such as a test and set sequence: {\tt LDI 1,Rz}, {\tt LOCK}, {\tt LOD (Rx),Ry},
1188
{\tt STO Rz,(Rx)}.
1189 21 dgisselq
 
1190 199 dgisselq
\subsection{Floating Point}
1191
Although the ZipCPU does not (yet) have a floating point unit, the current
1192 69 dgisselq
instruction set offers eight opcodes for floating point operations, and treats
1193
floating point exceptions like divide by zero errors.  Once this unit is built
1194 199 dgisselq
and integrated together with the rest of the CPU, the ZipCPU will support
1195 69 dgisselq
32--bit floating point instructions natively.  Any 64--bit floating point
1196 199 dgisselq
instructions will either need to be emulated in software, or else they will
1197
need an external floating point peripheral.
1198 69 dgisselq
 
1199 199 dgisselq
Until the FPU is built and integrated, of even afterwards if the floating point
1200
unit is not installed by option, floating point instructions will trigger an
1201
illegal instruction exception, which may be trapped and then implemented in
1202
software.
1203 139 dgisselq
 
1204 199 dgisselq
\subsection{Load/Store byte}
1205
One difference between the ZipCPU and many other architectures is that there are
1206
no load byte {\tt LB}, store byte {\tt SB}, load halfword {\tt LH} or store
1207
halfword {\tt SH} instructions.  This lack is by design in an attempt to keep
1208
the 32--bit bus simple.
1209
 
1210
Because the ZipCPU's addresses refer to 32--bit values, i.e. address one
1211
will refer to a completely different 32--bit value than address two, simulating
1212
these load and store byte instructions is difficult.
1213
 
1214
This is just the nature of the ZipCPU, as a result of the design choices that
1215
were made.
1216
 
1217
\subsection{Derived Instructions}
1218
The ZipCPU supports many other common instructions by construction, although
1219
not all of them are single cycle instructions.  Tables~\ref{tbl:derived-1}, \ref{tbl:derived-2}, \ref{tbl:derived-3} and~\ref{tbl:derived-4} show how these
1220
other instructions may be implemented on the ZipCPU.  Many of these
1221
instructions will have assembly equivalents,
1222 21 dgisselq
such as the branch instructions, to facilitate working with the CPU.
1223
\begin{table}\begin{center}
1224
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
1225
Mapped & Actual  & Notes \\\hline
1226 39 dgisselq
{\tt ABS Rx}
1227
        & \parbox[t]{1.5in}{\tt TST -1,Rx\\NEG.LT Rx}
1228 199 dgisselq
        & Absolute value, depends upon the derived {\tt NEG} instruction
1229
        below, and so this expands into three instructions total.\\\hline
1230 39 dgisselq
\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
1231
        & \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
1232 21 dgisselq
        & Add with carry \\\hline
1233 199 dgisselq
{\tt BRA.$x$ +/-\$Addr}
1234
        & \hbox{\tt ADD.$x$ \$Addr+PC,PC}
1235
        & Branch or jump on condition $x$.  Works for 18--bit
1236 24 dgisselq
                signed address offsets.\\\hline
1237 199 dgisselq
% {\tt BRA.Cond +/-\$Addr}
1238
%       & \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
1239
%       & Branch/jump on condition.  Works for 23 bit address offsets, but
1240
%       costs a register and an extra instruction.  With LDIHI and LDILO
1241
%       this can be made to work anywhere in the 32-bit address space, but yet
1242
%       cost an additional instruction still. \\\hline
1243
% {\tt BNC PC+\$Addr}
1244
%       & \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ ADD.Z PC+\$Addr,PC}
1245
%       & Example of a branch on an unsupported
1246
%               condition, in this case a branch on not carry \\\hline
1247
{\tt BUSY } & {\tt ADD \$-1,PC} & Execute an infinite loop.  This is used
1248
        within ZipCPU simulations as the execute simulation on error
1249
        instruction. \\\hline
1250 39 dgisselq
{\tt CLRF.NZ Rx }
1251
        & {\tt XOR.NZ Rx,Rx}
1252 21 dgisselq
        & Clear Rx, and flags, if the Z-bit is not set \\\hline
1253 39 dgisselq
{\tt CLR Rx }
1254
        & {\tt LDI \$0,Rx}
1255 199 dgisselq
        & Clears Rx, leaving the flags untouched.  This instruction cannot be
1256 21 dgisselq
                conditional. \\\hline
1257 199 dgisselq
{\tt CLR.NZ Rx }
1258
        & {\tt BREV.NZ \$0,Rx}
1259
        & Clears Rx, leaving the flags untouched.  This instruction can be
1260
                executed conditionally. The assembler will quietly  choose
1261
                between {\tt LDI} and {\tt BREV} depending upon the existence
1262
                of the condition.\\\hline
1263 39 dgisselq
{\tt EXCH.W Rx }
1264
        & {\tt ROL \$16,Rx}
1265 21 dgisselq
        & Exchanges the top and bottom 16'bit words of Rx \\\hline
1266 39 dgisselq
{\tt HALT }
1267
        & {\tt Or \$SLEEP,CC}
1268
        & This only works when issued in interrupt/supervisor mode.  In user
1269 199 dgisselq
        mode this is simply a wait until interrupt instruction.
1270
 
1271
        This is also used within the simulator as an exit simulation on
1272
        success instruction.\\\hline
1273 69 dgisselq
{\tt INT } & {\tt LDI \$0,CC} & This is also known as a trap instruction\\\hline
1274 39 dgisselq
{\tt IRET}
1275
        & {\tt OR \$GIE,CC}
1276
        & Also known as an RTU instruction (Return to Userspace) \\\hline
1277 92 dgisselq
{\tt JMP R6+\$Offset}
1278
        & {\tt MOV \$Offset(R6),PC}
1279 199 dgisselq
        & Only works for 13--bit offsets.  Other offsets require adding the
1280
        offset first to R6 before jumping.\\\hline
1281 69 dgisselq
{\tt LJMP \$Addr}
1282
        & \parbox[t]{1.5in}{\tt LOD (PC),PC \\ {\em Address }}
1283
        & Although this only works for an unconditional jump, and it only
1284 199 dgisselq
        works in an architecture with a unified instruction and data address
1285
        space, this instruction combination makes for a nice combination that
1286
        can be adjusted by a linker at a later time.\\\hline
1287
{\tt LJMP.x \$Addr}
1288
        & \parbox[t]{1.5in}{\tt LOD.x 2(PC),PC \\ ADD 1,PC \\ {\em Address }}
1289
        & Long jump, works for a conditional long jump.  \\\hline
1290
\end{tabular}
1291
\caption{Derived Instructions}\label{tbl:derived-1}
1292
\end{center}\end{table}
1293
\begin{table}\begin{center}
1294
\begin{tabular}{p{1.1in}p{1.8in}p{3in}}\\\hline
1295
Mapped & Actual  & Notes \\\hline
1296
{\tt LJSR \$Addr  }
1297
        & \parbox[t]{1.5in}{\tt MOV \$2+PC,R0 \\ LOD (PC),PC \\ {\em Address}}
1298
        & Similar to LJMP, but it handles the return address properly.
1299
        \\\hline
1300 92 dgisselq
{\tt JSR PC+\$Offset  }
1301
        & \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ ADD \$Offset,PC}
1302 69 dgisselq
        & This is similar to the jump and link instructions from other
1303
        architectures, save only that it requires a specific link
1304 199 dgisselq
        instruction, seen here as the {\tt MOV} instruction on the
1305 69 dgisselq
        left.\\\hline
1306 199 dgisselq
{\tt LDI \$val,Rx }
1307
        & \parbox[t]{1.8in}{\tt BREV REV($val$)\&0x0ffff, Rx \\
1308
                        LDILO ($val$\&0x0ffff),Rx}
1309 69 dgisselq
        & \parbox[t]{3.0in}{Sadly, there's not enough instruction
1310 21 dgisselq
                space to load a complete immediate value into any register.
1311
                Therefore, fully loading any register takes two cycles.
1312 199 dgisselq
                The {\tt LDILO} (load immediate low) instruction has been
1313
                created to facilitate this together with {\tt BREV}.
1314 69 dgisselq
                \\
1315
        This is also the appropriate means for setting a register value
1316
        to an arbitrary 32--bit value in a post--assembly link
1317
        operation.}\\\hline
1318 39 dgisselq
{\tt LOD.b \$addr,Rx}
1319
        & \parbox[t]{1.5in}{\tt %
1320 21 dgisselq
        LDI     \$addr,Ra \\
1321
        LDI     \$addr,Rb \\
1322
        LSR     \$2,Ra \\
1323
        AND     \$3,Rb \\
1324
        LOD     (Ra),Rx \\
1325
        LSL     \$3,Rb \\
1326
        SUB     \$32,Rb \\
1327
        ROL     Rb,Rx \\
1328
        AND \$0ffh,Rx}
1329
        & \parbox[t]{3in}{This CPU is designed for 32'bit word
1330
        length instructions.  Byte addressing is not supported by the CPU or
1331
        the bus, so it therefore takes more work to do.
1332
 
1333
        Note also that in this example, \$Addr is a byte-wise address, where
1334 24 dgisselq
        all other addresses in this document are 32-bit wordlength addresses.
1335
        For this reason,
1336 21 dgisselq
        we needed to drop the bottom two bits.  This also limits the address
1337
        space of character accesses using this method from 16 MB down to 4MB.}
1338
                \\\hline
1339 39 dgisselq
\parbox[t]{1.5in}{\tt LSL \$1,Rx\\ LSLC \$1,Ry}
1340
        & \parbox[t]{1.5in}{\tt LSL \$1,Ry \\
1341 21 dgisselq
        LSL \$1,Rx \\
1342
        OR.C \$1,Ry}
1343
        & Logical shift left with carry.  Note that the
1344
        instruction order is now backwards, to keep the conditions valid.
1345 33 dgisselq
        That is, LSL sets the carry flag, so if we did this the other way
1346 21 dgisselq
        with Rx before Ry, then the condition flag wouldn't have been right
1347 199 dgisselq
        for an {\tt OR} correction at the end. \\\hline
1348 39 dgisselq
\parbox[t]{1.5in}{\tt LSR \$1,Rx \\ LSRC \$1,Ry}
1349
        & \parbox[t]{1.5in}{\tt CLR Rz \\
1350 21 dgisselq
        LSR \$1,Ry \\
1351 199 dgisselq
        BREV.C \$1,Rz \\
1352 21 dgisselq
        LSR \$1,Rx \\
1353
        OR Rz,Rx}
1354 199 dgisselq
        & Logical shift right with carry.  Unlike the shift left, this
1355
        approach doesn't extend well to numbers larger than two words. \\\hline
1356 36 dgisselq
\end{tabular}
1357
\caption{Derived Instructions, continued}\label{tbl:derived-2}
1358
\end{center}\end{table}
1359
\begin{table}\begin{center}
1360 199 dgisselq
\begin{tabular}{p{1.2in}p{1.5in}p{3.2in}}\\\hline
1361
{\tt NEG Rx} & \parbox[t]{1.5in}{\tt XOR \$-1,Rx \\ ADD \$1,Rx} & Negates Rx\\\hline
1362
{\tt NEG.C Rx} & \parbox[t]{1.5in}{\tt MOV.C \$-1+Rx,Rx\\XOR.C \$-1,Rx}
1363
        & Conditionally negates Rx\\\hline
1364
{\tt NOT Rx } & {\tt XOR \$-1,Rx } & One's complement\\\hline
1365
{\tt POP Rx }
1366
        & \parbox[t]{1.5in}{\tt LOD \$(SP),Rx \\ ADD \$1,SP}
1367
        & The compiler avoids the need for this instruction and the similar
1368
        {\tt PUSH} instruction when setting up the stack by coalescing all
1369
        the stack address modifications into a single instruction at the
1370
        beginning of any stack frame.\\\hline
1371 39 dgisselq
{\tt PUSH Rx}
1372 69 dgisselq
        & \parbox[t]{1.5in}{\hbox{\tt SUB \$1,SP}
1373
        \hbox{\tt STO Rx,\$(SP)}}
1374 39 dgisselq
        & Note that for pipelined operation, it helps to coalesce all the
1375
        {\tt SUB}'s into one command, and place the {\tt STO}'s right
1376 69 dgisselq
        after each other.  Further, to avoid a pipeline stall, the
1377 199 dgisselq
        immediate value for the first store must be zero.
1378 69 dgisselq
        \\\hline
1379 39 dgisselq
{\tt PUSH Rx-Ry}
1380 69 dgisselq
        & \parbox[t]{1.5in}{\tt SUB \$$n$,SP \\
1381
        STO Rx,\$(SP)
1382 36 dgisselq
        \ldots \\
1383 69 dgisselq
        STO Ry,\$$\left(n-1\right)$(SP)}
1384 36 dgisselq
        & Multiple pushes at once only need the single subtract from the
1385
        stack pointer.  This derived instruction is analogous to a similar one
1386 199 dgisselq
        on the Motorola 68k architecture, although the Zip Assembler
1387
        does not support the combined instruction.  This instruction
1388 39 dgisselq
        also supports pipelined memory access.\\\hline
1389
{\tt RESET}
1390 199 dgisselq
        & \parbox[t]{1in}{\tt STO \$1,\$watchdog(R12)\\BUSY}
1391
        & This depends upon the existence of a watchdog peripheral, and the
1392
        peripheral base address being preloaded into {\tt R12}.  The BUSY
1393
        instructions are required because the CPU will continue until the
1394
        {\tt STO} has completed.
1395 21 dgisselq
 
1396
        Another opportunity might be to jump to the reset address from within
1397 39 dgisselq
        supervisor mode.\\\hline
1398 69 dgisselq
{\tt RET} & {\tt MOV R0,PC}
1399
        & This depends upon the form of the {\tt JSR} given on the previous
1400
        page that stores the return address into R0.
1401 21 dgisselq
        \\\hline
1402 199 dgisselq
{\tt SEX.b Rx }
1403
        & \parbox[t]{1.5in}{\tt LSL 24,Rx \\ ASR 24,Rx}
1404
        & Signed extend an 8--bit value into a full word.\\\hline
1405
{\tt SEX.h Rx }
1406
        & \parbox[t]{1.5in}{\tt LSL 16,Rx \\ ASR 16,Rx}
1407
        & Sign extend a 16--bit value into a full word.\\\hline
1408 39 dgisselq
{\tt STEP Rr,Rt}
1409
        & \parbox[t]{1.5in}{\tt LSR \$1,Rr \\ XOR.C Rt,Rr}
1410 21 dgisselq
        & Step a Galois implementation of a Linear Feedback Shift Register, Rr,
1411
                using taps Rt \\\hline
1412 199 dgisselq
{\tt STEP}
1413
        & \parbox[t]{1.5in}{\tt OR \$Step|\$GIE,CC}
1414
        & Steps a user mode process by one instruction\\\hline
1415 139 dgisselq
%
1416
%
1417 199 dgisselq
\end{tabular}
1418
\caption{Derived Instructions, continued}\label{tbl:derived-3}
1419
\end{center}\end{table}
1420
\begin{table}\begin{center}
1421
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
1422 39 dgisselq
{\tt STO.b Rx,\$addr}
1423
        & \parbox[t]{1.5in}{\tt %
1424 21 dgisselq
        LDI \$addr,Ra \\
1425
        LDI \$addr,Rb \\
1426
        LSR \$2,Ra \\
1427
        AND \$3,Rb \\
1428
        SUB \$32,Rb \\
1429
        LOD (Ra),Ry \\
1430
        AND \$0ffh,Rx \\
1431 39 dgisselq
        AND \~\$0ffh,Ry \\
1432 21 dgisselq
        ROL Rb,Rx \\
1433
        OR Rx,Ry \\
1434
        STO Ry,(Ra) }
1435 199 dgisselq
        & \parbox[t]{3in}{This CPU and its bus are {\em not} optimized
1436 21 dgisselq
        for byte-wise operations.
1437
 
1438
        Note that in this example, \$addr is a
1439
        byte-wise address, whereas in all of our other examples it is a
1440
        32-bit word address. This also limits the address space
1441 199 dgisselq
        of character accesses from 16 MB down to 4MB.
1442 21 dgisselq
        Further, this instruction implies a byte ordering,
1443
        such as big or little endian.} \\\hline
1444 199 dgisselq
{\tt SUBR Rx,Ry }
1445
        & \parbox[t]{1.5in}{\tt SUB 1+Rx,Ry\\ XOR -1,Ry}
1446
        & Ry is set to Rx-Ry, rather than the normal subtract which
1447
        sets Ry to Ry-Rx. \\\hline
1448
\parbox[t]{1.4in}{\tt SUB Ra,Rx\\SUBC Rb,Ry}
1449
        & \parbox[t]{1.5in}{\tt SUB Ra,Rx\\SUB.C \$1,Ry\\SUB Rb,Ry}
1450
        & Subtract with carry.  Note that the overflow flag may not be
1451
        set correctly after this operation.\\\hline
1452 39 dgisselq
{\tt SWAP Rx,Ry }
1453 69 dgisselq
        & \parbox[t]{1.5in}{\tt XOR Ry,Rx \\ XOR Rx,Ry \\ XOR Ry,Rx}
1454 21 dgisselq
        & While no extra registers are needed, this example
1455
        does take 3-clocks. \\\hline
1456 39 dgisselq
{\tt TRAP \#X}
1457 199 dgisselq
        & \parbox[t]{1.5in}{\tt LDI \$x,R1 \\ AND \textasciitilde\$GIE,CC }
1458 36 dgisselq
        & This works because whenever a user lowers the \$GIE flag, it sets
1459 199 dgisselq
        a TRAP bit within the uCC register.  Therefore, upon entering the
1460 36 dgisselq
        supervisor state, the CPU only need check this bit to know that it
1461
        got there via a TRAP.  The trap could be made conditional by making
1462
        the LDI and the AND conditional.  In that case, the assembler would
1463 199 dgisselq
        quietly turn the LDI instruction into a {\tt BREV}/{\tt LDILO} pair,
1464 37 dgisselq
        but the effect would be the same. \\\hline
1465 69 dgisselq
{\tt TS Rx,Ry,(Rz)}
1466
        & \hbox{\tt LDI 1,Rx}
1467
                \hbox{\tt LOCK}
1468
                \hbox{\tt LOD (Rz),Ry}
1469
                \hbox{\tt STO Rx,(Rz)}
1470
        & A test and set instruction.  The {\tt LOCK} instruction insures
1471
        that the next two instructions lock the bus between the instructions,
1472
        so no one else can use it.  Thus guarantees that the operation is
1473
        atomic.
1474
        \\\hline
1475 39 dgisselq
{\tt TST Rx}
1476
        & {\tt TST \$-1,Rx}
1477 199 dgisselq
        & Set the condition codes based upon Rx without changing Rx.
1478
        Equivalent to a CMP \$0,Rx.\\\hline
1479 39 dgisselq
{\tt WAIT}
1480
        & {\tt Or \$GIE | \$SLEEP,CC}
1481
        & Wait until the next interrupt, then jump to supervisor/interrupt
1482
        mode.
1483 21 dgisselq
\end{tabular}
1484 36 dgisselq
\caption{Derived Instructions, continued}\label{tbl:derived-4}
1485 21 dgisselq
\end{center}\end{table}
1486 69 dgisselq
 
1487 199 dgisselq
\subsection{Interrupt Handling}
1488
The ZipCPU does not maintain any interrupt vector tables.  If an interrupt
1489
takes place, the CPU simply switches to from user to supervisor (interrupt)
1490
mode.  The supervisor code then continues from where it left off after
1491 69 dgisselq
executing a return to userspace {\tt RTU} instruction.
1492
 
1493 199 dgisselq
Since the CPU may return from userspace after either an interrupt, a
1494
trap, or an exception, it is up to the supervisor code that handles the
1495
transition to determine which of the three has taken place.
1496 69 dgisselq
 
1497 199 dgisselq
\subsection{Pipeline Stages}
1498 32 dgisselq
As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},
1499 199 dgisselq
the ZipCPU supports a five stage pipeline.
1500 21 dgisselq
\begin{enumerate}
1501 199 dgisselq
\item {\bf Prefetch}: Reads instructions from memory.  If the CPU has been
1502
        configured with a cache, the cache has been integrated into the
1503
        prefetch.  Stalls are also created here if the instruction isn't
1504 21 dgisselq
        in the prefetch cache.
1505 36 dgisselq
 
1506 199 dgisselq
        The ZipCPU supports one of three prefetch methods, depending upon the
1507
        flags set at build time within the {\tt cpudefs.v} file.
1508
 
1509
        The simplest
1510 69 dgisselq
        is a non--cached implementation of a prefetch.  This implementation is
1511 199 dgisselq
        fairly small, and ideal for users of the ZipCPU who need the extra
1512 69 dgisselq
        space on the FPGA fabric.  However, because this non--cached version
1513
        has no cache, the maximum number of instructions per clock is limited
1514 199 dgisselq
        to about one per eight--depending upon the bus/memory delay.
1515
        This prefetch option is set by leaving the {\tt OPT\_SINGLE\_FETCH}
1516
        line uncommented within the {\tt cpudefs.v} file.  Using this option
1517
        will also turn off the ZipCPU pipeline.
1518 36 dgisselq
 
1519 199 dgisselq
        The second prefetch module is a non--traditional pipelined prefetch
1520
        with a cache.  This module tries to keep the instruction address
1521
        within a window of valid instruction addresses.  While effective, it
1522
        is not a traditional cache implementation.  A disappointing feature of
1523
        this implementation is that it needs an extra internal pipeline stage
1524 36 dgisselq
        to be implemented.
1525
 
1526 199 dgisselq
        The third prefetch and cache module implements a more traditional
1527
        cache.  This cache provides for the fastest CPU speed.  The only
1528
        drawback is that, when a cache line is loading, the CPU will be stalled
1529
        until the cache is completely loaded.
1530 69 dgisselq
 
1531 199 dgisselq
\item {\bf Decode}: Decodes an instruction into it's OpCode, register(s) to
1532
        read, condition code, and immediate offset.  This stage also
1533
        determines whether the flags will be read or set, whether registers
1534
        will be read (and hence the pipeline may need to stall), or whether the
1535
        result will be written back.  In many ways, simplifying the CPU also
1536
        meant simplifying this pipeline stage and hence the instruction set
1537
        architecture.
1538 69 dgisselq
 
1539 199 dgisselq
\item {\bf Read Operands}: Read from the register file and applies any
1540
        immediate values to the result.  There is no means of detecting or
1541
        flagging arithmetic overflow or carry when adding the immediate to the
1542
        operand.  This stage will stall if any source operand is pending
1543
        and the immediate value is non--zero.
1544 69 dgisselq
 
1545 199 dgisselq
\item At this point, the processing flow splits into one of four tracks: An
1546
        {\bf ALU} track which will accomplish a simple instruction, the
1547
        {\bf MemOps} stage which handles {\tt LOD} (load) and {\tt STO}
1548
        (store) instructions, the {\bf divide} unit, and the
1549
        {\bf floating point} unit.
1550 21 dgisselq
        \begin{itemize}
1551 199 dgisselq
        \item Loads will stall instructions in the read operands stage until the
1552
                entire memory is complete, lest a register be read only to be
1553
                updated unseen by the Load.
1554
        \item Condition codes are set upon completion of the ALU, divide,
1555
                or FPU stage.  (Memory operations do not set conditions.)
1556 69 dgisselq
        \item Issuing a non--pipelined memory instruction to the memory unit
1557 199 dgisselq
                while the memory unit is busy will stall the entire pipeline
1558
                until the memory unit is idle and ready to accept another
1559
                instruction.
1560 21 dgisselq
        \end{itemize}
1561 32 dgisselq
\item {\bf Write-Back}: Conditionally write back the result to the register
1562 199 dgisselq
        set, applying the condition and any special CC logic.  This routine is
1563
        quad-entrant: either the ALU, the memory, the divide, or the FPU may
1564
        commit a result.  The only design rule is that no more than a single
1565
        register may be written in any given clock cycle.
1566
 
1567
        This is also the stage where any special condition code logic takes
1568
        place.
1569 21 dgisselq
\end{enumerate}
1570
 
1571 199 dgisselq
The ZipCPU does not support out of order execution.  Therefore, if the memory
1572 69 dgisselq
unit stalls, every other instruction stalls.  The same is true for divide or
1573
floating point instructions--all other instructions will stall while waiting
1574
for these to complete.  Memory stores, however, can take place concurrently
1575 199 dgisselq
with non--memory operations, although memory reads (loads) cannot.  This is
1576
likely to change with the integration of an memory management unit (MMU), in which case a store
1577
instruction must stall the CPU until it is known whether or not the store
1578
address can be mapped by the MMU.
1579 24 dgisselq
 
1580 199 dgisselq
% \subsection{Instruction Cache}
1581
% \subsection{Data Cache}
1582
 
1583
\subsection{Pipeline Stalls}
1584 32 dgisselq
The processing pipeline can and will stall for a variety of reasons.  Some of
1585
these are obvious, some less so.  These reasons are listed below:
1586
\begin{itemize}
1587
\item When the prefetch cache is exhausted
1588 21 dgisselq
 
1589 36 dgisselq
This reason should be obvious.  If the prefetch cache doesn't have the
1590 69 dgisselq
instruction in memory, the entire pipeline must stall until an instruction
1591
can be made ready.  In the case of the {\tt pipefetch} windowed approach
1592
to the prefetch cache, this means the pipeline will stall until enough of the
1593
prefetch cache is loaded to support the next instruction.  In the case
1594
of the more traditional {\tt pfcache} approach, the entire cache line must
1595
fill before instruction execution can continue.
1596 21 dgisselq
 
1597 32 dgisselq
\item While waiting for the pipeline to load following any taken branch, jump,
1598 199 dgisselq
        return from interrupt or switch to interrupt context (4 stall cycles,
1599
        minimum)
1600 32 dgisselq
 
1601 68 dgisselq
Fig.~\ref{fig:bcstalls}
1602
\begin{figure}\begin{center}
1603
\includegraphics[width=3.5in]{../gfx/bc.eps}
1604 69 dgisselq
\caption{A conditional branch generates 4 stall cycles}\label{fig:bcstalls}
1605 68 dgisselq
\end{center}\end{figure}
1606
illustrates the situation for a conditional branch.  In this case, the branch
1607 69 dgisselq
instruction, {\tt BC}, is nominally followed by instructions {\tt I1} and so
1608 68 dgisselq
forth.  However, since the branch is taken, the next instruction must be
1609
{\tt IA}.  Therefore, the pipeline needs to be cleared and reloaded.
1610
Given that there are five stages to the pipeline, that accounts
1611 69 dgisselq
for the four stalls.  (Were the {\tt pipefetch} cache chosen, there would
1612
be another stall internal to the {\tt pipefetch} cache.)
1613 32 dgisselq
 
1614 199 dgisselq
The decode stage can handle the {\tt ADD \$X,PC}, {\tt LDI \$X,PC}, and
1615
{\tt LOD (PC),PC} instructions specially, however, when {\tt EARLY\_BRANCHING}
1616
is enabled.  These instructions, when
1617
not conditioned on the flags, can execute with only a single stall cycle (two
1618
for the {\tt LOD(PC),PC} instruction),
1619
such as is shown in Fig.~\ref{fig:branch}.
1620 68 dgisselq
\begin{figure}\begin{center}
1621 69 dgisselq
\includegraphics[width=4in]{../gfx/bra.eps} %0.4in per clock
1622
\caption{An expedited branch costs a single stall cycle}\label{fig:branch}
1623 68 dgisselq
\end{center}\end{figure}
1624
In this example, {\tt BR} is a branch always taken, {\tt I1} is the instruction
1625
following the branch in memory, while {\tt IA} is the first instruction at the
1626
branch address.  ({\tt CLR} denotes a clear--pipeline operation, and does
1627
not represent any instruction.)
1628 36 dgisselq
 
1629 32 dgisselq
\item When reading from a prior register while also adding an immediate offset
1630
\begin{enumerate}
1631
\item\ {\tt OPCODE ?,RA}
1632
\item\ {\em (stall)}
1633
\item\ {\tt OPCODE I+RA,RB}
1634
\end{enumerate}
1635
 
1636
Since the addition of the immediate register within OpB decoding gets applied
1637
during the read operand stage so that it can be nicely settled before the ALU,
1638
any instruction that will write back an operand must be separated from the
1639
opcode that will read and apply an immediate offset by one instruction.  The
1640
good news is that this stall can easily be mitigated by proper scheduling.
1641 36 dgisselq
That is, any instruction that does not add an immediate to {\tt RA} may be
1642
scheduled into the stall slot.
1643 32 dgisselq
 
1644 69 dgisselq
This is also the reason why, when setting up a stack frame, the top of the
1645 199 dgisselq
stack frame is used first: it eliminates this stall cycle.\footnote{This only
1646
applies if there is no local memory to allocate on the stack as well.}  Hence,
1647
to save registers at the top of a procedure, one would write:
1648 32 dgisselq
\begin{enumerate}
1649 69 dgisselq
\item\ {\tt SUB 2,SP}
1650
\item\ {\tt STO R1,(SP)}
1651
\item\ {\tt STO R2,1(SP)}
1652 32 dgisselq
\end{enumerate}
1653 69 dgisselq
Had {\tt R1} instead been stored at {\tt 1(SP)} as the top of the stack,
1654
there would've been an extra stall in setting up the stack frame.
1655 32 dgisselq
 
1656
\item When reading from the CC register after setting the flags
1657
\begin{enumerate}
1658 69 dgisselq
\item\ {\tt ALUOP RA,RB} {\em ; Ex: a compare opcode}
1659 36 dgisselq
\item\ {\em (stall)}
1660 32 dgisselq
\item\ {\tt TST sys.ccv,CC}
1661
\item\ {\tt BZ somewhere}
1662
\end{enumerate}
1663
 
1664 68 dgisselq
The reason for this stall is simply performance: many of the flags are
1665
determined via combinatorial logic {\em during} the writeback cycle.
1666
Trying to then place these into the input for one of the operands for an
1667
ALU instruction during the same cycle
1668 32 dgisselq
created a time delay loop that would no longer execute in a single 100~MHz
1669
clock cycle.  (The time delay of the multiply within the ALU wasn't helping
1670
either \ldots).
1671
 
1672 33 dgisselq
This stall may be eliminated via proper scheduling, by placing an instruction
1673
that does not set flags in between the ALU operation and the instruction
1674
that references the CC register.  For example, {\tt MOV \$addr+PC,uPC}
1675
followed by an {\tt RTU} ({\tt OR \$GIE,CC}) instruction will not incur
1676
this stall, whereas an {\tt OR \$BREAKEN,CC} followed by an {\tt OR \$STEP,CC}
1677 68 dgisselq
will incur the stall, while a {\tt LDI \$BREAKEN|\$STEP,CC} will not since
1678 69 dgisselq
it doesn't read the condition codes before executing.
1679 33 dgisselq
 
1680 32 dgisselq
\item When waiting for a memory read operation to complete
1681
\begin{enumerate}
1682
\item\ {\tt LOD address,RA}
1683 36 dgisselq
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
1684 32 dgisselq
\item\ {\tt OPCODE I+RA,RB}
1685
\end{enumerate}
1686
 
1687 199 dgisselq
Remember, the ZipCPU does not support out of order execution.  Therefore,
1688 32 dgisselq
anytime the memory unit becomes busy both the memory unit and the ALU must
1689 68 dgisselq
stall until the memory unit is cleared.  This is illustrated in
1690
Fig.~\ref{fig:memrd},
1691
\begin{figure}\begin{center}
1692 69 dgisselq
\includegraphics[width=5.6in]{../gfx/memrd.eps}
1693 68 dgisselq
\caption{Pipeline handling of a load instruction}\label{fig:memrd}
1694
\end{center}\end{figure}
1695
since it is especially true of a load
1696 69 dgisselq
instruction, which must still write its operand back to the register file.
1697
Further, note that on a pipelined memory operation, the instruction must
1698
stall in the decode operand stage, lest it try to read a result from the
1699
register file before the load result has been written to it.  Finally, note
1700
that there is an extra stall at the end of the memory cycle, so that
1701
the memory unit will be idle for two clocks before an instruction will be
1702
accepted into the ALU.  Store instructions are different, as shown in
1703
Fig.~\ref{fig:memwr},
1704 68 dgisselq
\begin{figure}\begin{center}
1705 69 dgisselq
\includegraphics[width=4in]{../gfx/memwr.eps}
1706 68 dgisselq
\caption{Pipeline handling of a store instruction}\label{fig:memwr}
1707
\end{center}\end{figure}
1708
since they can be busy with the bus without impacting later write back
1709
pipeline stages.  Hence, only loads stall the pipeline.
1710 32 dgisselq
 
1711 68 dgisselq
This, of course, also assumes that the memory being accessed is a single cycle
1712
memory and that there are no stalls to get to the memory.
1713 32 dgisselq
Slower memories, such as the Quad SPI flash, will take longer--perhaps even
1714 33 dgisselq
as long as forty clocks.   During this time the CPU and the external bus
1715 68 dgisselq
will be busy, and unable to do anything else.  Likewise, if it takes a couple
1716
of clock cycles for the bus to be free, as shown in both Figs.~\ref{fig:memrd}
1717
and~\ref{fig:memwr}, there will be stalls.
1718 32 dgisselq
 
1719
\item Memory operation followed by a memory operation
1720
\begin{enumerate}
1721
\item\ {\tt STO address,RA}
1722 36 dgisselq
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
1723 32 dgisselq
\item\ {\tt LOD address,RB}
1724 36 dgisselq
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
1725 32 dgisselq
\end{enumerate}
1726
 
1727 68 dgisselq
In this case, the LOD instruction cannot start until the STO is finished,
1728
as illustrated by Fig.~\ref{fig:mstld}.
1729
\begin{figure}\begin{center}
1730
\includegraphics[width=5.5in]{../gfx/mstld.eps}
1731
\caption{Pipeline handling of a store followed by a load instruction}\label{fig:mstld}
1732
\end{center}\end{figure}
1733 32 dgisselq
With proper scheduling, it is possible to do something in the ALU while the
1734 36 dgisselq
memory unit is busy with the STO instruction, but otherwise this pipeline will
1735 68 dgisselq
stall while waiting for it to complete before the load instruction can
1736
start.
1737 32 dgisselq
 
1738 199 dgisselq
The ZipCPU has the capability of supporting a form of burst memory access,
1739
often called pipelined memory access within this document due to its use of
1740
the Wishbone B4 pipelined access mode.
1741
When using this mode, the CPU may issue multiple loads or stores at a time,
1742
to the extent that all but the first take only a single clock.  Doing this
1743
requires several conditions to be true:
1744
\begin{enumerate}
1745
\item Aall accesses within the burst must all be reads or all be writes,
1746
\item All must use the same base register for their address, and
1747
\item There can be no stalls or other instructions between memory access instructions within the burst.
1748
\item Further, the immediate offset to memory must be either indentical or
1749
        increasing by one address each instruction.
1750
\end{enumerate}
1751
These conditions work well for saving or storing registers to the stack in a
1752
burst operation.  Indeed, if you noticed, both Fig.~\ref{fig:memrd} and
1753
Fig.~\ref{fig:memwr} illustrated pipelined memory accesses.  Beyond saving and
1754
restoring registers to the stack, the compiler does not optimize well (yet)
1755
for using this burst mode.
1756 36 dgisselq
 
1757 32 dgisselq
\end{itemize}
1758
 
1759 199 dgisselq
% \subsection{Debug}
1760 32 dgisselq
 
1761 199 dgisselq
\section{External Architecture}
1762 24 dgisselq
 
1763 199 dgisselq
Having now described the CPU registers, instructions, and instruction formats,
1764
we now turn our attention to how the CPU interacts with the rest of the world.
1765
Specifically, we shall discuss how the bus is implemented, and the memory
1766
model assumed by the CPU.
1767
 
1768
\subsection{Simplified Wishbone Bus}\label{ssec:bus}
1769
The bus architecture of the ZipCPU is that of a simplified, pipelined, WISHBONE
1770
bus built according to the B4 specification.  Several changes have been made to
1771
simplify this bus.  First, all unnecessary ancillary information has been
1772
removed.  This includes the retry, tag, lock, cycle type indicator, and burst
1773
indicator signals.  It also includes the select lines which would enable the
1774
CPU to act on less than 32--bit words.  As a result all operations on the bus
1775
are 32--bit operations.  The bus is neither little endian nor big endian.  For
1776
this reason, all words are 32--bits.  All instructions are also 32--bits wide.
1777
Everything has been built around the 32--bit word.  Even the byte size (the
1778
size of the minimum addressable unit) is 32--bits.  Second, we insist that all
1779
accesses be pipelined, and simplify that further by insisting that pipelined
1780
accesses not cross peripherals---although we leave it to the user to keep that
1781
from happening in practice.  Finally, we insist that the wishbone strobe line
1782
be zero any time the cycle line is inactive.  This makes decoding simpler
1783
in slave logic: a transaction is initiated whenever the strobe line is high
1784
and the stall line is low.  For those peripherals that do not generate stalls,
1785
only the strobe line needs to be tested for access.  The transaction completes
1786
whenever either the ACK or the ERR lines go high.
1787
 
1788
\subsection{Memory Model}\label{ssec:memory}
1789
The memory model of the ZipCPU is that of a uniform 32--bit address space.
1790
The CPU knows nothing about which addresses reference on--chip or off-chip
1791
memory, or even which reference peripherals.  Indeed, there is no indication
1792
within the CPU if a particular piece of memory can be cached or not, save that
1793
the CPU assumes any and all instruction words can be cached.
1794
 
1795
The one exception to this rule revolves around addresses beginning with
1796
{\tt 2'b11} in their high order word.  These addresses are used to access a
1797
variety of optional peripherals that will be discussed more in
1798
Sec.~\ref{sec:zipsys}, but that are only present within the {\tt ZipSystem}.
1799
When used with the bare {\tt ZipBones}, these addresses will cause a bus error.
1800
 
1801
The prefetch cache currently has no means of detecting an instruction that
1802
was changed, save by clearing the instruction cache.  This may be necessary
1803
when loading programs into previously used memory, or when creating
1804
self--modifying code.
1805
 
1806
Should the memory management unit (MMU) be integrated into the ZipCPU, the MMU
1807
will be able to be configured to instruct the ZipCPU as to which addresses may
1808
be cached and which not.
1809
 
1810
This topic is discussed further in the linker section, Sec.~\ref{sec:ld-mem}
1811
of the ABI chapter, Chap.~\ref{chap:abi}.
1812
 
1813
% \subsection{Measured Performance}\label{sec:perf}
1814
 
1815
\subsection{ZipSystem}\label{sec:zipsys}
1816
 
1817
While the previous chapter describes a CPU in isolation, the ZipSystem
1818
includes a small minimum set of peripherals that can be tightly integrated into
1819
the CPU.  These peripherals are shown in Fig.~\ref{fig:zipsystem}
1820 24 dgisselq
\begin{figure}\begin{center}
1821
\includegraphics[width=3.5in]{../gfx/system.eps}
1822 199 dgisselq
\caption{ZipSystem Peripherals}\label{fig:zipsystem}
1823 24 dgisselq
\end{center}\end{figure}
1824
and described here.  They are designed to make
1825 199 dgisselq
the ZipCPU more useful in an Embedded Operating System environment.
1826 24 dgisselq
 
1827 199 dgisselq
\subsubsection{Interrupt Controller}\label{sec:pic}
1828 24 dgisselq
 
1829 199 dgisselq
Perhaps the most important peripheral within the ZipSystem is the interrupt
1830
controller.  While the ZipCPU itself can only handle one interrupt, and has
1831 24 dgisselq
only the one interrupt state: disabled or enabled, the interrupt controller
1832
can make things more interesting.
1833
 
1834 199 dgisselq
The ZipSystem interrupt controller module supports up to 15 interrupts, all
1835
controlled from one register.  Further, it has been designed so that individual
1836
interrupts can be enabled or disabled individually without having any knowledge
1837
of the rest of the controller setting.  To enable an interrupt, write to the
1838
register with the high order global enable bit set and the respective interrupt
1839
enable bit set.  No other bits will be affected.  To disable an interrupt,
1840
write to the register with the high order global enable bit cleared and the
1841
respective interrupt enable bit set.  To clear an interrupt, write a `1' to
1842
that interrupt's status pin.  A zero written to the register has the sole
1843
effect of disabling the master interrupt enable bit.
1844 24 dgisselq
 
1845
As an example, suppose you wished to enable interrupt \#4.  You would then
1846
write to the register a {\tt 0x80100010} to enable interrupt \#4 and to clear
1847
any past active state.  When you later wish to disable this interrupt, you would
1848 199 dgisselq
write a {\tt 0x00100010} to the register.  This both disables the
1849 24 dgisselq
interrupt and clears the active indicator.  This also has the side effect of
1850
disabling all interrupts, so a second write of {\tt 0x80000000} may be necessary
1851
to re-enable any other interrupts.
1852
 
1853 199 dgisselq
The ZipSystem hosts two interrupt controllers: a primary and a secondary.  The
1854
primary interrupt controller is the one that interrupts the CPU.  It has
1855
six local interrupt lines, the rest coming from external interrupt sources.
1856
One of those interrupt lines to the primary controller comes from the secondary
1857
interrupt controller.  This controller maintains an interrupt state for the
1858
process accounting counters, and any other external interrupts that didn't fit
1859
into the primary interrupt controller.
1860 24 dgisselq
 
1861 199 dgisselq
As a word of caution, because the interrupt controller is an external
1862
peripheral, and because memory writes take place concurrently with any following
1863
instructions, any attempt to clear interrupts on one instruction followed by
1864
an immediate Return to Userspace ({\tt RTU}) instruction, may not have the
1865
effect of having interrupts cleared before the {\tt RTU} instruction executes.
1866 21 dgisselq
 
1867 199 dgisselq
\subsubsection{Counter}
1868
 
1869 21 dgisselq
The Zip Counter is a very simple counter: it just counts.  It cannot be
1870
halted.  When it rolls over, it issues an interrupt.  Writing a value to the
1871
counter just sets the current value, and it starts counting again from that
1872
value.
1873
 
1874 199 dgisselq
Eight counters are implemented in the ZipSystem for process accounting if
1875
the {\tt INCLUDE\_ACCOUNTING\_COUNTERS} define is set within {\tt cpudefs.v}.
1876
Four of those measure the performance of the system as a whole, four are
1877
used for measuring user CPU usage.
1878 21 dgisselq
This may change in the future, as nothing as yet uses these counters.
1879
 
1880 199 dgisselq
\subsubsection{Timer}
1881 21 dgisselq
 
1882 199 dgisselq
The Zip Timer is also very simple: it is a 31--bit counter that simply counts
1883
down to zero.  When it transitions from a one to a zero it creates an interrupt.
1884 21 dgisselq
 
1885
Writing any non-zero value to the timer starts the timer.  If the high order
1886
bit is set when writing to the timer, the timer becomes an interval timer and
1887
reloads its last start time on any interrupt.  Hence, to mark seconds, one
1888 199 dgisselq
might set the 31--bits of the timer to the number of clocks per second and the
1889
top bit to one.  Ever after, the timer will interrupt the CPU once per
1890
second--until a non--interrupt interval is set in the timer.  This reload
1891
capability also limits the maximum timer value to $2^{31}-1$, rather than
1892
$2^{32}-1$.
1893 21 dgisselq
 
1894 199 dgisselq
\subsubsection{Watchdog Timer}
1895 21 dgisselq
 
1896 199 dgisselq
The watchdog timer has only two differences from the of the other timers.
1897
The first difference is that it is a one--shot timer.  The second difference,
1898
though, is critical: the interrupt line from the watchdog timer is tied to the
1899
reset line of the CPU.  Hence writing a `1' to the watchdog timer will always
1900
reset the CPU.  To stop the Watchdog timer, write a `0' to it.  To start it,
1901 21 dgisselq
write any other number to it---as with the other timers.
1902
 
1903
 
1904 199 dgisselq
\subsubsection{Bus Watchdog}
1905
There is an additional watchdog timer on the Wishbone bus of the ZipSystem.
1906
This timer,
1907 68 dgisselq
however, is hardware configured and not software configured.  The timer is
1908
reset at the beginning of any bus transaction, and only counts clocks during
1909
such bus transactions.  If the bus transaction takes longer than the number
1910
of counts the timer allots, it will raise a bus error flag to terminate the
1911
transaction.  This is useful in the case of any peripherals that are
1912
misbehaving.  If the bus watchdog terminates a bus transaction, the CPU may
1913
then read from its port to find out which memory location created the problem.
1914
 
1915
Aside from its unusual configuration, the bus watchdog is just another
1916 69 dgisselq
implementation of the fundamental timer described above--stripped down
1917
for simplicity.
1918 68 dgisselq
 
1919 199 dgisselq
\subsubsection{Jiffies}
1920 21 dgisselq
 
1921
This peripheral is motivated by the Linux use of `jiffies' whereby a process
1922
can request to be put to sleep until a certain number of `jiffies' have
1923
elapsed.  Using this interface, the CPU can read the number of `jiffies'
1924
from the peripheral (it only has the one location in address space), add the
1925 69 dgisselq
sleep length to it, and write the result back to the peripheral.  The
1926
{\tt zipjiffies}
1927 21 dgisselq
peripheral will record the value written to it only if it is nearer the current
1928
counter value than the last current waiting interrupt time.  If no other
1929
interrupts are waiting, and this time is in the future, it will be enabled.
1930
(There is currently no way to disable a jiffie interrupt once set, other
1931 24 dgisselq
than to disable the interrupt line in the interrupt controller.)  The processor
1932 21 dgisselq
may then place this sleep request into a list among other sleep requests.
1933
Once the timer expires, it would write the next Jiffy request to the peripheral
1934
and wake up the process whose timer had expired.
1935
 
1936
Indeed, the Jiffies register is nothing more than a glorified counter with
1937 199 dgisselq
an interrupt.  Unlike the other counters, the internal Jiffies counter can only
1938
be read, never set.
1939 21 dgisselq
Writes to the jiffies register create an interrupt time.  When the Jiffies
1940
register later equals the value written to it, an interrupt will be asserted
1941
and the register then continues counting as though no interrupt had taken
1942
place.
1943
 
1944 199 dgisselq
Finally, if the new value written to the Jiffies register is within the past
1945
$2^{31-1}$ clock ticks, the Jiffies register will immediately cause an interrupt
1946
and otherwise ignore the new request.
1947
 
1948 21 dgisselq
The purpose of this register is to support alarm times within a CPU.  To
1949
set an alarm for a particular process $N$ clocks in advance, read the current
1950 199 dgisselq
Jiffies value, add $N$, and write it back to the Jiffies register.  The
1951 21 dgisselq
O/S must also keep track of values written to the Jiffies register.  Thus,
1952 32 dgisselq
when an `alarm' trips, it should be removed from the list of alarms, the list
1953 69 dgisselq
should be resorted, and the next alarm in terms of Jiffies should be written
1954
to the register--possibly for a second time.
1955 21 dgisselq
 
1956 199 dgisselq
\subsubsection{Direct Memory Access Controller}
1957 24 dgisselq
 
1958 36 dgisselq
The Direct Memory Access (DMA) controller can be used to either move memory
1959
from one location to another, to read from a peripheral into memory, or to
1960
write from a peripheral into memory all without CPU intervention.  Further,
1961
since the DMA controller can issue (and does issue) pipeline wishbone accesses,
1962
any DMA memory move will by nature be faster than a corresponding program
1963
accomplishing the same move.  To put this to numbers, it may take a program
1964 199 dgisselq
running on the CPU 18~clocks per word transferred, whereas this DMA controller
1965
can move one word in eight clocks--provided it has bus
1966
access\footnote{The pipeline cost of the DMA controller, including setup cost,
1967
is a minimum of $14+2N$ clocks.} (The CPU gets priority over the bus, but once
1968
bus access is granted to the DMA peripheral, it will not be revoked mid--read
1969
or mid--write.)
1970 24 dgisselq
 
1971 36 dgisselq
When copying memory from one location to another, the DMA controller will
1972
copy in units of a given transfer length--up to 1024 words at a time.  It will
1973
read that transfer length into its internal buffer, and then write to the
1974 69 dgisselq
destination address from that buffer.
1975 24 dgisselq
 
1976 36 dgisselq
When coupled with a peripheral, the DMA controller can be configured to start
1977 199 dgisselq
a memory copy when any interrupt line goes high.  Further, the controller can
1978 69 dgisselq
be configured to issue reads from (or to) the same address instead of
1979
incrementing the address at each clock.  The DMA completes once the total
1980
number of items specified (not the transfer length) have been transferred.
1981 36 dgisselq
 
1982
In each case, once the transfer is complete and the DMA unit returns to
1983
idle, the DMA will issue an interrupt.
1984
 
1985 199 dgisselq
% \subsubsection{Memory Management Unit}
1986 36 dgisselq
 
1987 199 dgisselq
\section{Debug Interface}\label{sec:debug}
1988 21 dgisselq
 
1989 199 dgisselq
The ZipCPU supports an external debug port.  Access to the port is the
1990
same as accessing a two register peripheral on a wishbone bus, so the basic
1991
interface is fairly simple.  Using this interface, it is possible to both
1992
control the CPU, as well as read register values and current status from the
1993
CPU.
1994
 
1995
While a more detailed discussion will be reserved for Sec.~\ref{sec:reg-debug},
1996
here we'll just discuss how it is put together.  The debug interface allows
1997
a controller access to the CPU reset line, and a halt line.  By raising the
1998
reset line, the CPU will be caused to clear it's cache, to clear any internal
1999
exception or error conditions, and then to start execution at the
2000
{\tt RESET\_ADDRESS}--just like a normal reboot.  In a similar fashion, the
2001
debug interface allows you to control the {\tt cpu\_halt} line into the
2002
CPU.  Holding this line high will hold the CPU in an externally halted state.
2003
Toggling the line low for one clock allows one to step the CPU by one
2004
instruction.  Lowering the line causes the CPU to go.  A final control wire,
2005
controlled by the debug interface, will force the CPU to clear its cache.
2006
All of these control wires are set or cleared from the debug control register.
2007
 
2008
The two debug command registers also make it possible to read and write
2009
all 32 registers within the CPU.  In this fashion, a debugger can halt the
2010
CPU, investigate its state, and even modify registers so as to have the
2011
CPU restart from a different state.
2012
 
2013
Finally, without halting the CPU, the debug controller can read from any
2014
single register, and it can see if the CPU is still actively running, whether
2015
it is in user or supervisor modes, and whether or not it is sleeping.  This
2016
alone is useful for detecting deadlocks or other difficult problems.
2017
 
2018
\chapter{Application Binary Interface}\label{chap:abi}
2019
 
2020
This chapter discusses not the CPU itself, but rather how the GCC and binutils
2021
toolchains have been configured to support the ZipCPU.
2022
 
2023
% ELF Format
2024
% Stack:
2025
%       R13 is the stack register.
2026
%       The stack grows downward.
2027
%       Memory at the current stack pointer is allocated.
2028
%       Hence, a PUSH is : SUB 1,SP; STO Rx,(SP)
2029
% Heap:
2030
%       In general, not yet implemented.
2031
%       A less than adequate Heap has been implemented as a pointer, from which
2032
%       malloc requests simply decrement it.  Free's are NOOPs, leaving
2033
%       allocated memory allocated forever.
2034
 
2035
\section{Executable File Format}\label{sec:abi-elf}
2036
ZipCPU executable files are stored in the Executable and Linkable Format
2037
(ELF), prior to being placed in flash, or whatever memory they will be
2038
executed from.  All addresses within this format are ZipCPU addresses,
2039
referencing 32--bit quantities, whereas all offsets internal to the ELF file
2040
represent 8--bit quantities.  Thus, when running the {\tt zip-objdump} utility
2041
on a ZipCPU ELF file, the addresses are properly set.
2042
 
2043
The ZipCPU does not (yet) have a dynamic linker/loader.  All linking is
2044
currently static, and done prior to run time.
2045
 
2046
\section{Stack}\label{sec:abi-stack}
2047
Although nothing in the hardware requires this, the compiler back end
2048
implementation uses {\tt R13} (also known as the {\tt SP} register) as a stack
2049
register, and grows the stack from
2050
high addresses to lower addresses.  That means that the stack will usually
2051
start out set to a very large value, such as one past the last RAM address,
2052
and it will grow to lower and lower values--hopefully never mixing with the
2053
heap.  Memory at the current stack position is assumed to be allocated.
2054
 
2055
When creating a stack frame for a function, the compiler will subtract
2056
the size of the stack frame from the stack register.  It will then store
2057
any registers used by the function, from {\tt R5} to {\tt R12} (including
2058
the link register {\tt R0}) onto offsets given by the stack pointer plus a
2059
constant.  If a frame pointer is used, the compiler uses {\tt R12} (or {\tt FP})
2060
for this purpose.  The frame pointer is set by moving the stack pointer
2061
plus an offset into {\tt FP}.  This {\tt MOV} instruction effectively limits
2062
the size of any individual stack frame to $2^{12}-1$ words.
2063
 
2064
Once a subroutine is complete, the frame is unwound.  If the frame pointer,
2065
{\tt FP} was used, then {\tt FP} is copied directly to the stack pointer,
2066
{\tt SP}.  Registers are restored, starting with {\tt R0} all the way to
2067
{\tt R12} ({\tt FP}).  This also restores, and obliterates, the subroutine
2068
frame pointer.  Once complete, a value is added to the stack pointer to return
2069
it to its original value, and a jump is made to the value located within
2070
{\tt R0}.
2071
 
2072
\section{Relocations}\label{sec:abi-reloc}
2073
 
2074
The ZipCPU binutils back end supports two several relocations, although the
2075
two most common are the 32--bit relocations for register load and long jump.
2076
 
2077
The first of these is for loading an arbitrary 32--bit value into a register.
2078
Such instructions are broken into a pair of {\tt BREV} and {\tt LDILO}
2079
instructions, and once the value of the parameter is known their immediates
2080
are filled in.
2081
 
2082
The second type of 32--bit relocation is for jumps to arbitrary addresses.
2083
These jumps are supported by the \hbox{\tt LOD (PC),PC} instruction, followed
2084
by the 32--bit address to be filled in later by the linker.  If the jump is
2085
conditional, then a conditional \hbox{\tt LOD.$x$ 1(PC),PC} instruction is
2086
used, followed by a {\tt BRA 1(PC),PC} and then the 32--bit relocation value.
2087
 
2088
If the branch distance is known and within reach, branches will be implemented
2089
with {\tt ADD \#,PC} instructions, possibly conditional, as necessary.
2090
 
2091
While other relocations are supported, they tend not to be used nearly as much
2092
as these two.
2093
 
2094
\section{Call format}\label{sec:abi-jsr}
2095
 
2096
One feature of the ZipCPU is that it has no JSR instruction.  Jumps to
2097
subroutine's therefore take three assembly instructions:
2098
The first is a {\tt MOV .Lcall\#\#(PC),R0}, which places the return address
2099
into R0.  {\tt .Lcall\#\#} in this case is a label, where \#\# is a unique
2100
number filled in by the compiler.  This instruction is followed by a
2101
{\tt BRA subroutine} instruction.  Finally, the third assembly ``instruction''
2102
of any call sequence is the label {\tt .Lcall\#\#}.
2103
 
2104
While this works well in practice, GCC's implementation prevents such things
2105
as {\tt JSR}'s followed by {\tt BRA}'s from being combined together.
2106
 
2107
Finally, the first five operands passed to the subroutine will be placed into
2108
registers R1--R5.  Any additional operands are placed upon the stack.
2109
 
2110
\section{Built-ins}\label{sec:abi-builtin}
2111
The ZipCPU ABI supports the a number of built in functions.  The compiler
2112
maps these functions directly to assembly language equivalents, essentially
2113
providing the C~programmer with access to several assembly language
2114
instructions.  These are:
2115 33 dgisselq
\begin{enumerate}
2116 199 dgisselq
\item {\tt zip\_bitrev(int)} reverses the bits in the given integer, returning
2117
        the result.  This utilizes the internal {\tt BREV} instruction, and is
2118
        designed to be used with FFT's as necessary.
2119
\item {\tt zip\_busy()} executes an {\tt ADD -1,PC} function, essentially
2120
        forcing the CPU into a very tight infinite loop.
2121
\item {\tt zip\_cc()} returns the value of the current CC register.  This may
2122
        be used within both user and supervisor code to determine in which
2123
        mode the CPU is within.
2124
\item {\tt zip\_halt()} executes an \hbox{\tt OR \$SLEEP,CC} instruction to
2125
        place the processor to sleep.  If the processor is in supervisor mode,
2126
        this halt's the processor.
2127
\item {\tt zip\_rtu()} executes an \hbox{\tt OR \$GIE,CC} instruction.  This
2128
        will place the CPU into user mode, and has no effect if the CPU is
2129
        already in user mode.
2130
\item {\tt zip\_step()} executes an \hbox{\tt OR \$STEP|\$GIE,CC} instruction.
2131
        This will place the CPU into user mode in order to step one instruction,
2132
        and then return to supervisor mode.
2133
        It has no effect if the CPU is already in user mode.
2134
\item {\tt zip\_system()} executes an \hbox{\tt AND \textasciitilde\$GIE,CC}
2135
        instruction to return the CPU to supervisor mode.  This essentially
2136
        executes a trap, setting the trap bit for the supervisor to examine.
2137
        What this instruction does not do is arrange for the trap arguments to
2138
        be placed into the  registers {\tt R1} through {\tt R5}.  Since this is
2139
        a wholly inadequate solution, a function call may be made to an
2140
        assembly routine that executes a trap if necessary.
2141
\item {\tt zip\_wait()} executes a \hbox{\tt \$SLEEP|\$GIE,CC} instruction.
2142
        Unlike {\tt zip\_halt()}, this {\tt zip\_wait()} instruction places
2143
        the CPU into a wait state regardless of whether or not the CPU is
2144
        in supervisor mode or not.   When this function, i.e. instruction,
2145
        completes, it will leave the CPU in supervisor mode upon an interrupt
2146
        having taken place.
2147
 
2148
        You may wish to set the user program counter prior to this instruction,
2149
        as the prefetch unit will try to load instructions from the address
2150
        contained within the user program counter.  Attempts to read from
2151
        addresses with sideeffects may not produce the desired outcome.
2152
        However, once that cache fails (or succeeds), the CPU will have been
2153
        put to sleep and will do no more.
2154
 
2155
\item {\tt zip\_restore\_context(context *)} inserts the 32~assembly
2156
        instructions necessary to copy all sixteen user registers to a memory
2157
        region pointed to by the given context pointer, starting with {\tt uR0}
2158
        on up to {\tt uPC}.
2159
 
2160
\item {\tt zip\_save\_context(context *)} inserts the 32~assembly instructions
2161
        necessary to copy all sixteen user registers to a memory region pointed
2162
        to by the given context pointer argument, starting
2163
        with {\tt uR0} on up to {\tt uPC}.
2164
\item {\tt zip\_ucc()}, returns the value of the user CC register.
2165 33 dgisselq
\end{enumerate}
2166
 
2167 199 dgisselq
% Builtin functions:
2168
%       zip_break();
2169
%       zip_idle();
2170
%       zip_syscall(a,b,c,d)
2171
%
2172
\section{Linker Scripts}\label{sec:ld}
2173
The ZipCPU makes no assumptions about its memory layout.  The result, though,
2174
is that the memory layout of a given project is board specific.  This
2175
is accomplished via a board specific linker script.  This section will discuss
2176
some of the specifics of a ZipCPU linker script.
2177 33 dgisselq
 
2178 199 dgisselq
Because the ZipCPU uses a modified binutils package as part of its tool chain,
2179
the format for this linker script is defined by the GNU LD project within
2180
binutils.  Further details on that format may be found within the GNU LD
2181
documentation within the binutils package.
2182 33 dgisselq
 
2183 199 dgisselq
This discussion will focus on those parts of the script specific to the ZipCPU.
2184 33 dgisselq
 
2185 199 dgisselq
\subsection{Memory Types}\label{sec:ld-mem}
2186
Of the FPGA boards that the ZipCPU has been applied to, most of them have some
2187
combination of three types of memory: flash, block RAM, and Synchronous
2188
Dynamic RAM (SDRAM).  Of these three, only the flash is non--volatile.  The
2189
block RAM is the fastest, and the SDRAM the largest.  While other memory types
2190
are available, such as files on an external media such as an SD card or a
2191
network drive, these three types have so far been sufficient for our purposes.
2192
 
2193
To support these memories, the linker script has three memory lines identifying
2194
where each memory exists on the bus, the size of the memory, and any protections
2195
associated with it.  For example,
2196
\begin{eqnarray*}
2197
\mbox{blkram (wx) : ORIGIN = 0x0008000, LENGTH = 0x0008000}
2198
\end{eqnarray*}
2199
specifies that there is a region of memory, called blkram, that can be read and
2200
written, and that programs can execute from.  This section starts at address
2201
{\tt 0x8000} and extends for another {\tt 0x8000} words.  The other memories
2202
are defined in a similar manner, with names {\tt flash} and {\tt sdram}.
2203
 
2204
Following the memory section, three specific symbols are defined:
2205
        {\tt \_flash}, defining the beginning of flash memory,
2206
        {\tt \_blkram}, defining the beginning of on--chip block RAM,
2207
        and
2208
        {\tt \_sdram}, defining the beginning of SDRAM.
2209
These symbols are used to make the bootloader's task easier.
2210
 
2211
\subsection{The Entry Function}\label{sec:ld-entry}
2212
The ZipCPU has, as a parameter, a {\tt RESET\_ADDRESS}.  It is important
2213
that this address contain a valid instruction (or more), since this is the
2214
first instruction the ZipCPU will execute.  Traditionally, this address is also
2215
the first address in instruction memory as well.
2216
 
2217
To make this happen, the ZipCPU defines two additional segments: the
2218
{\tt .start} and the {\tt .boot} segments.  The {\tt  .start} segment is to
2219
have nothing in it but the very initial startup code.  This code needs to run
2220
from flash (or other ROM).  By placing this segment at the very beginning of
2221
the ZipCPU's flash address space, and in particular at the first valid flash
2222
address, the ZipCPU will boot from this address.  This is the purpose of the
2223
{\tt .start} section.
2224
 
2225
The {\tt .boot} section has a similar purpose.  This section includes anything
2226
associated with the bootloader.  It is a special section because, when loading
2227
from flash, the bootloader {\em cannot} be placed in RAM, but must be placed
2228
in flash--since it is the code that loads things from flash into RAM.
2229
 
2230
It may also make sense to place any code executed once only within flash as
2231
well.  Such code may run slower than the main system code, but by leaving it in
2232
flash it can be kept from consuming any higher speed RAM.  To do this, place
2233
this other code into the {\tt .boot} section.
2234
 
2235
You may also find that large data structures that are best left in flash
2236
can also be placed into this {\tt .boot} section as well for that purpose.
2237
 
2238
\subsection{Bootloader Tags}\label{sec:ld-boot}
2239
 
2240
The bootloader needs to know a couple things from the linker script.  It needs
2241
to know what code/data to copy to block RAM from the flash, what code/data to
2242
copy to SDRAM, and finally what initial data area needs to be zeroed.  Four
2243
additional pointers, set within a linker script, can define these regions.
2244
 
2245
\begin{enumerate}
2246
\item {\tt \_kernel\_image\_start}
2247
 
2248
        This is the first location in flash containing data that the bootloader
2249
        needs to move.
2250
 
2251
\item {\tt \_kernel\_image\_end}
2252
 
2253
        This is a pointer to one past the last location in block RAM to place
2254
        things into.  If this pointer is equal to {\tt \_kernel\_image\_start},
2255
        then no information is placed into block RAM.
2256
 
2257
\item {\tt \_sdram\_image\_start}
2258
 
2259
        This should be equal to {\tt \_kernel\_image\_end}.  It is a pointer,
2260
        within block RAM address space, of the first location to be moved
2261
        into SDRAM.  By adding the difference between
2262
        {\tt \_sdram\_image\_start} and {\tt \_blkram} to the flash address
2263
        in {\tt \_kernel\_image\_start}, the actual source address within the
2264
        flash of the code/data that needs to be copied into SDRAM can be
2265
        determined.
2266
 
2267
\item {\tt \_sdram\_image\_end}
2268
 
2269
        This is the ending address of any code/data to be copied into SDRAM.
2270
        The distance between this pointer and {\tt \_sdram} should be the
2271
        amount of data to be placed into SDRAM.
2272
 
2273
\item {\tt \_bss\_image\_end}
2274
 
2275
        The BSS segment contains data the starts with an initial value of
2276
        zero.  Such data are usually not placed in the executable file, nor
2277
        are they placed into any flash image.  This address points to the
2278
        last location in SDRAM used by the BSS segment.  The bootloader
2279
        is responsible then for clearing the SDRAM between
2280
        {\tt \_sdram\_image\_end} and {\tt \_bss\_image\_end}.
2281
 
2282
        The bootloader must also be robust enough to handle the cases where
2283
        1) there is no SDRAM, 2) there is no block RAM, and 3) where there
2284
        is non requirement to move memory at all---such as when the program
2285
        is placed into memory and started from there.
2286
\end{enumerate}
2287
\subsection{Other required linker symbols}\label{sec:ld-other}
2288
 
2289
Two other symbols need to be defined in the linker script, which are used
2290
by the startup code.  These are:
2291
\begin{enumerate}
2292
\item {\tt \_top\_of\_stack}
2293
 
2294
        This is the address that the startup code will set the stack pointer
2295
        to point to.  It may be one past the last location of a RAM memory,
2296
        whether block RAM or SDRAM.
2297
 
2298
\item {\tt \_top\_of\_heap}
2299
 
2300
        This is the first location past the end of the {\tt .bss} segment.
2301
        Equivalently, this is the address of the first unused piece of
2302
        memory, or the location from whence to start any dynamic memory
2303
        subsystem.
2304
\end{enumerate}
2305
 
2306
\section{Loading ZipCPU Programs}
2307
There are two basic ways to load a ZipCPU program, depending upon whether or
2308
not the ZipCPU is active within the current configuration.  If the ZipCPU
2309
is not a part of the current FPGA configuration, one need only write the
2310
flash and then switch configurations.  It will be the CPU's responsibility
2311
to place itself in RAM then.
2312
 
2313
The more practical alternative is a little more involved, and there are
2314
several steps to it.
2315
\begin{enumerate}
2316
\item Halt the CPU by writing 0x0440 to the CPU control register.  This
2317
        both halts and resets the CPU.  It then prevents both bus contention,
2318
        while writing the new instructions to memory, as well as preventing the
2319
        CPU from running some instructions from one program and other
2320
        instructions from another.
2321
\item Load the program into memory.  For many programs this will involve
2322
        loading the program into flash, and necessitate having and using a
2323
        flash controller.  The ZipCPU also supports being loaded straight into
2324
        RAM address as well, as though the bootloader had completed
2325
        it's task.
2326
\item You may optionally, at this point, clear all of the CPUs registers,
2327
        to make certain the reboot is clean.
2328
\item Set the sPC register to the starting address.
2329
\item Clear the instruction cache in order to force the CPU to reload its
2330
        cache upon start.
2331
\item Release the CPU by writing to the CPU debug control register a number
2332
        between 0 and 31.  This number will correspond to the register number
2333
        of the register that can be ``peeked'' at while the CPU is running.
2334
\end{enumerate}
2335
 
2336
%
2337
\section{Starting a ZipCPU program}
2338
\subsection{CRT0}
2339
 
2340
Most computers have a section of code, conventionally called {\tt crt0}, which
2341
loads a program into memory.  On the ZipCPU, this code starts at {\tt \_start}.
2342
It is responsible for setting the stack pointer, calling the boot loader,
2343
and then calling the main entry function, {\tt entry()}.
2344
 
2345
Because {\tt \_start} {\em must} be the first symbol in a program, and because
2346
that first symbol is located at the boot address for the CPU, the {\tt \_start}
2347
is placed into the {\tt .start} segment.  It is the only routine placed there.
2348
 
2349
On those CPU's that don't have enough logic space for a debugger, it may be
2350
useful to place a routine to dump any registers, stack values and/or kernel
2351
traces to an output routine at this time.  That way, on any kernel fault, the
2352
kernel can be brought back up with a debug trace.  This works because rebooting
2353
the CPU doesn't reset any register values save the {\tt sCC} and {\tt sPC}.
2354
 
2355
\subsection{The Bootloader}
2356
 
2357
As discussed in Sec.~\ref{sec:ld-boot}, the bootloader must be placed into
2358
flash if it is used.  It can be a small C program (it need not be assembly,
2359
like {\tt \_start}), and it only needs to copy memory.  First, it copies any
2360
memory from flash to block RAM.  Second, it copies any necessary memory from
2361
flash to SDRAM.  Then, it zeros any memory necessary in SDRAM (or block RAM,
2362
if there is no SDRAM).
2363
 
2364
These memory copies may be done with the DMA, or they may be done one--at--a
2365
time for a performance penalty.
2366
 
2367
\subsection{Kernel Entry}
2368
 
2369
After calling the boot loader, execution returns to the {\tt \_start} routine
2370
which then calls the main program entry function, {\tt entry()}.  No
2371
requirements are laid upon this entry function regarding where it must reside.
2372
The simplest place to put it is in Block RAM--and just to put all code and
2373
variables there.  In reality, this entry function may easily be left in flash.
2374
It often doesn't need to run particularly fast, since there may easily be
2375
one--time setup functions that are independent of the programs main loop.
2376
 
2377
\subsection{Kernel Main}
2378
 
2379
If the kernel entry function, {\tt entry()}, is placed in flash, it should call
2380
a separate function to run the main while loop once it has been set up.  In
2381
this fashion, the main while loop may be kept in the fastest memory necessary
2382
(that it will fit within), to ensure good performance.
2383
 
2384
\chapter{Operation}\label{chap:ops}
2385
 
2386
This chapter will explore how to perform common tasks with the ZipCPU,
2387
offering examples in both C and assembly for those tasks.
2388
 
2389
\section{CRT0}
2390
 
2391
Of course, the one task that every CPU must do is start the CPU for other
2392
tasks.  The ZipCPU is no different.  This is the one ZipCPU task that must
2393
take place in assembly, since no assumptions can be made about the state of
2394
the ZipCPU upon entry.  In particular, the stack pointer, SP, needs to be
2395
loaded with a valid memory location before any higher level language can work.
2396
Once that has taken place, it is then possible to call other higher level
2397
routines.
2398
 
2399
Table.~\ref{tbl:op-init}
2400
\begin{table}\begin{center}
2401
\begin{tabbing}
2402
{\em ; By starting our loader in the .start section, we guarantee through our}\\
2403
{\em ; linker script that these are the very first instructions the CPU sees.}\\
2404
\hbox to 0.25in{}\={\tt .section .start} \\
2405
\>      {\tt .global \_start} \\
2406
{\em ; \_start is to be placed at our reboot/reset address, so it will be}\\
2407
{\em ; called upon any reboot.}\\
2408
{\tt \_start:} \\
2409
\> {\em ; The most important step: creating a stack pointer.  The value}\\
2410
\> {\em ; {\tt \_top\_of\_stack} is created by the linker based upon the linker script.}\\
2411
\>      {\tt LDI \_top\_of\_stack,SP} \\
2412
\> {\em ; We then call the bootloader to load our code into memory.}\\
2413
\>      {\tt MOV \_after\_bootloader(PC),R0} \\
2414
\>      {\tt BRA bootloader} \\
2415
{\tt \_after\_bootloader:} \\
2416
\>      {\em ; Just in case the bootloader messed up the stack, we'll reset it here.}\\
2417
\>      {\tt LDI \_top\_of\_stack,SP} \\
2418
\>      {\em ; Finally, we call the entry function for the entire design.}\\
2419
\>      {\tt MOV \_kernel\_exit(PC),R0}\\
2420
\>      {\tt BRA entry}\\
2421
{\em ; The {\tt \_kernel\_exit} routine that follows isn't strictly necessary,}\\
2422
{\em ; since the CPU should never return from the {\tt entry()} function.  However,}\\
2423
{\em ; since returning from such a function is valid C code, and just in case}\\
2424
{\em ; it does return, we provide this function as a fail safe to make sure}\\
2425
{\em ; the kernel halts upon completion.}\\
2426
{\tt \_kernel\_exit:}\\
2427
\> {\tt HALT}\\
2428
\> {\tt BRA \_kernel\_exit}
2429
\end{tabbing}
2430
\caption{Setting up a stack frame and starting the CPU}\label{tbl:op-init}
2431
\end{center}\end{table}
2432
presents an example of one such initialization routine
2433
that first sets up the stack, then calls a bootloader routine.  Upon completion,
2434
the initialization routine then calls the main entry point for the CPU.  Should
2435
that main entry point ever return, a short routine following halts the CPU.
2436
 
2437
The example also highlights one optimization that didn't take place.  Instead
2438
of placing the {\tt \_after\_bootloader} address into {\tt R0}, this script
2439
could have placed the {\tt entry()} address into {\tt R0}.  Had it done so, the
2440
CPU would not have suffered the pipeline stalls associated with two long jumps:
2441
the first to {\tt R0}, and the second to {\tt entry}.  Instead, it would have
2442
suffered such stalls only once: when jumping to {\tt entry()}.
2443
 
2444
% \section{Example bootloader}
2445
 
2446 68 dgisselq
\section{System High}
2447 199 dgisselq
The easiest and simplest way to run the ZipCPU is in the system high mode.
2448 68 dgisselq
In this mode, the CPU runs your program in supervisor mode from reboot to
2449
power down, and is never interrupted.  You will need to poll the interrupt
2450
controller to determine when any external condition has become active.  This
2451 199 dgisselq
mode is incredibly useful, and can handle many microcontroller--type tasks.
2452 68 dgisselq
 
2453
Even better, in system high mode, all of the user registers are available
2454
to the system high program as variables.  Accessing these registers can be
2455
done in a single clock cycle, which would move them to the active register
2456
set or move them back.  While this may seem like a load or store instruction,
2457
none of these register accesses will suffer from memory delays.
2458
 
2459
The one thing that cannot be done in supervisor mode is a wait for interrupt
2460
instruction.  This, however, is easily rectified by jumping to a user task
2461
within the supervisors memory space, such as Tbl.~\ref{tbl:shi-idle}.
2462
\begin{table}\begin{center}
2463
\begin{tabbing}
2464
{\tt supervisor\_idle:} \\
2465
\hbox to 0.25in{}\={\em ; While not strictly required, the following move helps to} \\
2466
\>      {\em ; ensure that the prefetch doesn't try to fetch an instruction} \\
2467
\>      {\em ; outside of the CPU's address space when it switches to user} \\
2468
\>      {\em ; mode.} \\
2469
\>      {\tt MOV supervisor\_idle\_continue,uPC} \\
2470
\>      {\em ; Put the processor into user mode and to sleep in the same} \\
2471
\>      {\em ; instruction. } \\
2472
\>      {\tt OR \$SLEEP|\$GIE,CC} \\
2473
{\tt supervisor\_idle\_continue:} \\
2474
\>      {\em ; Now, if we haven't done this inline, we need to return} \\
2475
\>      {\em ; to whatever function called us.} \\
2476
\>      {\tt RETN} \\
2477
\end{tabbing}
2478
\caption{Executing an idle from supervisor mode}\label{tbl:shi-idle}
2479
\end{center}\end{table}
2480
 
2481 199 dgisselq
There are some problems with this model, however.  For example, even though
2482
the user registers can be accessed in a single cycle, there is currently
2483
no way to do so other than with assembly instructions.
2484
 
2485
An alternative to this approach is to use the {\tt zip\_wait()} built--in
2486
function.  This places the ZipCPU into an idle/sleep mode to wait for
2487
interrupts.  Because the supervisor puts the CPU to sleep, rather than the
2488
user, no user context needs to be set up.
2489
 
2490
\section{A Programmable Delay}
2491
 
2492
One common task in microcontrollers, whether in a user task or supervisor
2493
task, is to wait for a programmable amount of time.  Using the ZipSystem,
2494
there are several peripherals that can be used to create such a delay.
2495
It can be done with one of the three timers, the jiffies, or even an off-chip
2496
ZipCounter.
2497
 
2498
Here, in Tbl.~\ref{tbl:shi-timer},
2499
\begin{table}\begin{center}
2500
\begin{tabbing}
2501
{\tt \#define EINT(A) (0x80000000|(A<<16))} \= {\em // Enable interrupt A}\\
2502
{\tt \#define DINT(A) (A<<16)} \>{\em // Just disable the interrupts in A}\\
2503
{\tt \#define DISABLEALL 0x7fff0000} \>{\em // Disable all interrupts}\\
2504
{\tt \#define CLEARPIC 0x7fff7fff} \>{\em // Clears and disables all interrupts}\\
2505
{\tt \#define SYSINT\_TMA 0x10} \>{\em // The Timer--A interrupt mask}\\
2506
\\
2507
{\tt void timer\_delay(int nclocks) \{} \\
2508
\hbox to 0.25in{}\= {\em // Clear the PIC.  We want to exit from here on timer counts alone}\\
2509
        \> {\tt zip->pic = DISABLEALL|SYSINT\_TMA;}\\
2510
        \> {\tt if (nclocks > 10) \{}\\
2511
        \> \hbox to 0.25in{}\= {\em // Set our timer to count down the given number of counts}\\
2512
        \> \> {\tt zip->tma = counts} \\
2513
        \> \> {\tt zip->pic = EINT(SYSINT\_TMA);} \\
2514
        \> \> {\tt zip\_wait();} \\
2515
        \> \> {\tt zip->pic = CLEARPIC;} \\
2516
        \> {\tt \} }{\em // else anything less has likely already passed}
2517
{\tt \}}\\
2518
\end{tabbing}
2519
\caption{Waiting on a timer}\label{tbl:shi-timer}
2520
\end{center}\end{table}
2521
we present one means of waiting for a programmable amount of time using a
2522
timer.  If exact timing is important, you may wish to calibrate the method
2523
by subtracting from the counts number the counts it takes to actually do the
2524
routine.  Otherwise, the timer is guaranteed to at least {\tt counts}
2525
ticks.
2526
 
2527
Notice that the routine clears the PIC early on.  While one might expect
2528
that this could be done in the instruction immediately before {\tt zip\_rtu()},
2529
this isn't the case.  The reason is a race condition created by the fact that
2530
the write to the PIC completes after the {\tt zip\_rtu()} instruction.  As a
2531
result, you might find yourself with a zero delay simply because the timer
2532
had tripped some time earlier.
2533
 
2534
The routine is also careful not to clear any other interrupts beyond the timer
2535
interrupt, lest some other condition trip that the user was also waiting on.
2536
 
2537 68 dgisselq
\section{Traditional Interrupt Handling}
2538 199 dgisselq
Although the ZipCPU does not have a traditional interrupt architecture,
2539 68 dgisselq
it is possible to create the more traditional interrupt approach via software.
2540
In this mode, the programmable interrupt controller is used together with the
2541
supervisor state to create the illusion of more traditional interrupt handling.
2542
 
2543
To set this up, upon reboot the supervisor task:
2544
\begin{enumerate}
2545
\item Creates a (single) user context, a user stack, and sets the user
2546
        program counter to the entry of the user task
2547
\item Creates a task table of ISR entries
2548
\item Enables the master interrupt enable via the interrupt controller, albeit
2549
        without enabling any of the fifteen potential underlying interrupts.
2550
\item Switches to user mode, as the first part of the while loop in
2551
        Tbl.~\ref{tbl:traditional-isr}.
2552
\end{enumerate}
2553
\begin{table}\begin{center}
2554
\begin{tabbing}
2555
{\tt while(true) \{} \\
2556 199 dgisselq
\hbox to 0.25in{}\= {\tt zip\_rtu();}\\
2557
        \> {\tt if (zip\_ucc() \& CC\_TRAPBIT) \{} {\em // Here, we allow users to install ISRs, or} \\
2558 68 dgisselq
        \>\hbox to 0.25in{}\= {\em // whatever else they may wish to do in supervisor mode.} \\
2559 199 dgisselq
        \>\> {\tt \ldots} \\
2560
        \> {\tt \} else (zip\_ucc() \& (CC\_BUSERR|CC\_FPUERR|CC\_DIVERR)) \{}\\
2561
        \>\> {\em // Here we handle any faults that the CPU may have
2562
                encountered }\\
2563
        \>\> {\em // The easiest solution is often to print a trace and reboot}\\
2564
        \>\> {\em // the CPU.}\\
2565
        \>\> {\tt \_start();} \\
2566 68 dgisselq
        \> {\tt \} else \{} \\
2567
        \> \> {\em // At this point, we know an interrupt has taken place:  Ask the programmable}\\
2568
        \> \> {\em // interrupt controller (PIC) which interrupts are enabled and which are active.}\\
2569 199 dgisselq
        \> \>   {\tt int        picv = zip->pic;}\\
2570 68 dgisselq
        \> \>   {\em // Turn off all active interrupts}\\
2571
        \> \>   {\em // Globally disable interrupt generation in the process}\\
2572
        \> \>   {\tt int        active = (picv >> 16) \& picv \& 0x07fff;}\\
2573 199 dgisselq
        \> \>   {\tt zip->pic = (active<<16);}\\
2574 68 dgisselq
        \> \>   {\em // We build a mask of interrupts to re-enable in picv.}\\
2575
        \> \>   {\tt picv = 0;}\\
2576
        \> \>   {\tt for(int i=0,msk=1; i<15; i++, msk<<=1) \{}\\
2577
        \> \>\hbox to 0.25in{}\={\tt if ((active \& msk)\&\&(isr\_table[i])) \{}\\
2578 199 dgisselq
        \> \>\>\hbox to 0.25in{}\={\em // Here we call our interrupt service routine.}\\
2579
        \> \>\>\hbox to 0.25in{}\= {\tt tmp = (isr\_table[i])(); }\\
2580 68 dgisselq
        \> \>\>\>       {\em // The tricky part is that, because of how the PIC is built, the ISR cannot}\\
2581 199 dgisselq
        \>\>\>\>        {\em // re-enable its own interrupts without re-enabling all interrupts.  Hence, we}\\
2582
        \>\>\>\>        {\em // look at the return value from the ISR to know if an interrupt needs to be }\\
2583 68 dgisselq
        \> \>\>\>       {\em // re-enabled. }\\
2584 199 dgisselq
        \> \>\>\>       {\tt if (tmp)} \\
2585
        \> \>\>\>       \hbox to 0.25in{}\={\tt picv |= msk; }\\
2586 68 dgisselq
        \> \>\>         {\tt \} }\\
2587
        \> \>   {\tt \} }\\
2588 199 dgisselq
        \> \>   {\em // Re-activate, but do not clear, all (requested) interrupts }\\
2589
        \> \>   {\tt zip->pic = picv | 0x80000000; }\\
2590 68 dgisselq
        \>{\tt \} }\\
2591
{\tt \}}\\
2592
\end{tabbing}
2593
\caption{Traditional Interrupt handling}\label{tbl:traditional-isr}
2594
\end{center}\end{table}
2595
 
2596
We can work through the interrupt handling process by examining
2597
Tbl.~\ref{tbl:traditional-isr}.  First, remember, the CPU is always running
2598
either the user or the supervisor context.  Once the supervisor switches to
2599 199 dgisselq
user mode, control does not return until either an interrupt, a trap, or an
2600
exception has taken place.  Therefore, if neither the trap bit nor any of the
2601
exception bits have been set, then we know an interrupt has taken place.
2602 68 dgisselq
 
2603 199 dgisselq
It is also possible that an interrupt will occur coincident with a trap or
2604
exception.  If this is the case, the subsequent {\tt zip\_rtu()} instruction
2605
will return immediately, since the interrupt has yet to be cleared.
2606 68 dgisselq
 
2607
As Sec.~\ref{sec:pic} discusses, the top of the PIC register stores which
2608
interrupts are enabled, and the bottom stores which have tripped.  (Interrupts
2609
may trip without being enabled, they just will not generate an interrupt to the
2610
CPU.)  Our first step is to query the register to find out our interrupt
2611
state, and then to disable any interrupts that have tripped.  To do
2612
that, we write a one to the enable half of the register while also clearing
2613
the top bit (master interrupt enable).  This has the consequence of disabling
2614
any and all further interrupts, not just the ones that have tripped.  Hence,
2615
upon completion, we re--enable the master interrupt bit again.   Finally,
2616
we keep track of which interrupts have tripped.
2617
 
2618
Using the bit mask of interrupts that have tripped, we walk through all fifteen
2619 199 dgisselq
possible interrupts.  If there is an ISR installed, we simply call it here.  The
2620
ISR, however, cannot re--enable its interrupt without re-enabling the master
2621
interrupt bit.  Thus, to keep things simple, when the ISR is finished it returns
2622
a boolean into R0 to indicate whether or not the interrupt needs to be
2623
re-enabled.  Put together, this tells the kernel which interrupts to re--enable.
2624
As a final instruction, interrupts are re--enabled before returning continuing
2625
the while loop.
2626 68 dgisselq
 
2627 199 dgisselq
There you have it: the ZipCPU, with its non-traditional interrupt architecture,
2628
can still process interrupts in a very traditional fashion.
2629
 
2630
\section{Idle Task}
2631
One task every operating system needs is the idle task, the task that takes
2632
place when nothing else can run.  On the ZipCPU, this task is quite simple,
2633
and it is shown in assembly in Tbl.~\ref{tbl:idle-asm},
2634 68 dgisselq
\begin{table}\begin{center}
2635
\begin{tabbing}
2636 199 dgisselq
{\tt idle\_task:} \\
2637
\hbox to 0.25in{}\= {\em ; Wait for the next interrupt, then switch to supervisor task} \\
2638
\>        {\tt WAIT} \\
2639
\>        {\em ; When we come back, it's because the supervisor wishes to} \\
2640
\>        {\em ; wait for an interrupt again, so go back to the top.} \\
2641
\>        {\tt BRA idle\_task} \\
2642 68 dgisselq
\end{tabbing}
2643 199 dgisselq
\caption{Example Idle Task in Assembly}\label{tbl:idle-asm}
2644 68 dgisselq
\end{center}\end{table}
2645 199 dgisselq
or equivalently in C in Tbl.~\ref{tbl:idle-c}.
2646
\begin{table}\begin{center}
2647
\begin{tabbing}
2648
{\tt void idle\_task(void) \{} \\
2649
\hbox to 0.25in{}\={\tt while(true) \{} {\em // Never exit}\\
2650
\> {\em // Wait for the next interrupt, then switch to supervisor task} \\
2651 68 dgisselq
 
2652 199 dgisselq
\> {\tt zip\_wait();} \\
2653
\> {\em // } \\
2654
\> {\em // When we come back, it's because the supervisor wishes to} \\
2655
\> {\em // wait for an interrupt again, so go back to the top.} \\
2656
\> {\tt \}} \\
2657
{\tt \}}
2658
\end{tabbing}
2659
\caption{Example Idle Task in C}\label{tbl:idle-c}
2660
\end{center}\end{table}
2661 68 dgisselq
 
2662 36 dgisselq
When this task runs, the CPU will fill up all of the pipeline stages up the
2663
ALU.  The {\tt WAIT} instruction, upon leaving the ALU, places the CPU into
2664 199 dgisselq
a sleep state where nothing more moves.  Then, once an interrupt takes place,
2665
control passes to the supervisor task to handle the interrupt.  When control
2666
passes back to this task, it will be on the next instruction.  Since that next
2667
instruction sends us back to the top of the task, the idle task thus does
2668
nothing but wait for an interrupt.
2669 36 dgisselq
 
2670
This should be the lowest priority task, the task that runs when nothing else
2671
can.  It will help lower the FPGA power usage overall---at least its dynamic
2672
power usage.
2673
 
2674 199 dgisselq
For those highly interested in reducing power consumption, the clock could
2675
even be disabled at this time--requiring only some small modifications to the
2676
core.
2677
 
2678
\section{Memory Copy}
2679
One common operation is that of a memory move or copy.  This section will
2680
present several methods available to the ZipCPU for performing a memory
2681
copy, starting with the C code shown in Tbl.~\ref{tbl:memcp-c}.
2682 36 dgisselq
\begin{table}\begin{center}
2683
\parbox{4in}{\begin{tabbing}
2684 199 dgisselq
{\tt void} \= {\tt memcpy(void *dest, void *src, int len) \{} \\
2685 36 dgisselq
        \> {\tt for(int i=0; i<len; i++)} \\
2686
        \> \hspace{0.2in} {\tt *dest++ = *src++;} \\
2687
\}
2688
\end{tabbing}}
2689
\caption{Example Memory Copy code in C}\label{tbl:memcp-c}
2690
\end{center}\end{table}
2691 199 dgisselq
Each successive example will further speed up the memory copying process.
2692
 
2693
This memory copy code can be translated in Zip Assembly as shown in
2694 36 dgisselq
Tbl.~\ref{tbl:memcp-asm}.
2695
\begin{table}\begin{center}
2696 199 dgisselq
\begin{tabbing}
2697
memcpy: \\
2698
\hbox to 0.35in{}\={\em ; R0 = return address, R1 = *dest, R2 = *src, R3 = LEN} \\
2699
\>      {\em ; The following will operate in 6 ($N=0$), or $2+12N$ clocks ($N\neq 0$).} \\
2700
\>      {\tt CMP 0,R3} \\ % 8 clocks per setup
2701
\>      {\tt JMP.Z R0} \hbox to 0.3in{}\= {\em ; A conditional return }\\
2702
\>      {\em ; No stack frame needs to be set up to use {\tt R4}, since the compiler}\\
2703
\>      {\em  ; assumes {\tt R1}-{\tt R4} may be used and changed by any subroutine} \\
2704
memcpy\_loop: \\ % 12 clocks per loop
2705
\>      {\tt LOD (R2),R4} \\
2706
\>      {\em ; (4 stalls, cannot be scheduled away)} \\
2707
\>      {\tt STO R4,(R1)} \> {\em ; (4 schedulable stalls, has no impact now)} \\
2708
\>      {\em ; Update our count of the number of remaining values to copy}\\
2709
\>      {\tt SUB 1,R3}  \> {\em ; This will be zero when we have copied our last}\\
2710
\>      {\tt JMP.Z R0}  \> {\em ; + 4 stalls, if taken}\\
2711
\>      {\tt ADD 1,R1}  \> {\em ; Implement the destination pointer }\\
2712
\>      {\tt ADD 1,R2}  \> {\em ; Implement the source pointer }\\
2713
\>      {\tt BRA memcpy\_loop} \\
2714
\>      {\em ; (1 stall on a BRA instruction)} \\
2715
\end{tabbing}
2716
\caption{Example Memory Copy code in Zip Assembly, Unoptimized}\label{tbl:memcp-asm}
2717 36 dgisselq
\end{center}\end{table}
2718 199 dgisselq
This example points out several things associated with the ZipCPU.  First,
2719 36 dgisselq
a straightforward implementation of a for loop is not the fastest loop
2720
structure.  For this reason, we have placed the test to continue at the
2721
end.  Second, all pointers are {\tt void} pointers to arbitrary 32--bit
2722 199 dgisselq
data types.  The ZipCPU does not have explicit support for smaller or larger
2723
data types, and so this memory copy cannot be applied at an 8--bit level.
2724
Third, notice that we can use {\tt R4} without storing it, since the C~ABI
2725
allows for subroutines to use {\tt R1}--{\tt R4} without saving them.  This
2726
means that we can return from this subroutine using conditional jumps to
2727
{\tt R0}.
2728 36 dgisselq
 
2729 199 dgisselq
Still, there's more that could be done.  Suppose we wished to use the pipeline
2730
bus capability?  We might then write something closer to
2731
Tbl.~\ref{tbl:memcp-opt}.
2732
\begin{table}\begin{center}\scalebox{0.8}{\parbox{\textwidth}{%
2733
\begin{tabbing}
2734
% 27 cycles for 0
2735
% 52 cycles for 3
2736
{\em ; Upon entry, R0 = return address, R1 = *dest, R2 = *src, R3 = LEN} \\
2737
{\em ; Achieves roughly $32+17\left\lfloor\frac{N}{4}\right\rfloor$ clocks,
2738
        after the initial pipeline delay}\\
2739
memcpy\_opt: \\
2740
\hbox to 0.35in{}\=\hbox to 1.4in{\tt CMP 4,R3}\= {\em ; Check for small short lengths, len $<$ 4}\\
2741
\>      {\tt BC memcpy\_finish} \> {\em ; Jump to the end if so}\\
2742
\hbox to 0.35in{}\=\hbox to 1.4in{\tt SUB 3,SP}\= {\em ; Otherwise, create a stack frame, storing the registers}\\
2743
\>      {\tt STO R5,(SP)}       \> {\em ; we will be using.  Note that this is a pipelined store, so}\\
2744
\>      {\tt STO R6,1(SP)}      \> {\em ; subsequent stores only cost 1 clock.}\\
2745
\>      {\tt STO R7,2(SP)}\\
2746
\>      {\tt ADD 4,R2}          \> {\em ; Pre-Increment our pointers, for a 4-stage pipeline.  This}\\
2747
\>      {\tt ADD 4,R1}          \> {\em ; also fills up the 3 of the 4 stall states following the}\\
2748
\>      {\tt SUB 5,R3}          \> {\em ; stores.  Also, leave {\tt R3} as the number left minus one.}\\
2749
\>      {\tt LOD -4(R2),R4}     \> {\em ; Load the first four values into }\\
2750
\>      {\tt LOD -3(R2),R5}     \> {\em ; registers, using a pipelined load.}\\
2751
\>      {\tt LOD -2(R2),R6}\\
2752
\>      {\tt LOD -1(R2),R7}\\
2753
{\tt mcopy\_next\_four\_chars:} \>\> {\em ; Here's the top of our copy loop}\\
2754
\>      {\tt STO  R4,-4(R1)}    \> {\em ; Store four values, using a burst memory operation.}\\
2755
\>      {\tt STO  R5,-3(R1)}    \> {\em ; One clock for subsequent stores.}\\
2756
\>      {\tt STO  R6,-2(R1)}    \> {\em ; None of these effect the flags, that were set when}\\
2757
\>      {\tt STO  R7,-1(R1)}    \> {\em ; we last adjusted {\tt R3}}\\
2758
\>      {\tt BC  preend\_memcpy} \> {\em ; +4 stall cycles, but only when taken}\\
2759
\>      {\tt ADD  4,R1} \> {\em ; ALU ops don't stall during stores, so}\\
2760
\>      {\tt ADD  4,R2} \> {\em ; increment our pointers here.} \\
2761
\>      {\tt SUB  4,R3} \> {\em ; Calculate whether or not we have a next round}\\
2762
\>      {\tt LOD  -4(R2),R4} \> {\em ; Preload the values for the next round}\\
2763
\>      {\tt LOD  -3(R2),R5}\>  {\em ; Notice that these are also pipelined}\\
2764
\>      {\tt LOD  -2(R2),R6}\>  {\em ; loads, as before.}\\
2765
\>      {\tt LOD  -1(R2),R7}\>  {\em ; The four stall cycles, though, are concurrent w/ the branch.}\\
2766
\>      {\tt BRA  mcopy\_next\_char} \> {\em ; Early branching avoids the full memory pipeline stall} \\
2767
{\tt preend\_memcpy:}\\
2768
\>      {\tt ADD  1,R3} \>{\em ; R3 is now the remaining length, rather than one less than it}\\
2769
\>      {\tt LOD (SP),R5}  \> {\em ; Restore our saved registers, since the remainder of the routine}\\
2770
\>      {\tt LOD 1(SP),R6} \> {\em ; doesn't use these registers}\\
2771
\>      {\tt LOD 2(SP),R7} \> {\em ;}\\
2772
\>      {\tt ADD 3,SP}  \>{\em ; Adjust the stack pointer back to what it was}\\
2773
{\tt memcpy\_finish:}\>\>{\em ; At this point, there are $0\leq$ {\tt R3}$<4$ words left}\\
2774
\>      {\tt CMP 1,R3} \> {\em ; Check if any ops are remaining }\\
2775
\>      {\tt JMP.LT R0} \> {\em ; Return now if nothing is left}\\
2776
\>      {\tt LOD (R1),R4} \> {\em ; Load and store the first item}\\
2777
\>      {\tt STO R4,(R1)} \> {\em ;}\\
2778
\>      {\tt JMP.Z R0}  \> {\em ; Return if that was our only value}\\
2779
\>      {\tt LOD 1(R1),R4}\>{\em; Load and store the second item (if necessary)} \\
2780
\>      {\tt STO R4,1(R1)}\\
2781
\>      {\tt CMP 2, R3}\\
2782
\>      {\tt JMP.LT R0}\\
2783
\>      {\tt LOD 2(R1),R4}\>{\em; Load and store the second item (if necessary)} \\
2784
\>      {\tt STO R4,2(R1)}\>{\em; {\tt LOD}, {\tt STO}, {\tt JMP R0} will cost 10 cycles}\\
2785
\>      {\tt JMP     R0} \> {\em ; Finally, we return}\\
2786
\end{tabbing}}}
2787
\caption{Example Memory Copy code in Zip Assembly, Hand Optimized}\label{tbl:memcp-opt}
2788
\end{center}\end{table}
2789
This pipeline memory example, though, provides some neat things to discuss
2790
about optimizing code using the ZipCPU.
2791 36 dgisselq
 
2792 199 dgisselq
First, note that all of the loads and stores, except the three following
2793
{\tt memcpy\_finish}, are pipelined.  To do this, we needed to unroll the
2794
copy loop by a factor of four.  This means that each time through the loop,
2795
we can read and store four values.  At 17~clocks to copy four values, that's
2796
roughly three times faster than our previous example.  The down side, though,
2797
is that the loop now needs a final cleanup section where the last 0--3 values
2798
will be copied.
2799
 
2800
Second, note that we used our remaining length minus one as our loop variable.
2801
This was done so that the conditions set by subtracting four from our loop
2802
variable could be used without a separate compare.  Speaking of the compare,
2803
note that we have chosen to use a branch if carry ({\tt BC}) comparison, which
2804
is equivalent to a less--than unsigned comparison.
2805
 
2806
Third, notice how we packed four ALU instructions, two adds, a subtract, and a
2807
conditional branch, after the four store instructions.  These instructions can
2808
complete while the memory unit is busy, preparing us to start the subsequent
2809
load without any further stalls (unless the memory is particularly slow.)
2810
 
2811
Next, you may wish to notice that the four memory loads within the loop are
2812
followed by the early branching instruction.  As a result, the branch costs
2813
no extra clocks, and the time between the loads at the bottom of the loop
2814
is dominated by the load to store time frame.
2815
 
2816
Finally, notice how the comparison at the end has been stacked.  By comparing
2817
against one, we can return when there are zero items left, or one item left,
2818
without needing a new comparison.  Hence, zero to three separate values can be
2819
copied using only two compares.
2820
 
2821
However, this discussion wouldn't be complete without an example of how
2822
this memory operation would be made even simpler using the direct memory
2823
access controller.  In that case, we can return to C with the code in
2824
Tbl.~\ref{tbl:memcp-dmac}.
2825
\begin{table}\begin{center}
2826
\begin{tabbing}
2827
{\tt \#define DMACOPY 0x0fed0000} {\em // Copy memory, largest chunk at a time possible} \\
2828
\\
2829
{\tt void} \= {\tt memcpy\_dma(void *dest, void *src, int len) \{} \\
2830
        \> {\em // This assumes we have access to the DMA, that the DMA is not}\\
2831
        \> {\em // busy, and that we are running in system high mode ...}\\
2832
        \> {\tt zip->dma.len = len;} \= {\em // Set up the DMA }\\
2833
        \> {\tt zip->dma.rd  = src;}\\
2834
        \> {\tt zip->dma.wr  = dst;}\\
2835
        \> {\em // Command the DMA to start copying} \\
2836
        \> {\tt zip->dma.ctrl= DMACOPY;} \\
2837
        \> {\em // Note that we take two clocks to set up our PIC.  This is }\\
2838
        \> {\em // required because the PIC takes at least a clock cycle to clear.} \\
2839
        \> {\tt zip->pic = DISABLEALL|SYSINT\_DMA;} \\
2840
        \> {\em // Now that our PIC is actually clear, with no more DMA }\\
2841
        \> {\em // interrupt within it, now we enable the DMA interrupt, and}\\
2842
        \> {\em // only the DMA interrupt.}\\
2843
        \> {\tt zip->pic = EINT(SYSINT\_DMA);}\\
2844
        \> {\em // And wait for the DMA to complete.} \\
2845
        \> {\tt zip\_wait();}\\
2846
{\tt \}}
2847
\end{tabbing}
2848
\caption{Example Memory Copy code using the DMA}\label{tbl:memcp-dmac}
2849
\end{center}\end{table}
2850
For large memory amounts, the cost of this approach will scale at roughly
2851
2~clocks per word transferred.
2852
 
2853
Notice how much simpler this memory copy has become to write by using the DMA.
2854
But also consider, the system has only one direct memory access controller.
2855
What happens if one task tries to use the controller when it is already in use
2856
by another task?  The result is that the direct memory access controller may
2857
need some special protections to make certain that only one task uses it at a
2858
time---much like any other hardware peripheral.
2859
 
2860
\section{Memset}
2861
Another example worth discussing is the {\tt memset()} library function.
2862
A straightforward implementation of this function in C might look like
2863
Tbl.~\ref{tbl:memset-c}.
2864
\begin{table}\begin{center}
2865
\begin{tabbing}
2866
\hbox to 0.4in{\tt void} \= {\tt *memset(void *s, int c, size\_t n) \{} \\
2867
        \> {\tt for(size\_t i=0; i<n; i++)} \\
2868
        \> \hspace{0.4in} {\tt *s++ = c;} \\
2869
        \> {\tt return s;}\\
2870
{\tt \}}
2871
\end{tabbing}
2872
\caption{Example Memset code}\label{tbl:memset-c}
2873
\end{center}\end{table}
2874
The function is simple enough to handle compile into the assembling listing in
2875
Tbl.~\ref{tbl:memset-unop}.
2876
\begin{table}\begin{center}
2877
\begin{tabbing}
2878
{\em ; Upon entry, R0 = return address, R1 = s, R2 = c, R3 = len}\\
2879
{\em ; Cost: Roughly $4+6N$ clocks}\\
2880
{\tt memset:}\\
2881
\hbox to 0.25in{}\=\hbox to 1in{\tt TST R3}\={\em ; Return immediately if len (R3) is zero}\\
2882
\>      {\tt JMP.Z R0}\\
2883
\>      {\tt MOV R1,R4} \> {\em ; Keep our return value in R1, use R4 as a local}\\
2884
{\tt memset\_loop:}\>\> {\em ; Here, we know we have at least one more to go}\\
2885
\>      {\tt STO R2,(R4)} \> {\em       ; Store one value (no pipelining)} \\
2886
\>      {\tt SUB 1,R3} \> {\em; Subtract during the store}\\
2887
\>      {\tt JMP.Z R0} \> {\em; Return (during store) if all done}\\
2888
\>      {\tt ADD 1,R4} \> {\em; Otherwise increment our pointer}\\
2889
\>      {\tt BRA memset\_loop} {\em ; and repeat}\\
2890
\end{tabbing}
2891
\caption{Example Memset code, minimally optimized}\label{tbl:memset-unop}
2892
\end{center}\end{table}
2893
Note that we grab {\tt R4} as a local variable, so that we can maintain the
2894
source pointer in {\tt R1} as our result upon return.  This is valid, since the
2895
compiler assumes that {\tt R1}--{\tt R4} will be clobbered upon any function
2896
call and so they are not saved.
2897
 
2898
You can also see that this straight forward implementation costs about
2899
six clocks per value to be set.
2900
 
2901
Were we to pipeline the memory accesses, we might choose to unroll the loop
2902
and do something more like Tbl.~\ref{tbl:memset-pipe}.
2903
\begin{table}\begin{center}
2904
\begin{tabbing}
2905
{\em ; Upon entry, R0 = return address, R1 = s, R2 = c, R3 = len}\\
2906
{\em ; Cost: roughly $20+9\left\lfloor\frac{N}{4}\right\rfloor$}\\
2907
{\tt memset\_pipe:}\\
2908
\hbox to 0.25in{}\=\hbox to 0.6in{\tt MOV}\=\hbox to 1.0in{\tt R1,R4}\={\em ; Make a local copy of *s, so we can return R1}\\
2909
\>      {\tt CMP}\>{\tt 4,R3}\>{\em ; Jump to non--unrolled section}\\
2910
\>      {\tt JMP.C}\>{\tt memset\_pipe\_tail}\\
2911
\>      {\tt SUB}\>{\tt 1,R3}\> {\em ; R3 is now one less than the number to finish}\\
2912
{\tt memset\_pipe\_unrolled:}\>\>\> {\em ; Here, we know we have at least four more to go}\\
2913
\>      {\tt STO}\>{\tt R2,(R4)} \> {\em  ; Store our four values, pipelining our}\\
2914
\>      {\tt STO}\>{\tt R2,1(R4)} \> {\em ; access across the bus }\\
2915
\>      {\tt STO}\>{\tt R2,2(R4)} \\
2916
\>      {\tt STO}\>{\tt R2,3(R4)} \\
2917
\>      {\tt SUB}\>{\tt 4,R3} \> {\em; If there are zero left, this will be a -1 result}\\
2918
\>      {\tt JMP.C}\>{\tt prememset\_pipe\_tail}\> \hbox to 0.5in{}\= {\em; So we can use our LT condition}\\
2919
\>      {\tt ADD}\>{\tt 4,R4} \> {\em ; Otherwise increment our pointer}\\
2920
\>      {\tt BRA}\>{\tt memset\_pipe\_loop} {\em ; and repeat using an early branchable instruction}\\
2921
{\tt prememset\_pipe\_tail:} \\
2922
\>    {\tt ADD}\>{\tt 1,R3}\>{\em ; Return our counts left to the run number}\\
2923
{\tt memset\_pipe\_tail:}\>\>\>{\em ; At this point, we have R3=0-3 remaining}\\
2924
\>      {\tt CMP}\>{\tt 1,R3}   \> {\em ; If there's less than one left}\\
2925
\>      {\tt JMP.C}\>{\tt R0}   \> {\em ; then return early.}\\
2926
\>      {\tt STO}\>{\tt R2,(R4)} \> {\em ; If we've got one left, store it}\\
2927
\>      {\tt STO.GT}\>{\tt R2,1(R4)} \> {\em ; if two, do a burst store}\\
2928
\>      {\tt CMP}\>{\tt 3,R3}   \> {\em ; Check if we have another left}\\
2929
\>      {\tt STO.Z}\>{\tt R2,2(R4)}     \> {\em ; and store it if so.}\\
2930
\>      {\tt JMP}\>{\tt R0}     \> {\em ; Return now that we are complete.}
2931
\end{tabbing}
2932
\caption{Example Memset after loop unrolling, using pipelined memory ops}\label{tbl:memset-pipe}
2933
\end{center}\end{table}
2934
Note that, in this example as with the {\tt memcpy} example, our loop variable
2935
is one less than the number of operations remaining.  This is because the ZipCPU
2936
has no less than or equal comparison, but only a less than comparison.  Further,
2937
because the length is given as an unsigned quantity, we {\em only} have a
2938
less than comparison.  By subtracting one from the loop variable, that's
2939
all our comparison needs to be--at least, until the end of the loop.  For
2940
that, we jump to a section one instruction earlier and return our counts
2941
value to the true remaining length.
2942
 
2943
You may also notice that, despite the four possibilities in the end game, we
2944
can carefully rearrange the logic to only use two compares.  The first compare
2945
tests against less than one and returns if there are no more sets left.  Using
2946
the same compare, though, we can also know if we have one or more stores left.
2947
Hence, we can create a burst memory operation with one or two stores.
2948
 
2949
As one final example, we might also use the DMA for this operation, as with
2950
Tbl.~\ref{tbl:memset-dma}.
2951
\begin{table}\begin{center}
2952
\begin{tabbing}
2953
{\tt \#define DMA\_CONSTSRC 0x20000000} {\em // Don't increment the source address}
2954
\\
2955
{\tt void *} \= {\tt memset\_dma(void *s, int c, size\_t len) \{} \\
2956
        \> {\em // As before, this assumes we have access to the DMA, and that}\\
2957
        \> {\em // we are running in system high mode ...}\\
2958
        \> {\tt zip->dma.len = len;} \= {\em // Set up the DMA }\\
2959
        \> {\tt zip->dma.rd  = \&c;}\\
2960
        \> {\tt zip->dma.wr  = s;}\\
2961
        \> {\em // Command the DMA to start copying, but not to increment the} \\
2962
        \> {\em // source address during the copy.} \\
2963
        \> {\tt zip->dma.ctrl= DMACOPY|DMA\_CONSTSRC;} \\
2964
        \> {\em // Note that we take two clocks to set up our PIC.  This is }\\
2965
        \> {\em // required because the PIC takes at least a clock cycle to clear.} \\
2966
        \> {\tt zip->pic = DISABLEALL|SYSINT\_DMA;} \\
2967
        \> {\em // Now that our PIC is actually clear, with no more DMA }\\
2968
        \> {\em // interrupt within it, now we enable the DMA interrupt, and}\\
2969
        \> {\em // only the DMA interrupt.}\\
2970
        \> {\tt zip->pic = EINT(SYSINT\_DMA);}\\
2971
        \> {\em // And wait for the DMA to complete.} \\
2972
        \> {\tt zip\_wait();}\\
2973
{\tt \}}
2974
\end{tabbing}
2975
\caption{Example Memset code, only this time with the DMA}\label{tbl:memset-dma}
2976
\end{center}\end{table}
2977
This is almost identical to the {\tt memcpy} function above that used the
2978
DMA, save that the pointer for the value read is given to be the address
2979
of c, and that the DMA is instructed not to increment its source pointer.
2980
The DMA will still do {\tt len} reads, so the asymptotic performance will never
2981
be less than $2N$ clocks per transfer.
2982
 
2983
\section{String Operations}
2984
Perhaps one of the immediate questions most folks will have is, how does one
2985
handle string operations on a CPU that only handles 32--bit numbers?  Here we
2986
offer a couple of possibilities.
2987
 
2988
The first possibility is the easy and natural choice: just define characters
2989
to be 32--bit numbers and ignore the upper 24 bits.  This is the choice made
2990
by the compiler.  Hence, if you compile a simple string compare function,
2991
such as Tbl.~\ref{tbl:str-cmp},
2992
\begin{table}\begin{center}
2993
\begin{tabbing}
2994
\hbox to 0.25in{\tt int} \= {\tt strcmp(const char *s1, const char *s2) \{} \\
2995
        \> {\tt while(*s1 == *s2)} \\
2996
        \> \hbox to 0.25in{} {\tt s1++, s2++;} \\
2997
        \> {\tt return *s2 - *s1;} \\
2998
{\tt \}}
2999
\end{tabbing}
3000
\caption{Example string compare function}\label{tbl:str-cmp}
3001
\end{center}\end{table}
3002
string length function, such as Tbl.~\ref{tbl:str-len},
3003
\begin{table}\begin{center}
3004
\begin{tabbing}
3005
{\tt unsigned} \= {\tt strlen(const char *s) \{} \\
3006
        \> {\tt int ln = 0;} \\
3007
        \> {\tt while(*s++ != 0)} \\
3008
        \> \hbox to 0.25in{} {\tt ln++;} \\
3009
        \> {\tt return ln;} \\
3010
{\tt \}}
3011
\end{tabbing}
3012
\caption{Example string compare function}\label{tbl:str-len}
3013
\end{center}\end{table}
3014
or string copy function, such as Tbl.~\ref{tbl:str-cpy},
3015
\begin{table}\begin{center}
3016
\begin{tabbing}
3017
{\tt char *} \= {\tt strcpy(char *dest, const char *src) \{} \\
3018
        \> {\tt char *d = dest;} {\em // Make a working copy of the dest ptr}\\
3019
        \> {\tt do \{} \\
3020
        \> \hbox to 0.25in{} {\tt *d++ = *src;} \\
3021
        \> {\tt \} while(*src++);} \\
3022
        \> {\tt return dest;} \\
3023
{\tt \}}
3024
\end{tabbing}
3025
\caption{Example string copy function}\label{tbl:str-cpy}
3026
\end{center}\end{table}
3027
this is what you will get.
3028
 
3029
A little work with these functions, and you should be able to optimize them
3030
in a fashion similar to that with memcpy.  This doesn't solve the fundamental
3031
problem, though, of why am I wasting 32--bits for 8--bit quantities?
3032
 
3033
An alternative would be to use a packed string structure.  To pack a string,
3034
one might do something like Tbl.~\ref{tbl:pstr}.
3035
\begin{table}\begin{center}
3036
\begin{tabbing}
3037
{\tt void} \= {\tt packstr(char *s) \{} \\
3038
        \> {\tt char *d = s;} \= {\em // Pack our string in place} \\
3039
        \> {\tt int w;}\>{\em // A holding word to pack things into} \\
3040
        \> {\tt int k=0;}\>{\em // A count to know when to move to the next word} \\
3041
        \> {\tt while(*s) \{} \\
3042
        \> \hbox to 0.25in{}\={\tt w = (w<<8)|(*s \& 0x0ff);} \\
3043
        \>\> {\em // After four of these octets, write the result out} \\
3044
        \> \> {\tt if (((++k)\&3)==0) *d++ = w;} \\
3045
        \> {\tt \}} \\
3046
        \> {\em // But what happens if we never got to the fourth octet}\\
3047
        \> {\em // in our last word?  We need to clean that up here.}\\
3048
\\
3049
        \> {\em // First, shift the partial value all the way up}\\
3050
        \> {\tt w = (w<<(32-((k\&3)<<3));} {\em // Shift up the last word}\\
3051
        \> {\tt *d++ = w;} {\em // Store any remaining partial value }\\
3052
        \> {\em // If we want to make sure our strings end in zero, we need}\\
3053
        \> {\em // one more step:}\\
3054
        \> {\tt *d = 0;} {\em // Make sure string ends in a zero.}\\
3055
{\tt \}}
3056
\end{tabbing}
3057
\caption{String packing function}\label{tbl:pstr}
3058
\end{center}\end{table}
3059
Notice that our packed string places its first byte in the high order octet
3060
of our first word, that any excess octets in the last word are zeros,
3061
and that there remains a zero word following our string.  With this packed
3062
string approach, compares and copies can proceed four times faster.  As an
3063
example, Tbl.~\ref{tbl:pstr-cmp}
3064
\begin{table}\begin{center}
3065
\begin{tabbing}
3066
\hbox to 0.25in{\tt int} \= {\tt pstrcmp(const char *s1, const char *s2) \{} \\
3067
        \> {\tt while(*s1 == *s2)} \\
3068
        \> \hbox to 0.25in{} {\tt s1++, s2++;} \\
3069
        \> {\tt return *s2 - *s1;} \\
3070
{\tt \}}
3071
\end{tabbing}
3072
\caption{Packed string compare function}\label{tbl:pstr-cmp}
3073
\end{center}\end{table}
3074
presents a string compare function for a packed string.  You'll notice that
3075
it doesn't look all that different from a string compare for a non-packed
3076
string.  This is on purpose.  Another example might be a string copy, which
3077
again, wouldn't look all that different.  Getting the number of used 8--bit
3078
octets within a string is a touch more difficult.  In that case, one might
3079
try something like Tbl.~\ref{tbl:pstr-len}.
3080
\begin{table}\begin{center}
3081
\begin{tabbing}
3082
{\tt unsigned} \= {\tt pstrlen(const char *s) \{} \\
3083
        \> {\tt int ln = 0;} \\
3084
        \> {\tt while(*s++ != 0)} \\
3085
        \> \hbox to 0.25in{}\={\tt ln+=4;} \\
3086
        \> {\tt if (ln) \{}\\
3087
        \>\>    {\em // Touch up the length in case of an incomplete last word} \\
3088
        \>\>    {\tt int lastval = s[-1];}\\
3089
\\
3090
        \>\>    {\tt if ((lastval \& 0x0ff)==0) ln--;}\\
3091
        \>\>    {\tt if ((lastval \& 0x0ffff)==0) ln--;}\\
3092
        \>\>    {\tt if ((lastval \& 0x0ffffff)==0) ln--;}\\
3093
        \> {\tt \}} \\
3094
        \> {\tt return ln;} \\
3095
{\tt \}}
3096
\end{tabbing}
3097
\caption{Packed string subcharacter length function}\label{tbl:pstr-len}
3098
\end{center}\end{table}
3099
 
3100
\section{Context Switch}
3101
 
3102 36 dgisselq
Fundamental to any multiprocessing system is the ability to switch from one
3103 199 dgisselq
task to the next.  In the ZipSystem, this is accomplished in one of a couple of
3104
ways.  The first step is that an interrupt, trap, or exception takes place.
3105
This will pull the CPU out of user mode and into supervisor mode.  At this
3106
point, the CPU needs to execute the following tasks:
3107 36 dgisselq
\begin{enumerate}
3108 199 dgisselq
\item Check for the reason, why did we return from user mode?  Did the user
3109
        execute a trap instruction, or did some other user exception such as a
3110
        break, bus error, division by zero error, or floating point exception
3111
        occur.  That is, if the user process needs attending then we may not
3112
        wish to adjust the context, check interrupts, or call the scheduler.
3113 69 dgisselq
        Tbl.~\ref{tbl:trap-check}
3114 36 dgisselq
\begin{table}\begin{center}
3115 199 dgisselq
\begin{tabbing}
3116
{\tt while(true) \{} \\
3117
        \hbox to 0.25in{}\={\em // The instruction before the context switch processing must} \\
3118
\>      {\em // be the RTU instruction that enacted user mode in the first} \\
3119
\>      {\em // place.  We show it here just for reference.} \\
3120
\>      {\tt zip\_rtu();} \\
3121
\\
3122
\>      {\tt if (zip\_ucc() \& (CC\_FAULT)) \{} \\
3123
\>      \hbox to 0.25in{}\={\em // The user program has experienced an unrecoverable fault and must die.}\\
3124
\>\>    {\em // Do something here to kill the task, recover any resources} \\
3125
\>\>            {\em // it was using, and report/record the problem.}\\
3126
\>\>            \ldots \\
3127
\>      {\tt \} else if (zip\_ucc() \& (CC\_TRAPBIT)) \{} \\
3128
\>\>            {\em // Handle any user request} \\
3129
\>\>            {\tt zip\_restore\_context(userregs);} \\
3130
\>\>            {\em // If the request ID is in uR1, that is now userregs[1]}\\
3131
\>\>            {\tt switch(userregs[1]) \{} \\
3132
\>\>            {\tt case $x$:} {\em // Perform some user requested function} \\
3133
\>\>            \hbox to 0.25in{}\= {\tt break;}\\
3134
\>\>            {\tt \}} \\
3135
\>      {\tt \}}\\
3136
\\
3137
{\tt \}}
3138
\end{tabbing}
3139 69 dgisselq
\caption{Checking for whether the user task needs our attention}\label{tbl:trap-check}
3140 36 dgisselq
\end{center}\end{table}
3141
        shows the rudiments of this code, while showing nothing of how the
3142
        actual trap would be implemented.
3143
 
3144
You may also wish to note that the instruction before the first instruction
3145
in our context swap {\em must be} a return to userspace instruction.
3146
Remember, the supervisor process is re--entered where it left off.  This is
3147
different from many other processors that enter interrupt mode at some vector
3148
or other.  In this case, we always enter supervisor mode right where we last
3149 199 dgisselq
left.
3150 36 dgisselq
 
3151 199 dgisselq
\item Capture user accounting counters.  If the operating system is keeping
3152
        track of system usage via the accounting counters, those counters need
3153
        to be copied and accumulated into some master counter at this point.
3154 36 dgisselq
 
3155 199 dgisselq
\item Preserve the old context.  This involves recording all of the user
3156
        registers to some supervisor memory structure, such as is shown in
3157
        Tbl.~\ref{tbl:context-out}.
3158 36 dgisselq
\begin{table}\begin{center}
3159 199 dgisselq
\begin{tabbing}
3160
{\tt save\_context:} \\
3161
\hbox to 0.25in{}\={\tt SUB 1,SP}\hbox to 0.5in{}\= {\em ; Function prologue: create a stack}\\
3162
\>        {\tt STO R5,(SP)}     \> {\em ; frame and save R5.  (R1-R4 are assumed}\\
3163
\>        {\tt MOV uR0,R2}      \> {\em ; to be used and in need of saving.  Then}\\
3164
\>        {\tt MOV uR1,R3}      \> {\em ; copy the user registers, four at a time to }\\
3165
\>        {\tt MOV uR2,R4}      \> {\em ; supervisor registers, where they can be}\\
3166
\>        {\tt MOV uR3,R5}      \> {\em ; stored, while exploiting memory pipelining}\\
3167
\>        {\tt STO R2,(R1)}     \>{\em ; Exploit memory pipelining: }\\
3168
\>        {\tt STO R3,1(R1)}    \>{\em ; All instructions write to same base memory}\\
3169
\>        {\tt STO R4,2(R1)}    \>{\em ; All offsets increment by one }\\
3170
\>        {\tt STO R5,3(R1)} \\
3171
\>      \ldots {\em ; Need to repeat for all user registers} \\
3172 39 dgisselq
\iffalse
3173
&        {\tt MOV uR5,R0} \\
3174
&        {\tt MOV uR6,R1} \\
3175
&        {\tt MOV uR7,R2} \\
3176
&        {\tt MOV uR8,R3} \\
3177
&        {\tt MOV uR9,R4} \\
3178 69 dgisselq
&        {\tt STO R0,5(R5) }\\
3179
&        {\tt STO R1,6(R5) }\\
3180
&        {\tt STO R2,7(R5) }\\
3181
&        {\tt STO R3,8(R5) }\\
3182
&        {\tt STO R4,9(R5)} \\
3183 39 dgisselq
\fi
3184 199 dgisselq
\>        {\tt MOV uR12,R2}     \> {\em ; Finish copying ... } \\
3185
\>        {\tt MOV uSP,R3} \\
3186
\>        {\tt MOV uCC,R4} \\
3187
\>        {\tt MOV uPC,R5} \\
3188
\>        {\tt STO R2,12(R1)}   \> {\em ; and saving the last registers.}\\
3189
\>        {\tt STO R3,13(R1)}   \> {\em ; Note that even the special user registers }\\
3190
\>        {\tt STO R4,14(R1)}   \> {\em ; are saved just like any others. }\\
3191
\>        {\tt STO R5,15(R1)} \\
3192
\>        {\tt LOD (SP),R5}     \> {\em ; Restore our one saved register}\\
3193
\>        {\tt ADD 1,SP}                \> {\em ; our stack frame,} \\
3194
\>        {\tt JMP R0}          \> {\em ; and return }\\
3195
\end{tabbing}
3196 36 dgisselq
\caption{Example Storing User Task Context}\label{tbl:context-out}
3197
\end{center}\end{table}
3198 199 dgisselq
Since this task is so fundamental, the ZipCPU compiler back end provides
3199
the {\tt zip\_save\_context(int *)} function.
3200 36 dgisselq
 
3201
\item Reset the watchdog timer.  If you are using the watchdog timer, it should
3202
        be reset on a context swap, to know that things are still working.
3203
 
3204 199 dgisselq
\item Interrupt handling.  How you handle interrupts on the ZipCPU are up to
3205
        you.  You can activate a sleeping task if you like, or for smaller
3206
        faster interrupt routines, such as copying a character to or from a
3207
        serial port or providing a sample to an audio port, you might choose
3208
        to do the task within the kernel main loop.  The difference may
3209
        depend upon how you have your hardware set up, and how fast the
3210
        kernel main loop is.
3211 36 dgisselq
 
3212
\item Calling the scheduler.  This needs to be done to pick the next task
3213
        to switch to.  It may be an interrupt handler, or it may  be a normal
3214
        user task.  From a priority standpoint, it would make sense that the
3215
        interrupt handlers all have a higher priority than the user tasks,
3216
        and that once they have been called the user tasks may then be called
3217
        again.  If no task is ready to run, run the idle task to wait for an
3218
        interrupt.
3219
 
3220
        This suggests a minimum of four task priorities:
3221
        \begin{enumerate}
3222
        \item Interrupt handlers, executed with their interrupts disabled
3223
        \item Device drivers, executed with interrupts re-enabled
3224
        \item User tasks
3225
        \item The idle task, executed when nothing else is able to execute
3226
        \end{enumerate}
3227
 
3228 199 dgisselq
%       For our purposes here, we'll just assume that a pointer to the current
3229
%       task is maintained in {\tt R12}, that a {\tt JSR scheduler} is
3230
%       called, and that the next current task is likewise placed into
3231
%       {\tt R12}.
3232 36 dgisselq
 
3233
\item Restore the new tasks context.  Given that the scheduler has returned a
3234 199 dgisselq
        task that can be run at this time, the user registers need to be
3235
        read from the memory at the user context pointer and then placed into
3236
        the user registers.  An example of this is shown in
3237
        Tbl.~\ref{tbl:context-in},
3238 36 dgisselq
\begin{table}\begin{center}
3239 199 dgisselq
\begin{tabbing}
3240
{\tt restore\_context:} \\
3241
\hbox to 0.25in{}\= {\tt SUB 1,SP}\hbox to 0.4in{}\={\em ; Set up a stack frame} \\
3242
\>      {\tt STO R5,(SP)} \> {\em ; and store a local register onto it.}\\
3243
\\
3244
\>      {\tt LOD (R1),R2} \> {\em ; By doing four loads at a time, we are }\\
3245
\>      {\tt LOD 1(R1),R3} \> {\em ; making sure we are using our pipelined}\\
3246
\>      {\tt LOD 2(R1),R4} \> {\em ; memory capability. }\\
3247
\>      {\tt LOD 3(R1),R5} \\
3248
\>      {\tt MOV R2,uR1} \> {\em ; Once the registers are loaded, copy them }\\
3249
\>      {\tt MOV R3,uR2} \> {\em ; into the user registers that they need to}\\
3250
\>      {\tt MOV R4,uR3} \> {\em ; be placed within.} \\
3251
\>      {\tt MOV R5,uR4} \\
3252
        \> \ldots {\em ; Need to repeat for all user registers} \\
3253
\>      {\tt LOD 12(R1),R2} \> {\em ; Now for our last four registers ...}\\
3254
\>      {\tt LOD 13(R5),R3} \\
3255
\>      {\tt LOD 14(R5),R4} \\
3256
\>      {\tt LOD 15(R5),R5} \\
3257
\>      {\tt MOV R2,uR12} \> {\em ; These are the special purpose ones, restored }\\
3258
\>      {\tt MOV R3,uSP} \> {\em ; just like any others.}\\
3259
\>      {\tt MOV R4,uCC} \\
3260
\>      {\tt MOV R5,uPC} \\
3261 39 dgisselq
 
3262 199 dgisselq
\>      {\tt LOD (SP),R5} \> {\em ; Restore our saved register, } \\
3263
\>      {\tt ADD 1,SP}  \> {\em ; and the stack frame, }\\
3264
\>      {\tt JMP R0}    \> {\em ; and return to where we were called from.}\\
3265
\end{tabbing}
3266 36 dgisselq
\caption{Example Restoring User Task Context}\label{tbl:context-in}
3267
\end{center}\end{table}
3268 199 dgisselq
        Because this is such an important task, the ZipCPU GCC provides a
3269
        built--in function, {\tt zip\_restore\_context(int *)}, which can be
3270
        used for this task.
3271 36 dgisselq
 
3272
\item Clear the userspace accounting registers.  In order to keep track of
3273
        per process system usage, these registers need to be cleared before
3274
        reactivating the userspace process.  That way, upon the next
3275
        interrupt, we'll know how many clocks the userspace program has
3276
        encountered, and how many instructions it was able to issue in
3277
        those many clocks.
3278
 
3279 199 dgisselq
\item Return back to the top of our loop in order to execute {\tt zip\_rtu()}
3280
        again.
3281 36 dgisselq
\end{enumerate}
3282
 
3283 199 dgisselq
 
3284 21 dgisselq
\chapter{Registers}\label{chap:regs}
3285 199 dgisselq
This chapter covers the definitions and locations of the various registers
3286
associated with both the ZipSystem, and the ZipCPU contained within it.
3287
These registers fall into two separate categories: the registers belonging
3288
to the ZipSystem, and then the two debug port registers belonging to the CPU
3289
itself.  In this chapter, we'll discuss the ZipSystem peripheral registers
3290
first, followed by the two ZipCPU registers.
3291 21 dgisselq
 
3292 199 dgisselq
 
3293
\section{ZipSystem Peripheral Registers}
3294
The ZipSystem maintains currently maintains 20 register locations, as shown
3295
in Tbl.~\ref{tbl:zpregs}.
3296 24 dgisselq
\begin{table}[htbp]
3297
\begin{center}\begin{reglist}
3298 32 dgisselq
PIC   & \scalebox{0.8}{\tt 0xc0000000} & 32 & R/W & Primary Interrupt Controller \\\hline
3299 199 dgisselq
WDT & \scalebox{0.8}{\tt 0xc0000001} & 32 & R/W & Watchdog Timer \\\hline
3300
WBU&\scalebox{0.8}{\tt 0xc0000002} & 32 & R & Address of last bus timeout error\\\hline
3301 32 dgisselq
CTRIC & \scalebox{0.8}{\tt 0xc0000003} & 32 & R/W & Secondary Interrupt Controller \\\hline
3302
TMRA  & \scalebox{0.8}{\tt 0xc0000004} & 32 & R/W & Timer A\\\hline
3303
TMRB  & \scalebox{0.8}{\tt 0xc0000005} & 32 & R/W & Timer B\\\hline
3304
TMRC  & \scalebox{0.8}{\tt 0xc0000006} & 32 & R/W & Timer C\\\hline
3305
JIFF  & \scalebox{0.8}{\tt 0xc0000007} & 32 & R/W & Jiffies \\\hline
3306
MTASK  & \scalebox{0.8}{\tt 0xc0000008} & 32 & R/W & Master Task Clock Counter \\\hline
3307
MMSTL  & \scalebox{0.8}{\tt 0xc0000009} & 32 & R/W & Master Stall Counter \\\hline
3308
MPSTL  & \scalebox{0.8}{\tt 0xc000000a} & 32 & R/W & Master Pre--Fetch Stall Counter \\\hline
3309
MICNT  & \scalebox{0.8}{\tt 0xc000000b} & 32 & R/W & Master Instruction Counter\\\hline
3310
UTASK  & \scalebox{0.8}{\tt 0xc000000c} & 32 & R/W & User Task Clock Counter \\\hline
3311
UMSTL  & \scalebox{0.8}{\tt 0xc000000d} & 32 & R/W & User Stall Counter \\\hline
3312
UPSTL  & \scalebox{0.8}{\tt 0xc000000e} & 32 & R/W & User Pre--Fetch Stall Counter \\\hline
3313
UICNT  & \scalebox{0.8}{\tt 0xc000000f} & 32 & R/W & User Instruction Counter\\\hline
3314 36 dgisselq
DMACTRL  & \scalebox{0.8}{\tt 0xc0000010} & 32 & R/W & DMA Control Register\\\hline
3315
DMALEN  & \scalebox{0.8}{\tt 0xc0000011} & 32 & R/W & DMA total transfer length\\\hline
3316
DMASRC  & \scalebox{0.8}{\tt 0xc0000012} & 32 & R/W & DMA source address\\\hline
3317
DMADST  & \scalebox{0.8}{\tt 0xc0000013} & 32 & R/W & DMA destination address\\\hline
3318 32 dgisselq
% Cache  & \scalebox{0.8}{\tt 0xc0100000} & & & Base address of the Cache memory\\\hline
3319 24 dgisselq
\end{reglist}
3320 199 dgisselq
\caption{ZipSystem Internal/Peripheral Registers}\label{tbl:zpregs}
3321 24 dgisselq
\end{center}\end{table}
3322 199 dgisselq
These registers are located in the CPU's address space, although in a special
3323
area of that space.  Indeed, the area is so special, that the CPU decodes
3324
the address space location before placing the request onto the bus.  For
3325
this reason, other containers for the CPU, such as the ZipBones which doesn't
3326
have these registers, will still create errors when they are referenced.
3327 24 dgisselq
 
3328 199 dgisselq
Here in this section, we'll walk through the definition of each of these
3329
registers in turn, together with any bit fields that may be associated with
3330
them, and how to set those fields.
3331 24 dgisselq
 
3332 69 dgisselq
\subsection{Interrupt Controller(s)}
3333 199 dgisselq
Any CPU with only a single interrupt line, such as the ZipCPU, really needs an
3334
interrupt controller to give it access to more than the single interrupt.  The
3335
ZipCPU is no different.  When the ZipCPU is built as part of the ZipSystem,
3336
this interrupt controller comes integrated into the system.
3337
 
3338
Looking into the bits that define this controller, you can see from
3339
Tbl.~\ref{tbl:picbits},
3340 33 dgisselq
\begin{table}\begin{center}
3341
\begin{bitlist}
3342
31 & R/W & Master Interrupt Enable\\\hline
3343 199 dgisselq
30\ldots 16 & R/W & Interrupt Enable lines\\\hline
3344 33 dgisselq
15 & R & Current Master Interrupt State\\\hline
3345 69 dgisselq
15\ldots 0 & R/W & Input Interrupt states, write `1' to clear\\\hline
3346 33 dgisselq
\end{bitlist}
3347
\caption{Interrupt Controller Register Bits}\label{tbl:picbits}
3348
\end{center}\end{table}
3349 199 dgisselq
that the ZipCPU Interrupt controller has four different types of bits.
3350 33 dgisselq
The high order bit, or bit--31, is the master interrupt enable bit.  When this
3351
bit is set, then any time an interrupt occurs the CPU will be interrupted and
3352
will switch to supervisor mode, etc.
3353
 
3354 199 dgisselq
Bits 30~\ldots 16 are interrupt enable bits.  Should the interrupt line ever be
3355
high while enabled, an interrupt will be generated.  Further, interrupts are
3356
level triggered.  Hence, if the interrupt is cleared while the line feeding
3357
the controller remains high, then the interrupt will re--trip.  To set one of
3358
these interrupt enable bits, one needs to write the master interrupt enable
3359
while writing a `1' to this the bit.  To clear, one need only write a `0' to
3360
the master interrupt enable, while leaving this line high.
3361 33 dgisselq
 
3362
Bits 15\ldots 0 are the current state of the interrupt vector.  Interrupt lines
3363 199 dgisselq
trip whenever they are high, and remain tripped until the input is lowered and
3364
the interrupt is acknowledged.  Thus, if the interrupt line is high when the
3365
controller receives a clear request, then the interrupt will not clear.
3366
The incoming line must go low again before the status bit can be cleared.
3367 33 dgisselq
 
3368 199 dgisselq
As an example, consider the following scenario where the ZipCPU supports four
3369 33 dgisselq
interrupts, 3\ldots0.
3370
\begin{enumerate}
3371
\item The Supervisor will first, while in the interrupts disabled mode,
3372
        write a {\tt 32'h800f000f} to the controller.  The supervisor may then
3373
        switch to the user state with interrupts enabled.
3374
\item When an interrupt occurs, the supervisor will switch to the interrupt
3375
        state.  It will then cycle through the interrupt bits to learn which
3376
        interrupt handler to call.
3377
\item If the interrupt handler expects more interrupts, it will clear its
3378
        current interrupt when it is done handling the interrupt in question.
3379 69 dgisselq
        To do this, it will write a `1' to the low order interrupt mask,
3380
        such as writing a {\tt 32'h0000\_0001}.
3381 33 dgisselq
\item If the interrupt handler does not expect any more interrupts, it will
3382
        instead clear the interrupt from the controller by writing a
3383 69 dgisselq
        {\tt 32'h0001\_0001} to the controller.
3384 33 dgisselq
\item Once all interrupts have been handled, the supervisor will write a
3385 69 dgisselq
        {\tt 32'h8000\_0000} to the interrupt register to re-enable interrupt
3386 33 dgisselq
        generation.
3387
\item The supervisor should also check the user trap bit, and possible soft
3388
        interrupt bits here, but this action has nothing to do with the
3389
        interrupt control register.
3390
\item The supervisor will then leave interrupt mode, possibly adjusting
3391
        whichever task is running, by executing a return from interrupt
3392
        command.
3393
\end{enumerate}
3394
 
3395 199 dgisselq
\subsection{Timer Register}\label{sec:reg-timer}
3396 69 dgisselq
 
3397 33 dgisselq
Leaving the interrupt controller, we show the timer registers bit definitions
3398
in Tbl.~\ref{tbl:tmrbits}.
3399
\begin{table}\begin{center}
3400
\begin{bitlist}
3401
31 & R/W & Auto-Reload\\\hline
3402
30\ldots 0 & R/W & Current timer value\\\hline
3403
\end{bitlist}
3404
\caption{Timer Register Bits}\label{tbl:tmrbits}
3405
\end{center}\end{table}
3406
As you may recall, the timer just counts down to zero and then trips an
3407
interrupt.  Writing to the current timer value sets that value, and reading
3408
from it returns that value.  Writing to the current timer value while also
3409
setting the auto--reload bit will send the timer into an auto--reload mode.
3410
In this mode, upon setting its interrupt bit for one cycle, the timer will
3411
also reset itself back to the value of the timer that was written to it when
3412
the auto--reload option was written to it.  To clear and stop the timer,
3413
just simply write a `32'h00' to this register.
3414
 
3415 199 dgisselq
\subsection{Jiffies}\label{sec:reg-jiffies}
3416 69 dgisselq
 
3417 199 dgisselq
The Jiffies register is first and foremost a counter.  It counts up one on
3418
every clock.  Reads from this register, as shown in Tbl.~\ref{tbl:jiffybits},
3419 33 dgisselq
\begin{table}\begin{center}
3420
\begin{bitlist}
3421
31\ldots 0 & R & Current jiffy value\\\hline
3422
31\ldots 0 & W & Value/time of next interrupt\\\hline
3423
\end{bitlist}
3424
\caption{Jiffies Register Bits}\label{tbl:jiffybits}
3425
\end{center}\end{table}
3426 199 dgisselq
always return the time value contained in the register.
3427 33 dgisselq
 
3428 199 dgisselq
The register accepts writes as well.  Writes to the register set the time of
3429
the next Jiffy interrupt.  If the next interrupt is between 0~and $2^{31}$
3430
clocks in the past, the peripheral will immediately create an interrupt.
3431
Otherwise, the register will compare the new value against the currently
3432
stored interrupt value.  The value nearest in time to the current jiffies value
3433
will be kept, and so the jiffies register will trip at that value.  Prior
3434
values are forgotten.
3435
 
3436
When the Jiffy counter value equals the value in its trigger register, then
3437
the jiffies peripheral will trigger an interrupt.  At this point, the internal
3438
register is cleared.  It will create no more interrupts unless a new value
3439
is written to it.
3440
 
3441 69 dgisselq
\subsection{Performance Counters}
3442
 
3443 199 dgisselq
The ZipCPU also supports several counter peripherals, mostly for the purpose of
3444
process accounting.  These counters each contain a single register, as shown
3445
in Tbl.~\ref{tbl:ctrbits}.
3446 33 dgisselq
\begin{table}\begin{center}
3447
\begin{bitlist}
3448
31\ldots 0 & R/W & Current counter value\\\hline
3449
\end{bitlist}
3450
\caption{Counter Register Bits}\label{tbl:ctrbits}
3451
\end{center}\end{table}
3452
Writes to this register set the new counter value.  Reads read the current
3453
counter value.
3454
 
3455 199 dgisselq
These counters can be configured to count upwards upon any event.  Using this
3456
capability, eight counters have been assigned the task of performance counting.
3457 33 dgisselq
Two sets of four registers are available for keeping track of performance.
3458 199 dgisselq
The first set tracks master performance, including both supervisor as well as
3459
user CPU statistics.  The second set tracks user statistics only, and will not
3460
count in supervisor mode.
3461 33 dgisselq
 
3462 199 dgisselq
Of the four registers in each set, the first is a task counter that just counts
3463
clock ticks.  The second counter is a prefetch stall counter, then an master
3464
stall counter.  These allow the CPU to be evaluated as to how efficient it is.
3465
The fourth and final counter in each set is an instruction counter, which
3466
counts how many instructions the CPU has issued.
3467
 
3468 33 dgisselq
It is envisioned that these counters will be used as follows: First, every time
3469
a master counter rolls over, the supervisor (Operating System) will record
3470
the fact.  Second, whenever activating a user task, the Operating System will
3471
set the four user counters to zero.  When the user task has completed, the
3472
Operating System will read the timers back off, to determine how much of the
3473 69 dgisselq
CPU the process had consumed.  To keep this accurate, the user counters will
3474
only increment when the GIE bit is set to indicate that the processor is
3475
in user mode.
3476 33 dgisselq
 
3477 199 dgisselq
\subsection{DMA Controller}\label{sec:reg-dmac}
3478 69 dgisselq
 
3479 36 dgisselq
The final peripheral to discuss is the DMA controller.  This controller
3480
has four registers.  Of these four, the length, source and destination address
3481
registers should need no further explanation.  They are full 32--bit registers
3482
specifying the entire transfer length, the starting address to read from, and
3483
the starting address to write to.  The registers can be written to when the
3484
DMA is idle, and read at any time.  The control register, however, will need
3485
some more explanation.
3486
 
3487
The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.
3488
\begin{table}\begin{center}
3489
\begin{bitlist}
3490
31 & R & DMA Active\\\hline
3491 199 dgisselq
30 & R & Wishbone error, transaction aborted.  This bit is cleared the next
3492
        time this register is written to.\\\hline
3493
29 & R/W & Set to `1' to prevent the controller from incrementing the source
3494
        address, `0' for normal memory copy. \\\hline
3495 69 dgisselq
28 & R/W & Set to `1' to prevent the controller from incrementing the
3496
        destination address, `0' for normal memory copy. \\\hline
3497 36 dgisselq
27 \ldots 16 & W & The DMA Key.  Write a 12'hfed to these bits to start the
3498
        activate any DMA transfer.  \\\hline
3499 69 dgisselq
27 & R & Always reads `0', to force the deliberate writing of the key. \\\hline
3500 36 dgisselq
26 \ldots 16 & R & Indicates the number of items in the transfer buffer that
3501
        have yet to be written. \\\hline
3502 69 dgisselq
15 & R/W & Set to `1' to trigger on an interrupt, or `0' to start immediately
3503 36 dgisselq
        upon receiving a valid key.\\\hline
3504
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
3505 199 dgisselq
9\ldots 0 & R/W & Intermediate transfer length.  Thus, to transfer
3506
        one item at a time set this value to 1. To transfer the maximum number,
3507
        1024, at a time set it to 0.\\\hline
3508 36 dgisselq
\end{bitlist}
3509
\caption{DMA Control Register Bits}\label{tbl:dmacbits}
3510
\end{center}\end{table}
3511
This control register has been designed so that the common case of memory
3512
access need only set the key and the transfer length.  Hence, writing a
3513 199 dgisselq
\hbox{32'h0fed0000} to the control register will start any memory transfer.
3514 36 dgisselq
On the other hand, if you wished to read from a serial port (constant address)
3515
and put the result into a buffer every time a word was available, you
3516 199 dgisselq
might wish to write \hbox{32'h2fed8001}--this assumes, of course, that you
3517 36 dgisselq
have a serial port wired to the zero bit of this interrupt control.  (The
3518
DMA controller does not use the interrupt controller, and cannot clear
3519
interrupts.)  As a third example, if you wished to write to an external
3520
FIFO anytime it was less than half full (had fewer than 512 items), and
3521 167 dgisselq
interrupt line 3 indicated this condition, you might wish to issue a
3522 36 dgisselq
\hbox{32'h1fed8dff} to this port.
3523
 
3524 199 dgisselq
\section{Debug Port Registers}\label{sec:reg-debug}
3525
Accessing the ZipSystem via the debug port isn't as straight forward as
3526 33 dgisselq
accessing the system via the wishbone bus.  The debug port itself has been
3527
reduced to two addresses, as outlined earlier in Tbl.~\ref{tbl:dbgregs}.
3528 199 dgisselq
\begin{table}[htbp]
3529
\begin{center}\begin{reglist}
3530
ZIPCTRL & 0 & 32 & R/W & Debug Control Register \\\hline
3531
ZIPDATA & 1 & 32 & R/W & Debug Data Register \\\hline
3532
\end{reglist}
3533
\caption{ZipSystem Debug Registers}\label{tbl:dbgregs}
3534
\end{center}\end{table}
3535
 
3536
Access to the ZipSystem begins with the Debug Control register, shown in
3537 33 dgisselq
Tbl.~\ref{tbl:dbgctrl}.
3538
\begin{table}\begin{center}
3539
\begin{bitlist}
3540 69 dgisselq
31\ldots 14 & R & External interrupt state.  Bit 14 is valid for one
3541
        interrupt only, bit 15 for two, etc.\\\hline
3542 33 dgisselq
13 & R & CPU GIE setting\\\hline
3543
12 & R & CPU is sleeping\\\hline
3544
11 & W & Command clear PF cache\\\hline
3545 69 dgisselq
10 & R/W & Command HALT, Set to `1' to halt the CPU\\\hline
3546
9 & R & Stall Status, `1' if CPU is busy (i.e., not halted yet)\\\hline
3547
8 & R/W & Step Command, set to `1' to step the CPU, also sets the halt bit\\\hline
3548
7 & R & Interrupt Request Pending\\\hline
3549 33 dgisselq
6 & R/W & Command RESET \\\hline
3550
5\ldots 0 & R/W & Debug Register Address \\\hline
3551
\end{bitlist}
3552
\caption{Debug Control Register Bits}\label{tbl:dbgctrl}
3553
\end{center}\end{table}
3554
 
3555
The first step in debugging access is to determine whether or not the CPU
3556 69 dgisselq
is halted, and to halt it if not.  To do this, first write a `1' to the
3557 33 dgisselq
Command HALT bit.  This will halt the CPU and place it into debug mode.
3558
Once the CPU is halted, the stall status bit will drop to zero.  Thus,
3559
if bit 10 is high and bit 9 low, the debug port is open to examine the
3560
internal state of the CPU.
3561
 
3562
At this point, the external debugger may examine internal state information
3563
from within the CPU.  To do this, first write again to the command register
3564
a value (with command halt still high) containing the address of an internal
3565
register of interest in the bottom 6~bits.  Internal registers that may be
3566
accessed this way are listed in Tbl.~\ref{tbl:dbgaddrs}.
3567
\begin{table}\begin{center}
3568
\begin{reglist}
3569
sR0 & 0 & 32 & R/W & Supervisor Register R0 \\\hline
3570
sR1 & 0 & 32 & R/W & Supervisor Register R1 \\\hline
3571
sSP & 13 & 32 & R/W & Supervisor Stack Pointer\\\hline
3572
sCC & 14 & 32 & R/W & Supervisor Condition Code Register \\\hline
3573
sPC & 15 & 32 & R/W & Supervisor Program Counter\\\hline
3574
uR0 & 16 & 32 & R/W & User Register R0 \\\hline
3575
uR1 & 17 & 32 & R/W & User Register R1 \\\hline
3576
uSP & 29 & 32 & R/W & User Stack Pointer\\\hline
3577
uCC & 30 & 32 & R/W & User Condition Code Register \\\hline
3578
uPC & 31 & 32 & R/W & User Program Counter\\\hline
3579
PIC & 32 & 32 & R/W & Primary Interrupt Controller \\\hline
3580
WDT & 33 & 32 & R/W & Watchdog Timer\\\hline
3581 199 dgisselq
WBUS & 34 & 32 & R & Last Bus Error\\\hline
3582 33 dgisselq
CTRIC & 35 & 32 & R/W & Secondary Interrupt Controller\\\hline
3583
TMRA & 36 & 32 & R/W & Timer A\\\hline
3584
TMRB & 37 & 32 & R/W & Timer B\\\hline
3585
TMRC & 38 & 32 & R/W & Timer C\\\hline
3586
JIFF & 39 & 32 & R/W & Jiffies peripheral\\\hline
3587
MTASK & 40 & 32 & R/W & Master task clock counter\\\hline
3588
MMSTL & 41 & 32 & R/W & Master memory stall counter\\\hline
3589
MPSTL & 42 & 32 & R/W & Master Pre-Fetch Stall counter\\\hline
3590
MICNT & 43 & 32 & R/W & Master instruction counter\\\hline
3591
UTASK & 44 & 32 & R/W & User task clock counter\\\hline
3592
UMSTL & 45 & 32 & R/W & User memory stall counter\\\hline
3593
UPSTL & 46 & 32 & R/W & User Pre-Fetch Stall counter\\\hline
3594
UICNT & 47 & 32 & R/W & User instruction counter\\\hline
3595 39 dgisselq
DMACMD & 48 & 32 & R/W & DMA command and status register\\\hline
3596
DMALEN & 49 & 32 & R/W & DMA transfer length\\\hline
3597
DMARD & 50 & 32 & R/W & DMA read address\\\hline
3598
DMAWR & 51 & 32 & R/W & DMA write address\\\hline
3599 33 dgisselq
\end{reglist}
3600
\caption{Debug Register Addresses}\label{tbl:dbgaddrs}
3601
\end{center}\end{table}
3602
Primarily, these ``registers'' include access to the entire CPU register
3603 36 dgisselq
set, as well as the internal peripherals.  To read one of these registers
3604 33 dgisselq
once the address is set, simply issue a read from the data port.  To write
3605
one of these registers or peripheral ports, simply write to the data port
3606
after setting the proper address.
3607
 
3608
In this manner, all of the CPU's internal state may be read and adjusted.
3609
 
3610
As an example of how to use this, consider what would happen in the case
3611
of an external break point.  If and when the CPU hits a break point that
3612
causes it to halt, the Command HALT bit will activate on its own, the CPU
3613
will then raise an external interrupt line and wait for a debugger to examine
3614
its state.  After examining the state, the debugger will need to remove
3615
the breakpoint by writing a different instruction into memory and by writing
3616
to the command register while holding the clear cache, command halt, and
3617
step CPU bits high, (32'hd00).  The debugger may then replace the breakpoint
3618
now that the CPU has gone beyond it, and clear the cache again (32'h500).
3619
 
3620
To leave this debug mode, simply write a `32'h0' value to the command register.
3621
 
3622
\chapter{Wishbone Datasheets}\label{chap:wishbone}
3623 199 dgisselq
The ZipSystem supports two wishbone ports, a slave debug port and a master
3624 21 dgisselq
port for the system itself.  These are shown in Tbl.~\ref{tbl:wishbone-slave}
3625
\begin{table}[htbp]
3626
\begin{center}
3627
\begin{wishboneds}
3628
Revision level of wishbone & WB B4 spec \\\hline
3629
Type of interface & Slave, Read/Write, single words only \\\hline
3630 24 dgisselq
Address Width & 1--bit \\\hline
3631 21 dgisselq
Port size & 32--bit \\\hline
3632
Port granularity & 32--bit \\\hline
3633
Maximum Operand Size & 32--bit \\\hline
3634
Data transfer ordering & (Irrelevant) \\\hline
3635 69 dgisselq
Clock constraints & Works at 100~MHz on a Basys--3 board, and 80~MHz on a
3636
                XuLA2--LX25\\\hline
3637 21 dgisselq
Signal Names & \begin{tabular}{ll}
3638
                Signal Name & Wishbone Equivalent \\\hline
3639
                {\tt i\_clk} & {\tt CLK\_I} \\
3640
                {\tt i\_dbg\_cyc} & {\tt CYC\_I} \\
3641 199 dgisselq
                {\tt i\_dbg\_stb} & {\tt (CYC\_I)\&(STB\_I)} \\
3642 21 dgisselq
                {\tt i\_dbg\_we} & {\tt WE\_I} \\
3643
                {\tt i\_dbg\_addr} & {\tt ADR\_I} \\
3644
                {\tt i\_dbg\_data} & {\tt DAT\_I} \\
3645
                {\tt o\_dbg\_ack} & {\tt ACK\_O} \\
3646
                {\tt o\_dbg\_stall} & {\tt STALL\_O} \\
3647
                {\tt o\_dbg\_data} & {\tt DAT\_O}
3648
                \end{tabular}\\\hline
3649
\end{wishboneds}
3650 22 dgisselq
\caption{Wishbone Datasheet for the Debug Interface}\label{tbl:wishbone-slave}
3651 21 dgisselq
\end{center}\end{table}
3652
and Tbl.~\ref{tbl:wishbone-master} respectively.
3653
\begin{table}[htbp]
3654
\begin{center}
3655
\begin{wishboneds}
3656
Revision level of wishbone & WB B4 spec \\\hline
3657 24 dgisselq
Type of interface & Master, Read/Write, single cycle or pipelined\\\hline
3658 199 dgisselq
Address Width & (ZipSystem parameter, can be up to 32--bit bits) \\\hline
3659 21 dgisselq
Port size & 32--bit \\\hline
3660
Port granularity & 32--bit \\\hline
3661
Maximum Operand Size & 32--bit \\\hline
3662
Data transfer ordering & (Irrelevant) \\\hline
3663 69 dgisselq
Clock constraints & Works at 100~MHz on a Basys--3 board, and 80~MHz on a
3664
                XuLA2--LX25\\\hline
3665 21 dgisselq
Signal Names & \begin{tabular}{ll}
3666
                Signal Name & Wishbone Equivalent \\\hline
3667
                {\tt i\_clk} & {\tt CLK\_O} \\
3668
                {\tt o\_wb\_cyc} & {\tt CYC\_O} \\
3669 199 dgisselq
                {\tt o\_wb\_stb} & {\tt (CYC\_O)\&(STB\_O)} \\
3670 21 dgisselq
                {\tt o\_wb\_we} & {\tt WE\_O} \\
3671
                {\tt o\_wb\_addr} & {\tt ADR\_O} \\
3672
                {\tt o\_wb\_data} & {\tt DAT\_O} \\
3673
                {\tt i\_wb\_ack} & {\tt ACK\_I} \\
3674
                {\tt i\_wb\_stall} & {\tt STALL\_I} \\
3675 69 dgisselq
                {\tt i\_wb\_data} & {\tt DAT\_I} \\
3676
                {\tt i\_wb\_err} & {\tt ERR\_I}
3677 21 dgisselq
                \end{tabular}\\\hline
3678
\end{wishboneds}
3679 22 dgisselq
\caption{Wishbone Datasheet for the CPU as Master}\label{tbl:wishbone-master}
3680 21 dgisselq
\end{center}\end{table}
3681 199 dgisselq
I do not recommend that you connect these together through the interconnect,
3682
since 1) it doesn't make sense that the CPU should be able to halt itself,
3683
and 2) it helps to be able to reboot the CPU in case something has gone
3684
terribly wrong and the CPU is stalling the entire interconnect.
3685 24 dgisselq
Rather, the debug port of the CPU should be accessible regardless of the state
3686
of the master bus.
3687 21 dgisselq
 
3688 69 dgisselq
You may wish to notice that neither the {\tt LOCK} nor the {\tt RTY} (retry)
3689
wires have been connected to the CPU's master interface.  If necessary, a
3690 199 dgisselq
rudimentary {\tt LOCK} may be created by tying this wire to the {\tt wb\_cyc}
3691 69 dgisselq
line.  As for the {\tt RTY}, all the CPU recognizes at this point are bus
3692
errors---it cannot tell the difference between a temporary and a permanent bus
3693 199 dgisselq
error.  Therefore, one might logically OR the bus error and bus retry flags on
3694
input to the CPU if necessary.
3695 21 dgisselq
 
3696 199 dgisselq
The final simplification made of the standard wishbone bus B4 specification, is
3697
that the strobe lines are assumed to be zero in any slave if {\tt CYC\_I} is
3698
zero, and the master is responsible for ensuring that {\tt STB\_O} is never
3699
true when {\tt CYC\_O} is true in order to make this work.  All of the ZipCPU
3700
and ZipSystem masters and peripherals have been created with this assumption.
3701
Converting peripherals that have made this assumption to work with masters
3702
that don't guarantee this property is as simple as anding the slave's
3703
{\tt CYC\_I} and {\tt STB\_I} lines together.  No change needs to be made to
3704
any ZipCPU master, however, in order to access any peripheral that hasn't been
3705
so simplified.
3706
 
3707 21 dgisselq
\chapter{Clocks}\label{chap:clocks}
3708
 
3709 199 dgisselq
This core has now been tested and proven on the Xilinx Spartan~6 FPGA as well
3710
as the Artix--7 FPGA.
3711 21 dgisselq
\begin{table}[htbp]
3712
\begin{center}
3713
\begin{clocklist}
3714 199 dgisselq
i\_clk & External & 100~MHz & & System clock, Artix--7/35T\\\hline
3715
 & & 80~MHz & & System clock, Spartan 6\\\hline
3716 21 dgisselq
\end{clocklist}
3717
\caption{List of Clocks}\label{tbl:clocks}
3718
\end{center}\end{table}
3719
I hesitate to suggest that the core can run faster than 100~MHz, since I have
3720
had struggled with various timing violations to keep it at 100~MHz.  So, for
3721
now, I will only state that it can run at 100~MHz.
3722
 
3723 69 dgisselq
On a SPARTAN 6, the clock can run successfully at 80~MHz.
3724 21 dgisselq
 
3725 199 dgisselq
A second Artix--7 design on the Digilent's Arty board is limited to 81.25~MHz
3726
by the memory interface generated core used to access SDRAM.
3727
 
3728 21 dgisselq
\chapter{I/O Ports}\label{chap:ioports}
3729 199 dgisselq
This chapter presents and outlines the various I/O lines in and out of the
3730
ZipSystem.  Since the ZipCPU needs to be a component of such a larger part,
3731
this makes sense.
3732
 
3733
The I/O ports to the ZipSystem may be grouped into three categories.  The first
3734 33 dgisselq
is that of the master wishbone used by the CPU, then the slave wishbone used
3735
to command the CPU via a debugger, and then the rest.  The first two of these
3736
were already discussed in the wishbone chapter.  They are listed here
3737
for completeness in Tbl.~\ref{tbl:iowb-master}
3738
\begin{table}
3739
\begin{center}\begin{portlist}
3740
{\tt o\_wb\_cyc}   &  1 & Output & Indicates an active Wishbone cycle\\\hline
3741
{\tt o\_wb\_stb}   &  1 & Output & WB Strobe signal\\\hline
3742
{\tt o\_wb\_we}    &  1 & Output & Write enable\\\hline
3743
{\tt o\_wb\_addr}  & 32 & Output & Bus address \\\hline
3744
{\tt o\_wb\_data}  & 32 & Output & Data on WB write\\\hline
3745
{\tt i\_wb\_ack}   &  1 & Input  & Slave has completed a R/W cycle\\\hline
3746
{\tt i\_wb\_stall} &  1 & Input  & WB bus slave not ready\\\hline
3747
{\tt i\_wb\_data}  & 32 & Input  & Incoming bus data\\\hline
3748 69 dgisselq
{\tt i\_wb\_err}   &  1 & Input  & Bus Error indication\\\hline
3749 33 dgisselq
\end{portlist}\caption{CPU Master Wishbone I/O Ports}\label{tbl:iowb-master}\end{center}\end{table}
3750
and~\ref{tbl:iowb-slave} respectively.
3751
\begin{table}
3752
\begin{center}\begin{portlist}
3753 199 dgisselq
{\tt i\_dbg\_cyc}   &  1 & Input & Indicates an active Wishbone cycle\\\hline
3754
{\tt i\_dbg\_stb}   &  1 & Input & WB Strobe signal\\\hline
3755
{\tt i\_dbg\_we}    &  1 & Input & Write enable\\\hline
3756
{\tt i\_dbg\_addr}  &  1 & Input & Bus address, command or data port \\\hline
3757
{\tt i\_dbg\_data}  & 32 & Input & Data on WB write\\\hline
3758
{\tt o\_dbg\_ack}   &  1 & Output  & Slave has completed a R/W cycle\\\hline
3759
{\tt o\_dbg\_stall} &  1 & Output  & WB bus slave not ready\\\hline
3760
{\tt o\_dbg\_data}  & 32 & Output  & Incoming bus data\\\hline
3761 33 dgisselq
\end{portlist}\caption{CPU Debug Wishbone I/O Ports}\label{tbl:iowb-slave}\end{center}\end{table}
3762 21 dgisselq
 
3763 33 dgisselq
There are only four other lines to the CPU: the external clock, external
3764
reset, incoming external interrupt line(s), and the outgoing debug interrupt
3765
line.  These are shown in Tbl.~\ref{tbl:ioports}.
3766
\begin{table}
3767
\begin{center}\begin{portlist}
3768
{\tt i\_clk} & 1 & Input & The master CPU clock \\\hline
3769
{\tt i\_rst} & 1 & Input &  Active high reset line \\\hline
3770 69 dgisselq
{\tt i\_ext\_int} & 1\ldots 16 & Input &  Incoming external interrupts, actual
3771 199 dgisselq
                value set by implementation parameter.  This is only ever one
3772
                for the ZipBones implementation.\\\hline
3773 33 dgisselq
{\tt o\_ext\_int} & 1 & Output & CPU Halted interrupt \\\hline
3774
\end{portlist}\caption{I/O Ports}\label{tbl:ioports}\end{center}\end{table}
3775 199 dgisselq
The clock line was discussed briefly in Chapt.~\ref{chap:clocks}.  The reset
3776
line is an active high reset.  When
3777
asserted, the CPU will start running again from its {\tt RESET\_ADDRESS} in
3778 69 dgisselq
memory.  Further, depending upon how the CPU is configured and specifically
3779
based upon how the {\tt START\_HALTED} parameter is set, the CPU may or may
3780
not start running automatically following a reset.  The {\tt i\_ext\_int}
3781 199 dgisselq
bus is for set of external interrupt lines to the ZipSystem.  This line may
3782
actually be as wide as 16~external interrupts, depending upon the setting of
3783
the {\tt EXTERNAL\_INTERRUPTS} parameter.  Finally, the ZipSystem produces one
3784 69 dgisselq
external interrupt whenever the entire CPU halts to wait for the debugger.
3785 33 dgisselq
 
3786 199 dgisselq
The I/O lines to the ZipBones package are identical to those of the ZipSystem,
3787
with the only exception that the ZipBones package has only a single interrupt
3788
line input.  This means that the ZipBones implementation practically depends
3789
upon an external interrupt controller.
3790
 
3791 36 dgisselq
\chapter{Initial Assessment}\label{chap:assessment}
3792
 
3793 199 dgisselq
Having now worked with the ZipCPU for a while, it is worth offering an
3794 36 dgisselq
honest assessment of how well it works and how well it was designed. At the
3795
end of this assessment, I will propose some changes that may take place in a
3796 199 dgisselq
later version of this ZipCPU to make it better.
3797 36 dgisselq
 
3798
\section{The Good}
3799
\begin{itemize}
3800 199 dgisselq
\item The ZipCPU was designed to be a simple and light weight CPU.  It has
3801
        achieved this end nicely.  The proof of this is the full multitasking
3802
        operating system built for Digilent's CMod S6 board, based around
3803
        a very small Spartan~6/LX4 FPGA.
3804
 
3805
        As a result, the ZipCPU also makes a good starting point for anyone
3806
        who wishes to build a general purpose CPU and then to experiment with
3807
        building and adding particular features.  Modifications should be
3808
        simple enough.
3809
 
3810
        Indeed, a non--pipelined version of the bare ZipBones (with no
3811
        peripherals) has been built that only uses 1.3k~6--LUTs.  When using
3812
        pipelining, the full cache, and all of the peripherals, the ZipSystem
3813
        can take up to 4.5~k LUTs.  Where it fits in between is a function of
3814
        your needs.
3815
 
3816
        A new implementation using an iCE40 FPGA suggests that the ZipCPU
3817
        will fit within the 4k~4--way LUTs of the iCE40 HK4X FPGA, but only
3818
        just barely.
3819
 
3820
\item The ZipCPU was designed to be an implementable soft core that could be
3821 36 dgisselq
        placed within an FPGA, controlling actions internal to the FPGA. It
3822 199 dgisselq
        fits this role rather nicely. It does not fit the role of a general
3823
        purpose CPU replacement very well: it has no octet level access,
3824
        no double--precision floating point capability, neither does it have
3825
        vector registers and operations.  However, it was never designed to be
3826
        such a general purpose CPU but rather a system within a chip.
3827
 
3828
\item The extremely simplified instruction set of the ZipCPU was a good
3829 36 dgisselq
        choice. Although it does not have many of the commonly used
3830
        instructions, PUSH, POP, JSR, and RET among them, the simplified
3831
        instruction set has demonstrated an amazing versatility. I will contend
3832
        therefore and for anyone who will listen, that this instruction set
3833
        offers a full and complete capability for whatever a user might wish
3834
        to do with two exceptions: bytewise character access and accelerated
3835
        floating-point support.
3836
\item This simplified instruction set is easy to decode.
3837
\item The simplified bus transactions (32-bit words only) were also very easy
3838
        to implement.
3839 199 dgisselq
\item The burst load/store approach using the wishbone pipelining mode is
3840
        novel, and can be used to greatly increase the speed of the processor.
3841
\item The novel approach to interrupts greatly facilitates the development of
3842
        interrupt handlers from within high level languages.
3843
 
3844
        The approach involves a single interrupt ``vector'' only, and simply
3845
        switches the CPU back to the instruction it left off at.  By using
3846
        this approach, interrupt handlers no longer need careful assembly
3847
        language scripting in order to save their context upon any interrupt.
3848
 
3849
        At the same time, if most modern systems handle interrupt vectoring in
3850
        software anyway, why maintain complicated hardware support for it?
3851
 
3852 36 dgisselq
\item My goal of a high rate of instructions per clock may not be the proper
3853 199 dgisselq
        measure of this CPU. For example, if instructions are being read from a
3854
        SPI flash device, such as is common among FPGA implementations, these
3855
        same instructions may suffer stalls of between 64 and 128 cycles per
3856 36 dgisselq
        instruction just to read the instruction from the flash. Executing the
3857
        instruction in a single clock cycle is no longer the appropriate
3858
        measure. At the same time, it should be possible to use the DMA
3859
        peripheral to copy instructions from the FLASH to a temporary memory
3860
        location, after which they may be executed at a single instruction
3861
        cycle per access again.
3862 199 dgisselq
 
3863
\item Both GCC and binutils back ends exist for the ZipCPU.
3864 36 dgisselq
\end{itemize}
3865
 
3866
\section{The Not so Good}
3867
\begin{itemize}
3868 199 dgisselq
\item The CPU has no octet (character) support. This is both good and bad.
3869 36 dgisselq
        Realistically, the CPU works just fine without it. Characters can be
3870
        supported as subsets of 32-bit words without any problem. Practically,
3871 199 dgisselq
        though, this creates two problems.  The first is that it makes porting
3872
        code from non-ZipCPU platforms to the ZipCPU is difficult--especially
3873
        anything that depends upon the existence of {\tt *int8\_t},
3874
        {\tt *int16\_t}, the size difference between
3875
        {\tt sizeof(int)=4*sizeof(char)}, or that tries to
3876 36 dgisselq
        create unions with characters and integers and then attempts to
3877 199 dgisselq
        reference the address of the characters within that union.
3878 36 dgisselq
 
3879 199 dgisselq
        The second problem is that peripherals that depend upon character
3880
        support on the bus may need to be rewritten to work on a 32--bit bus.
3881 36 dgisselq
 
3882 199 dgisselq
\item The ZipCPU does not (yet) support a data cache.  One is currently under
3883
        development.
3884 36 dgisselq
 
3885 199 dgisselq
        The ZipCPU compensates for this lack via its burst memory capability.
3886
        Further, performance tests using Dhrystone suggest that the ZipCPU is
3887
        no slower than other processors containing a data cache.
3888 68 dgisselq
 
3889 36 dgisselq
\item Many other instruction sets offer three operand instructions, whereas
3890 199 dgisselq
        the ZipCPU only offers two operand instructions. This means that it
3891
        may take the ZipCPU more instructions to do many of the same operations.
3892
        The good part of this is that it gives the ZipCPU a greater amount of
3893 36 dgisselq
        flexibility in its immediate operand mode, although that increased
3894
        flexibility isn't necessarily as valuable as one might like.
3895
 
3896 199 dgisselq
        The impact of this lack of three operand instructions is application
3897
        dependent, but does not appear to be too severe.
3898 36 dgisselq
 
3899 199 dgisselq
\item The ZipCPU doesn't support out of order execution.
3900
 
3901
        I suppose it could be modified to do so, but then it would no longer
3902
        be the ``simple'' and low LUT count CPU it was designed to be.
3903
 
3904
\item Although switching to an interrupt context in the ZipCPU design doesn't
3905 36 dgisselq
        require a tremendous swapping of registers, in reality it still
3906 199 dgisselq
        does--since any task swap (such as swapping to a task waiting on an
3907
        interrupt) still requires saving and restoring all 16~user registers.
3908
        That's a lot of memory movement just to service an interrupt.
3909 36 dgisselq
 
3910 199 dgisselq
        This isn't nearly as bad as it sounds, however, since most RISC
3911
        architectures have 32~registers that will need to be swapped upon any
3912
        context swap.
3913
 
3914
\item The ZipCPU is by no means generic: it will never handle addresses
3915
        larger than 32-bits (4GW or 16GB) without a complete and total redesign.
3916 36 dgisselq
        This may limit its utility as a generic CPU in the future, although
3917 199 dgisselq
        as an embedded CPU within an FPGA this isn't really much of a
3918
        restriction.
3919 36 dgisselq
 
3920 199 dgisselq
\item While a toolchain does exist for the ZipCPU, it isn't yet fully featured.
3921
        The ZipCPU has no support for soft floating point arithmetic,
3922
        nor does it have support for several standard library functions.
3923
        Indeed, full C library support and gdb support are still lacking.
3924 36 dgisselq
\end{itemize}
3925
 
3926
\section{The Next Generation}
3927 199 dgisselq
This section could also be labeled as my ``To do'' list.  It outlines where
3928
you may expect features in the future.  Currently, there are five primary
3929
items on my to do list:
3930
\begin{enumerate}
3931
\item Soft Floating Point capability
3932 36 dgisselq
 
3933 199 dgisselq
        The lack of any floating point capability, either hard or soft, makes
3934
        porting math software to the ZipCPU difficult.  Simply building a
3935
        soft floating point library will solve this problem.
3936 36 dgisselq
 
3937 199 dgisselq
\item A C library.
3938
 
3939
        The lack of octet support has so far prevented the porting of
3940
        newlib to the ZipCPU platform.  In the end, it may mean that any
3941
        C library implementation for the ZipCPU may be subtly different
3942
        from any you are familiar with.
3943
 
3944
\item A data cache
3945
 
3946
        A preliminary data cache implemented as a write through cache has
3947
        been developed.  Adding this into the CPU should require few changes
3948
        internal to the CPU.  I expect future versions of the CPU will permit
3949
        this as an option.
3950
 
3951
\item A Memory Management Unit
3952