Subversion Repositories zipcpu

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%%

%% Filename:    spec.tex

%%

%% Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

%%

%% Purpose:     This LaTeX file contains all of the documentation/description

%%              currently provided with this Zip CPU soft core.  It supersedes

%%              any information about the instruction set or CPUs found

%%              elsewhere.  It's not nearly as interesting, though, as the PDF

%%              file it creates, so I'd recommend reading that before diving

%%              into this file.  You should be able to find the PDF file in

%%              the SVN distribution together with this PDF file and a copy of

%%              the GPL-3.0 license this file is distributed under.  If not,

%%              just type 'make' in the doc directory and it (should) build

%%              without a problem.

%%

%%

%% Creator:     Dan Gisselquist

%%              Gisselquist Technology, LLC

%%

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%%

%% Copyright (C) 2015, Gisselquist Technology, LLC

%%

%% This program is free software (firmware): you can redistribute it and/or

%% modify it under the terms of  the GNU General Public License as published

%% by the Free Software Foundation, either version 3 of the License, or (at

%% your option) any later version.

%%

%% This program is distributed in the hope that it will be useful, but WITHOUT

%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

%% for more details.

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%% You should have received a copy of the GNU General Public License along

%% with this program.  (It's in the $(ROOT)/doc directory, run make with no

%% target there if the PDF file isn't present.)  If not, see

%% <http://www.gnu.org/licenses/> for a copy.

%%

%% License:     GPL, v3, as defined and found on www.gnu.org,

%%              http://www.gnu.org/licenses/gpl.html

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%%

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\documentclass{gqtekspec}

\usepackage{import}

% \graphicspath{{../gfx}}

\project{Zip CPU}

\title{Specification}

\author{Dan Gisselquist, Ph.D.}

\email{dgisselq (at) opencores.org}

\revision{Rev.~0.6}

\definecolor{webred}{rgb}{0.2,0,0}

\definecolor{webgreen}{rgb}{0,0.2,0}

\usepackage[dvips,ps2pdf,colorlinks=true,

        anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames,

        pdfauthor={Dan Gisselquist},

        pdfsubject={Zip CPU}]{hyperref}

\begin{document}

\pagestyle{gqtekspecplain}

\titlepage

\begin{license}

Copyright (C) \theyear\today, Gisselquist Technology, LLC

This project is free software (firmware): you can redistribute it and/or

modify it under the terms of  the GNU General Public License as published

by the Free Software Foundation, either version 3 of the License, or (at

your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT

ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License along

with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a

copy.

\end{license}

\begin{revisionhistory}

0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline

0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline

0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline

0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline

0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline

0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline

\end{revisionhistory}

% Revision History

% Table of Contents, named Contents

\tableofcontents

\listoffigures

\listoftables

\begin{preface}

Many people have asked me why I am building the Zip CPU. ARM processors are

good and effective. Xilinx makes and markets Microblaze, Altera Nios, and both

have better toolsets than the Zip CPU will ever have. OpenRISC is also

available, RISC--V may be replacing it. Why build a new processor?

The easiest, most obvious answer is the simple one: Because I can.

There's more to it, though. There's a lot that I would like to do with a

processor, and I want to be able to do it in a vendor independent fashion.

First, I would like to be able to place this processor inside an FPGA.  Without

paying royalties, ARM is out of the question.  I would then like to be able to

generate Verilog code, both for the processor and the system it sits within,

that can run equivalently on both Xilinx and Altera chips, and that can be

easily ported from one manufacturer's chipsets to another. Even more, before

purchasing a chip or a board, I would like to know that my soft core works. I

would like to build a test bench to test components with, and Verilator is my

chosen test bench. This forces me to use all Verilog, and it prevents me from

using any proprietary cores. For this reason, Microblaze and Nios are out of

the question.

Why not OpenRISC? That's a hard question. The OpenRISC team has done some

wonderful work on an amazing processor, and I'll have to admit that I am

envious of what they've accomplished. I would like to port binutils to the

Zip CPU, as I would like to port GCC and GDB. They are way ahead of me. The

OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has

a lot of features of modern CPUs within it that ... well, let's just say it's

not the little guy on the block. The Zip CPU is lighter weight, costing only

about 2,300 LUTs with no peripherals, and 3,200 LUTs with some very basic

peripherals.

My final reason is that I'm building the Zip CPU as a learning experience. The

Zip CPU has allowed me to learn a lot about how CPUs work on a very micro

level. For the first time, I am beginning to understand many of the Computer

Architecture lessons from years ago.

To summarize: Because I can, because it is open source, because it is light

weight, and as an exercise in learning.

\end{preface}

\chapter{Introduction}

\pagenumbering{arabic}

\setcounter{page}{1}

The original goal of the Zip CPU was to be a very simple CPU.   You might

think of it as a poor man's alternative to the OpenRISC architecture.

For this reason, all instructions have been designed to be as simple as

possible, and are all designed to be executed in one instruction cycle per

instruction, barring pipeline stalls.  Indeed, even the bus has been simplified

to a constant 32-bit width, with no option for more or less.  This has

resulted in the choice to drop push and pop instructions, pre-increment and

post-decrement addressing modes, and more.

For those who like buzz words, the Zip CPU is:

\begin{itemize}

\item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits,

                instructions are 32-bits wide, etc.

\item A RISC CPU.  There is no microcode for executing instructions.  All

        instructions are designed to be completed in one clock cycle.

\item A Load/Store architecture.  (Only load and store instructions

                can access memory.)

\item Wishbone compliant.  All peripherals are accessed just like

                memory across this bus.

\item A Von-Neumann architecture.  (The instructions and data share a

                common bus.)

\item A pipelined architecture, having stages for {\bf Prefetch},

                {\bf Decode}, {\bf Read-Operand}, the {\bf ALU/Memory}

                unit, and {\bf Write-back}.  See Fig.~\ref{fig:cpu}

\begin{figure}\begin{center}

\includegraphics[width=3.5in]{../gfx/cpu.eps}

\caption{Zip CPU internal pipeline architecture}\label{fig:cpu}

\end{center}\end{figure}

                for a diagram of this structure.

\item Completely open source, licensed under the GPL.\footnote{Should you

        need a copy of the Zip CPU licensed under other terms, please

        contact me.}

\end{itemize}

The Zip CPU also has one very unique feature: the ability to do pipelined loads

and stores.  This allows the CPU to access on-chip memory at one access per

clock, minus a stall for the initial access.

\section{Characteristics of a SwiC}

Here, we shall define a soft core internal to an FPGA as a ``System within a

Chip,'' or a SwiC.  SwiCs have some very unique properties internal to them

that have influenced the design of the Zip CPU.  Among these are the bus,

memory, and available peripherals.

Most other approaches to soft core CPU's employ a Harvard architecture.

This allows these other CPU's to have two separate bus structures: one for the

program fetch, and the other for thememory.  The Zip CPU is fairly unique in

its approach because it uses a von Neumann architecture.  This was done for

simplicity.  By using a von Neumann architecture, only one bus needs to be

implemented within any FPGA.  This helps to minimize real-estate, while

maintaining a high clock speed.  The disadvantage is that it can severely

degrade the overall instructions per clock count.

Soft core's within an FPGA have an additional characteristic regarding

memory access: it is slow.  Memory on chip may be accessed at a single

cycle per access, but small FPGA's have a limited amount of memory on chip.

Going off chip, however, is expensive.  Two examples will prove this point.  On

the XuLA2 board, Flash can be accessed at 128~cycles per 32--bit word,

or 64~cycles per subsequent word in a pipelined architecture.  Likewise, the

SDRAM chip on the XuLA2 board allows 6~cycle access for a write, 10~cycles

per read, and 2~cycles for any subsequent pipelined access read or write.

Either way you look at it, this memory access will be slow and this doesn't

account for any logic delays should the bus implementation logic get

complicated.

As may be noticed from the above discussion about memory speed, a second

characteristic of memory is that all memory accesses may be pipelined, and

that pipelined memory access is faster than non--pipelined access.  Therefore,

a SwiC soft core should support pipelined operations, but it should also

allow a higher priority subsystem to get access to the bus (no starvation).

As a further characteristic of SwiC memory options, on-chip cache's are

expensive.  If you want to have a minimum of logic, cache logic may not be

the highest on the priority list.

In sum, memory is slow.  While one processor on one FPGA may be able to fill

its pipeline, the same processor on another FPGA may struggle to get more than

one instruction at a time into the pipeline.  Any SwiC must be able to deal

with both cases: fast and slow memories.

A final characteristic of SwiC's within FPGA's is the peripherals.

Specifically, FPGA's are highly reconfigurable.  Soft peripherals can easily

be created on chip to support the SwiC if necessary.  As an example, a simple

30-bit peripheral could easily support reversing 30-bit numbers: a read from

the peripheral returns it's bit--reversed address.  This is cheap within an

FPGA, but expensive in instructions.

Indeed, anything that must be done fast within an FPGA is likely to already

be done--elsewhere in the fabric.  This leaves the CPU with the role of handling

sequential tasks that need a lot of state.

This means that the SwiC needs to live within a very unique environment,

separate and different from the traditional SoC.  That isn't to say that a

SwiC cannot be turned into a SoC, just that this SwiC has not been designed

for that purpose.

\section{Lessons Learned}

Now, however, that I've worked on the Zip CPU for a while, it is not nearly

as simple as I originally hoped.  Worse, I've had to adjust to create

capabilities that I was never expecting to need.  These include:

\begin{itemize}

\item {\bf External Debug:} Once placed upon an FPGA, some external means is

        still necessary to debug this CPU.  That means that there needs to be

        an external register that can control the CPU: reset it, halt it, step

        it, and tell whether it is running or not.  My chosen interface

        includes a second register similar to this control register.  This

        second register allows the external controller or debugger to examine

        registers internal to the CPU.

\item {\bf Internal Debug:} Being able to run a debugger from within

        a user process requires an ability to step a user process from

        within a debugger.  It also requires a break instruction that can

        be substituted for any other instruction, and substituted back.

        The break is actually difficult: the break instruction cannot be

        allowed to execute.  That way, upon a break, the debugger should

        be able to jump back into the user process to step the instruction

        that would've been at the break point initially, and then to

        replace the break after passing it.

        Incidentally, this break messes with the prefetch cache and the

        pipeline: if you change an instruction partially through the pipeline,

        the whole pipeline needs to be cleansed.  Likewise if you change

        an instruction in memory, you need to make sure the cache is reloaded

        with the new instruction.

\item {\bf Prefetch Cache:} My original implementation had a very

        simple prefetch stage.  Any time the PC changed the prefetch would go

        and fetch the new instruction.  While this was perhaps this simplest

        approach, it cost roughly five clocks for every instruction.  This

        was deemed unacceptable, as I wanted a CPU that could execute

        instructions in one cycle.  I therefore have a prefetch cache that

        issues pipelined wishbone accesses to memory and then pushes

        instructions at the CPU.  Sadly, this accounts for about 20\% of the

        logic in the entire CPU, or 15\% of the logic in the entire system.

\item {\bf Operating System:} In order to support an operating system,

        interrupts and so forth, the CPU needs to support supervisor and

        user modes, as well as a means of switching between them.  For example,

        the user needs a means of executing a system call.  This is the

        purpose of the {\bf `trap'} instruction.  This instruction needs to

        place the CPU into supervisor mode (here equivalent to disabling

        interrupts), as well as handing it a parameter such as identifying

        which O/S function was called.

My initial approach to building a trap instruction was to create an external

peripheral which, when written to, would generate an interrupt and could

return the last value written to it.  In practice, this approach didn't work

at all: the CPU executed two instructions while waiting for the

trap interrupt to take place.  Since then, I've decided to keep the rest of

the CC register for that purpose so that a write to the CC register, with the

GIE bit cleared, could be used to execute a trap.  This has other problems,

though, primarily in the limitation of the uses of the CC register.  In

particular, the CC register is the best place to put CPU state information and

to ``announce'' special CPU features (floating point, etc).  So the trap

instruction still switches to interrupt mode, but the CC register is not

nearly as useful for telling the supervisor mode processor what trap is being

executed.

Modern timesharing systems also depend upon a {\bf Timer} interrupt

to handle task swapping.  For the Zip CPU, this interrupt is handled

external to the CPU as part of the CPU System, found in {\tt zipsystem.v}.

The timer module itself is found in {\tt ziptimer.v}.

\item {\bf Pipeline Stalls:} My original plan was to not support pipeline

        stalls at all, but rather to require the compiler to properly schedule

        all instructions so that stalls would never be necessary.  After trying

        to build such an architecture, I gave up, having learned some things:

        First, and ideal pipeline might look something like

        Fig.~\ref{fig:ideal-pipeline}.

\begin{figure}

\begin{center}

\includegraphics[width=4in]{../gfx/fullpline.eps}

\caption{An Ideal Pipeline: One instruction per clock cycle}\label{fig:ideal-pipeline}

\end{center}\end{figure}

        Notice that, in this figure, all the pipeline stages are complete and

        full.  Every instruction takes one clock and there are no delays.

        However, as the discussion above pointed out, the memory associated

        with a SwiC may not allow single clock access.  It may be instead

        that you can only read every two clocks.  In that case, what shall

        the pipeline look like?  Should it look like

        Fig.~\ref{fig:waiting-pipeline},

\begin{figure}\begin{center}

\includegraphics[width=4in]{../gfx/stuttra.eps}

\caption{Instructions wait for each other}\label{fig:waiting-pipeline}

\end{center}\end{figure}

        where instructions are held back until the pipeline is full, or should

        it look like Fig.~\ref{fig:independent-pipeline},

\begin{figure}\begin{center}

\includegraphics[width=4in]{../gfx/stuttrb.eps}

\caption{Instructions proceed independently}\label{fig:independent-pipeline}

\end{center}\end{figure}

        where each instruction is allowed to move through the pipeline

        independently?  For better or worse, the Zip CPU allows instructions

        to move through the pipeline independently.

        One approach to avoiding stalls is to use a branch delay slot,

        such as is shown in Fig.~\ref{fig:brdelay}.

\begin{figure}\begin{center}

\includegraphics[width=4in]{../gfx/bdly.eps}

\caption{A typical branch delay slot approach}\label{fig:brdelay}

\end{center}\end{figure}

        In this figure, instructions

        {\tt BR} (a branch), {\tt BD} (a branch delay instruction),

        are followed by instructions after the branch: {\tt IA}, {\tt IB}, etc.

        Since it takes a processor a clock cycle to execute a branch, the

        delay slot allows the processor to do something useful in that

        branch.  The problem the Zip CPU has with this approach is, what

        happens when the pipeline looks like Fig.~\ref{fig:brbroken}?

\begin{figure}\begin{center}

\includegraphics[width=4in]{../gfx/bdbroken.eps}

\caption{The branch delay slot breaks with a slow memory}\label{fig:brbroken}

\end{center}\end{figure}

        In this case, the branch delay slot never gets filled in the first

        place, and so the pipeline squashes it before it gets executed.

        If not that, then what happens when handling interrupts or

        debug stepping: when has the CPU finished an instruction?

        When the {\tt BR} instruction has finished, or must {\tt BD}

        follow every {\tt BR}?  and, again, what if the pipeline isn't

        full?

        These thoughts killed any hopes of doing delayed branching.

        So I switched to a model of discrete execution: Once an instruction

        enters into either the ALU or memory unit, the instruction is

        guaranteed to complete.  If the logic recognizes a branch or a

        condition that would render the instruction entering into this stage

        possibly inappropriate (i.e. a conditional branch preceding a store

        instruction for example), then the pipeline stalls for one cycle

        until the conditional branch completes.  Then, if it generates a new

        PC address, the stages preceding are all wiped clean.

        This model, however, generated too many pipeline stalls, so the

        discrete execution model was modified to allow instructions to go

        through the ALU unit and be canceled before writeback.  This removed

        the stall associated with ALU instructions before untaken branches.

        The discrete execution model allows such things as sleeping, as

        outlined in Fig.~\ref{fig:sleeping}.

\begin{figure}\begin{center}

\includegraphics[width=4in]{../gfx/sleep.eps}

\caption{How the CPU halts when sleeping}\label{fig:sleeping}

\end{center}\end{figure}

        If the

        CPU is put to ``sleep,'' the ALU and memory stages stall and back up

        everything before them.  Likewise, anything that has entered the ALU

        or memory stage when the CPU is placed to sleep continues to completion.

        To handle this logic, each pipeline stage has three control signals:

        a valid signal, a stall signal, and a clock enable signal.  In

        general, a stage stalls if it's contents are valid and the next step

        is stalled.  This allows the pipeline to fill any time a later stage

        stalls, as illustrated in Fig.~\ref{fig:stacking}.

\begin{figure}\begin{center}

\includegraphics[width=4in]{../gfx/stacking.eps}

\caption{Instructions can stack up behind a stalled instruction}\label{fig:stacking}

\end{center}\end{figure}

        This approach is also different from other pipeline approaches.

        Instead of keeping the entire pipeline filled, each stage is treated

        independently.  Therefore, individual stages may move forward as long

        as the subsequent stage is available, regardless of whether the stage

        behind it is filled.

\item {\bf Verilog Modules:} When examining how other processors worked

        here on open cores, many of them had one separate module per pipeline

        stage.  While this appeared to me to be a fascinating and commendable

        idea, my own implementation didn't work out quite so nicely.

        As an example, the decode module produces a {\em lot} of

        control wires and registers.  Creating a module out of this, with

        only the simplest of logic within it, seemed to be more a lesson

        in passing wires around, rather than encapsulating logic.

        Another example was the register writeback section.  I would love

        this section to be a module in its own right, and many have made them

        such.  However, other modules depend upon writeback results other

        than just what's placed in the register (i.e., the control wires).

        For these reasons, I didn't manage to fit this section into it's

        own module.

        The result is that the majority of the CPU code can be found in

        the {\tt zipcpu.v} file.

\end{itemize}

With that introduction out of the way, let's move on to the instruction

set.

\chapter{CPU Architecture}\label{chap:arch}

The Zip CPU supports a set of two operand instructions, where the second operand

(always a register) is the result.  The only exception is the store instruction,

where the first operand (always a register) is the source of the data to be

stored.

\section{Simplified Bus}

The bus architecture of the Zip CPU is that of a simplified WISHBONE bus.

It has been simplified in this fashion: all operations are 32--bit operations.

The bus is neither little endian nor big endian.  For this reason, all words

are 32--bits.  All instructions are also 32--bits wide.  Everything has been

built around the 32--bit word.

\section{Register Set}

The Zip CPU supports two sets of sixteen 32-bit registers, a supervisor

and a user set as shown in Fig.~\ref{fig:regset}.

\begin{figure}\begin{center}

\includegraphics[width=3.5in]{../gfx/regset.eps}

\caption{Zip CPU Register File}\label{fig:regset}

\end{center}\end{figure}

The supervisor set is used in interrupt mode when interrupts are disabled,

whereas the user set is used otherwise.  Of this register set, the Program

Counter (PC) is register 15, whereas the status register (SR) or condition

code register

(CC) is register 14.  By convention, the stack pointer will be register 13 and

noted as (SP)--although there is nothing special about this register other

than this convention.

The CPU can access both register sets via move instructions from the

supervisor state, whereas the user state can only access the user registers.

The status register is special, and bears further mention.  As shown in

Fig.~\ref{tbl:cc-register},

\begin{table}\begin{center}

\begin{bitlist}

31\ldots 11 & R/W & Reserved for future uses\\\hline

10 & R & (Reserved for) Bus-Error Flag\\\hline

9 & R & Trap, or user interrupt, Flag.  Cleared on return to userspace.\\\hline

8 & R & Illegal Instruction Flag\\\hline

7 & R/W & Break--Enable\\\hline

6 & R/W & Step\\\hline

5 & R/W & Global Interrupt Enable (GIE)\\\hline

4 & R/W & Sleep.  When GIE is also set, the CPU waits for an interrupt.\\\hline

3 & R/W & Overflow\\\hline

2 & R/W & Negative.  The sign bit was set as a result of the last ALU instruction.\\\hline

1 & R/W & Carry\\\hline

\end{bitlist}

\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}

\end{center}\end{table}

the lower 11~bits of the status register form

a set of CPU state and condition codes.  Writes to other bits of this register

are preserved.

Of the condition codes, the bottom four bits are the current flags:

                Zero (Z),

                Carry (C),

                Negative (N),

                and Overflow (V).

The next bit is a clock enable (0 to enable) or sleep bit (1 to put

        the CPU to sleep).  Setting this bit will cause the CPU to

        wait for an interrupt (if interrupts are enabled), or to

        completely halt (if interrupts are disabled).

The sixth bit is a global interrupt enable bit (GIE).  When this

        sixth bit is a `1' interrupts will be enabled, else disabled.  When

        interrupts are disabled, the CPU will be in supervisor mode, otherwise

        it is in user mode.  Thus, to execute a context switch, one only

        need enable or disable interrupts.  (When an interrupt line goes

        high, interrupts will automatically be disabled, as the CPU goes

        and deals with its context switch.)  Special logic has been added to

        keep the user mode from setting the sleep register and clearing the

        GIE register at the same time, with clearing the GIE register taking

        precedence.

The seventh bit is a step bit.  This bit can be

        set from supervisor mode only.  After setting this bit, should

        the supervisor mode process switch to user mode, it would then

        accomplish one instruction in user mode before returning to supervisor

        mode.  Then, upon return to supervisor mode, this bit will

        be automatically cleared.  This bit has no effect on the CPU while in

        supervisor mode.

        This functionality was added to enable a userspace debugger

        functionality on a user process, working through supervisor mode

        of course.

The eighth bit is a break enable bit.  This controls whether a break

instruction in user mode will halt the processor for an external debugger

(break enabled), or whether the break instruction will simply send send the

CPU into interrupt mode.  Encountering a break in supervisor mode will

halt the CPU independent of the break enable bit.  This bit can only be set

within supervisor mode.

% Should break enable be a supervisor mode bit, while the break enable bit

% in user mode is a break has taken place bit?

%

This functionality was added to enable an external debugger to

        set and manage breakpoints.

The ninth bit is an illegal instruction bit.  When the CPU

tries to execute either a non-existant instruction, or an instruction from

an address that produces a bus error, the CPU will (if implemented) switch

to supervisor mode while setting this bit.  The bit will automatically be

cleared upon any return to user mode.

The tenth bit is a trap bit.  It is set whenever the user requests a soft

interrupt, and cleared on any return to userspace command.  This allows the

supervisor, in supervisor mode, to determine whether it got to supervisor

mode from a trap or from an external interrupt or both.

These status register bits are summarized in Tbl.~\ref{tbl:ccbits}.

\begin{table}

\begin{center}

\begin{tabular}{l|l}

Bit & Meaning \\\hline

9 & Soft trap, set on a trap from user mode, cleared when returning to user mode\\\hline

8 & Illegal instruction error flag \\\hline

7 & Halt on break, to support an external debugger \\\hline

6 & Step, single step the CPU in user mode\\\hline

5 & GIE, or Global Interrupt Enable \\\hline

4 & Sleep \\\hline

3 & V, or overflow bit.\\\hline

2 & N, or negative bit.\\\hline

1 & C, or carry bit.\\\hline

\end{tabular}

\caption{Condition Code / Status Register Bits}\label{tbl:ccbits}

\end{center}\end{table}

\section{Conditional Instructions}

Most, although not quite all, instructions may be conditionally executed.  From

the four condition code flags, eight conditions are defined.  These are shown

in Tbl.~\ref{tbl:conditions}.

\begin{table}

\begin{center}

\begin{tabular}{l|l|l}

Code & Mneumonic & Condition \\\hline

3'h0 & None & Always execute the instruction \\

3'h1 & {\tt .Z} & Only execute when 'Z' is set \\

3'h2 & {\tt .NE} & Only execute when 'Z' is not set \\

3'h3 & {\tt .GE} & Greater than or equal ('N' not set, 'Z' irrelevant) \\

3'h4 & {\tt .GT} & Greater than ('N' not set, 'Z' not set) \\

3'h5 & {\tt .LT} & Less than ('N' set) \\

3'h6 & {\tt .C} & Carry set\\

3'h7 & {\tt .V} & Overflow set\\

\end{tabular}

\caption{Conditions for conditional operand execution}\label{tbl:conditions}

\end{center}

\end{table}

There is no condition code for less than or equal, not C or not V.  Sorry,

I ran out of space in 3--bits.  Conditioning on a non--supported condition

is still possible, but it will take an extra instruction and a pipeline stall.  (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})

As an alternative, the condition may often be reversed, recovering those

extra two clocks.  Thus instead of \hbox{\tt CMP Rx,Ry;}

\hbox{\tt BNV label} you can issue a \hbox{\tt CMP Ry,Rx;} \hbox{\tt BV label}.

Conditionally executed ALU instructions will not further adjust the

condition codes, with the exception of \hbox{\tt CMP} and \hbox{\tt TST}

instructions.   Conditional \hbox{\tt CMP} or \hbox{\tt TST} instructions

will adjust conditions whenever their conditionals are true.  In this way,

multiple conditions may be evaluated without branches.  For example, to do

something if \hbox{\tt R0} is one and \hbox{\tt R1} is two, one might try

code such as Tbl.~\ref{tbl:dbl-condition}.

\begin{table}\begin{center}

\begin{tabular}{l}

        {\tt CMP 1,R0} \\

        {;\em Condition codes are now set based upon R0-1} \\

        {\tt CMP.Z 2,R1} \\

        {;\em If R0 $\neq$ 1, conditions are unchanged.} \\

        {;\em If R0 $=$ 1, conditions are set based upon R1-2.} \\

        {;\em Now do something based upon the conjunction of both conditions.} \\

        {;\em While we use the example of a STO, it could be any instruction.} \\

        {\tt STO.Z R0,(R2)} \\

\end{tabular}

\caption{An example of a double conditional}\label{tbl:dbl-condition}

\end{center}\end{table}

\section{Traditional Interrupt Handling}

\section{Operand B}

Many instruction forms have a 21-bit source ``Operand B'' associated with them.

This Operand B is either equal to a register plus a signed immediate offset,

or an immediate offset by itself.  This value is encoded as shown in

Tbl.~\ref{tbl:opb}.

\begin{table}\begin{center}

\begin{tabular}{|l|l|l|}\hline

Bit 20 & 19 \ldots 16 & 15 \ldots 0 \\\hline

1'b0 & \multicolumn{2}{l|}{20--bit Signed Immediate value} \\\hline

1'b1 & 4-bit Register & 16--bit Signed immediate offset \\\hline

\end{tabular}

\caption{Bit allocation for Operand B}\label{tbl:opb}

\end{center}\end{table}

Sixteen and twenty bit immediate values don't make sense for all instructions.

For example, what is the point of a 20--bit immediate when executing a 16--bit

multiply?  Likewise, why have a 16--bit immediate when adding to a logical

or arithmetic shift?  In these cases, the extra bits are reserved for future

instruction possibilities.

\section{Address Modes}

The Zip CPU supports two addressing modes: register plus immediate, and

immediate address.  Addresses are therefore encoded in the same fashion as

Operand B's, shown above.

A lot of long hard thought was put into whether to allow pre/post increment

and decrement addressing modes.  Finding no way to use these operators without

taking two or more clocks per instruction,\footnote{The two clocks figure

comes from the design of the register set, allowing only one write per clock.

That write is either from the memory unit or the ALU, but never both.} these

addressing modes have been

removed from the realm of possibilities.  This means that the Zip CPU has no

native way of executing push, pop, return, or jump to subroutine operations.

Each of these instructions can be emulated with a set of instructions from the

existing set.

\section{Move Operands}

The previous set of operands would be perfect and complete, save only that

the CPU needs access to non--supervisory registers while in supervisory mode.

Therefore, the MOV instruction is special and offers access to these registers

\ldots when in supervisory mode.  To keep the compiler simple, the extra bits

are ignored in non-supervisory mode (as though they didn't exist), rather than

being mapped to new instructions or additional capabilities.  The bits

indicating which register set each register lies within are the A-Usr and

B-Usr bits.  When set to a one, these refer to a user mode register.  When set

to a zero, these refer to a register in the current mode, whether user or

supervisor.  Further, because a load immediate instruction exists, there is no

move capability between an immediate and a register: all moves come from either

a register or a register plus an offset.

This actually leads to a bit of a problem: since the MOV instruction encodes

which register set each register is coming from or moving to, how shall a

compiler or assembler know how to compile a MOV instruction without knowing

the mode of the CPU at the time?  For this reason, the compiler will assume

all MOV registers are supervisor registers, and display them as normal.

Anything with the user bit set will be treated as a user register.  The CPU

will quietly ignore the supervisor bits while in user mode, and anything

marked as a user register will always be valid.

\section{Multiply Operations}

The Zip CPU supports two Multiply operations, a 16x16 bit signed multiply

({\tt MPYS}) and a 16x16 bit unsigned multiply ({\tt MPYU}).  In both

cases, the operand is a register plus a 16-bit immediate, subject to the

rule that the register cannot be the PC or CC registers.  The PC register

field has been stolen to create a multiply by immediate instruction.  The

CC register field is reserved.

\section{Floating Point}

The Zip CPU does not (yet) support floating point operations.  However, the

instruction set reserves two possibilities for future floating point

operations.

The first floating point operation hole in the instruction set involves

setting a proposed (but non-existent) floating point bit in the CC register.

The next instruction

would then simply interpret its operands as floating point instructions.

Not all instructions, however, have floating point equivalents.  Further, the

immediate fields do not apply in floating point mode, and must be set to

zero.  Not all instructions make sense as floating point operations.

Therefore, only the CMP, SUB, ADD, and MPY instructions may be issued as

floating point instructions.  Other instructions allow the examining of the

floating point bit in the CC register.  In all cases, the floating point bit

is cleared one instruction after it is set.

The other possibility for floating point operations involves exploiting the

hole in the instruction set that the NOOP and BREAK instructions reside within.

These two instructions use 24--bits of address space, when only a single bit

is necessary.  A simple adjustment to this space could create instructions

with 4--bit register addresses for each register, a 3--bit field for

conditional execution, and a 2--bit field for which operation.

In this fashion, such a floating point capability would only fill 13--bits of

the 24--bit field, still leaving lots of room for expansion.

In both cases, the Zip CPU would support 32--bit single precision floats

only, since other choices would complicate the pipeline.

The current architecture does not support a floating point not-implemented

interrupt.  Any soft floating point emulation must be done deliberately.

\section{Native Instructions}

The instruction set for the Zip CPU is summarized in

Tbl.~\ref{tbl:zip-instructions}.

\begin{table}\begin{center}

\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline

\rowcolor[gray]{0.85}

Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}

        & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}

        & Sets CC? \\\hline\hline

{\tt CMP(Sub)} & \multicolumn{4}{l|}{4'h0}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B}

                & Yes \\\hline

{\tt TST(And)} & \multicolumn{4}{l|}{4'h1}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

{\tt MOV} & \multicolumn{4}{l|}{4'h2}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & A-Usr

                & \multicolumn{4}{l|}{B-Reg}

                & B-Usr

                & \multicolumn{15}{l|}{15'bit signed offset}

                & \\\hline

{\tt LODI} & \multicolumn{4}{l|}{4'h3}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{24}{l|}{24'bit Signed Immediate}

                & \\\hline

{\tt NOOP} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{24}{l|}{24'h00}

                & \\\hline

{\tt BREAK} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{24}{l|}{24'h01}

                & \\\hline

{\em Reserved} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{24}{l|}{24'bits, but not 0 or 1.}

                & \\\hline

{\tt LODIHI }& \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b1

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{16}{l|}{16-bit Immediate}

                & \\\hline

{\tt LODILO} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b0

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{16}{l|}{16-bit Immediate}

                & \\\hline

16-b {\tt MPYU} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b0 & \multicolumn{4}{l|}{Reg}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

16-b {\tt MPYU}(I) & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b0 & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

16-b {\tt MPYS} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b1 & \multicolumn{4}{l|}{Reg}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

16-b {\tt MPYS}(I) & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b1 & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

{\tt ROL} & \multicolumn{4}{l|}{4'h5}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}

                & \\\hline

{\tt LOD} & \multicolumn{4}{l|}{4'h6}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B address}

                & \\\hline

{\tt STO} & \multicolumn{4}{l|}{4'h7}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B address}

                & \\\hline

{\tt SUB} & \multicolumn{4}{l|}{4'h8}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

{\tt AND} & \multicolumn{4}{l|}{4'h9}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

{\tt ADD} & \multicolumn{4}{l|}{4'ha}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

{\tt OR} & \multicolumn{4}{l|}{4'hb}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

{\tt XOR} & \multicolumn{4}{l|}{4'hc}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

{\tt LSL/ASL} & \multicolumn{4}{l|}{4'hd}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        & Yes \\\hline

{\tt ASR} & \multicolumn{4}{l|}{4'he}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        & Yes \\\hline

{\tt LSR} & \multicolumn{4}{l|}{4'hf}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        & Yes \\\hline

\end{tabular}

\caption{Zip CPU Instruction Set}\label{tbl:zip-instructions}

\end{center}\end{table}

As you can see, there's lots of room for instruction set expansion.  The

NOOP and BREAK instructions are the only instructions within one particular

24--bit hole.  The rest of this space is reserved for future enhancements.

\section{Derived Instructions}

The Zip CPU supports many other common instructions, but not all of them

are single cycle instructions.  The derived instruction tables,

Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, \ref{tbl:derived-3}

and~\ref{tbl:derived-4},

help to capture some of how these other instructions may be implemented on

the Zip CPU.  Many of these instructions will have assembly equivalents,

such as the branch instructions, to facilitate working with the CPU.

\begin{table}\begin{center}

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

Mapped & Actual  & Notes \\\hline

{\tt ABS Rx}

        & \parbox[t]{1.5in}{\tt TST -1,Rx\\NEG.LT Rx}

        & Absolute value, depends upon derived NEG.\\\hline

\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}

        & \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}

        & Add with carry \\\hline

{\tt BRA.Cond +/-\$Addr}

        & \hbox{\tt MOV.cond \$Addr+PC,PC}

        & Branch or jump on condition.  Works for 15--bit

                signed address offsets.\\\hline

{\tt BRA.Cond +/-\$Addr}

        & \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}

        & Branch/jump on condition.  Works for

        23 bit address offsets, but costs a register, an extra instruction,

        and sets the flags. \\\hline

{\tt BNC PC+\$Addr}

        & \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}

        & Example of a branch on an unsupported

                condition, in this case a branch on not carry \\\hline

{\tt BUSY } & {\tt MOV \$-1(PC),PC} & Execute an infinite loop \\\hline

{\tt CLRF.NZ Rx }

        & {\tt XOR.NZ Rx,Rx}

        & Clear Rx, and flags, if the Z-bit is not set \\\hline

{\tt CLR Rx }

        & {\tt LDI \$0,Rx}

        & Clears Rx, leaves flags untouched.  This instruction cannot be

                conditional. \\\hline

{\tt EXCH.W Rx }

        & {\tt ROL \$16,Rx}

        & Exchanges the top and bottom 16'bit words of Rx \\\hline

{\tt HALT }

        & {\tt Or \$SLEEP,CC}

        & This only works when issued in interrupt/supervisor mode.  In user

        mode this is simply a wait until interrupt instruction. \\\hline

{\tt INT } & {\tt LDI \$0,CC} &  \\\hline

{\tt IRET}

        & {\tt OR \$GIE,CC}

        & Also known as an RTU instruction (Return to Userspace) \\\hline

{\tt JMP R6+\$Addr}

        & {\tt MOV \$Addr(R6),PC}

        & \\\hline

{\tt JSR PC+\$Addr}

        & \parbox[t]{1.5in}{\tt SUB \$1,SP \\\