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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Blame information for rev 201

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1 195 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    busdelay.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Delay any access to the wishbone bus by a single clock.
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//
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//      When the first Zip System would not meet the timing requirements of
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//      the board it was placed upon, this bus delay was added to help out.
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//      It may no longer be necessary, having cleaned some other problems up
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//      first, but it will remain here as a means of alleviating timing
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//      problems.
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//
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//      The specific problem takes place on the stall line: a wishbone master
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//      *must* know on the first clock whether or not the bus will stall.
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//
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//
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//      After a period of time, I started a new design where the timing
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//      associated with this original bus clock just wasn't ... fast enough.
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//      I needed to delay the stall line as well.  A new busdelay was then
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//      written and debugged whcih delays the stall line.  (I know, you aren't
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//      supposed to delay the stall line--but what if you *have* to in order
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//      to meet timing?)  This new logic has been merged in with the old,
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//      and the DELAY_STALL line can be set to non-zero to use it instead
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//      of the original logic.  Don't use it if you don't need it: it will
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//      consume resources and slow your bus down more, but if you do need
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//      it--don't be afraid to use it.  
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//
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//      Both versions of the bus delay will maintain a single access per
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//      clock when pipelined, they only delay the time between the strobe
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//      going high and the actual command being accomplished.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module  busdelay(i_clk,
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                // The input bus
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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                        o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
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                // The delayed bus
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                o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr,o_dly_data,o_dly_sel,
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                        i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
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        parameter       AW=32, DW=32, DELAY_STALL = 0;
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        input   i_clk;
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        // Input/master bus
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        input                           i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [(AW-1):0]       i_wb_addr;
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        input           [(DW-1):0]       i_wb_data;
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        input           [(DW/8-1):0]     i_wb_sel;
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(DW-1):0]       o_wb_data;
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        output  wire                    o_wb_err;
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        // Delayed bus
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        output  reg                     o_dly_cyc, o_dly_stb, o_dly_we;
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        output  reg     [(AW-1):0]       o_dly_addr;
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        output  reg     [(DW-1):0]       o_dly_data;
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        output  reg     [(DW/8-1):0]     o_dly_sel;
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        input                           i_dly_ack;
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        input                           i_dly_stall;
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        input           [(DW-1):0]       i_dly_data;
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        input                           i_dly_err;
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        generate
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        if (DELAY_STALL != 0)
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        begin
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                reg     r_stb, r_we, r_rtn_stall, r_rtn_err;
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                reg     [(AW-1):0]       r_addr;
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                reg     [(DW-1):0]       r_data;
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                reg     [(DW/8-1):0]     r_sel;
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                initial o_dly_cyc  = 1'b0;
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                initial r_rtn_stall= 1'b0;
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                initial r_stb      = 1'b0;
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                always @(posedge i_clk)
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                begin
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                        o_dly_cyc <= (i_wb_cyc);
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                        if (!i_dly_stall)
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                        begin
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                                r_we   <= i_wb_we;
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                                r_addr <= i_wb_addr;
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                                r_data <= i_wb_data;
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                                r_sel  <= i_wb_sel;
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                                if (r_stb)
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                                begin
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                                        o_dly_we   <= r_we;
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                                        o_dly_addr <= r_addr;
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                                        o_dly_data <= r_data;
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                                        o_dly_sel  <= r_sel;
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                                        o_dly_stb  <= 1'b1;
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                                        r_rtn_stall <= 1'b0;
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                                        r_stb <= 1'b0;
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                                end else begin
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                                        o_dly_we   <= i_wb_we;
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                                        o_dly_addr <= i_wb_addr;
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                                        o_dly_data <= i_wb_data;
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                                        o_dly_sel  <= i_wb_sel;
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                                        o_dly_stb  <= i_wb_stb;
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                                        r_stb <= 1'b0;
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                                        r_rtn_stall <= 1'b0;
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                                end
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                        end else if ((!r_stb)&&(!o_wb_stall))
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                        begin
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                                r_we   <= i_wb_we;
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                                r_addr <= i_wb_addr;
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                                r_data <= i_wb_data;
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                                r_sel  <= i_wb_sel;
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                                r_stb  <= i_wb_stb;
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                                r_rtn_stall <= i_wb_stb;
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                        end
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                        if (!i_wb_cyc)
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                        begin
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                                o_dly_stb <= 1'b0;
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                                r_stb <= 1'b0;
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                                r_rtn_stall <= 1'b0;
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                        end
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                        o_wb_ack  <= (i_dly_ack)&&(i_wb_cyc)&&(o_dly_cyc);
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                        o_wb_data <= i_dly_data;
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                        r_rtn_err <= (i_dly_err)&&(i_wb_cyc)&&(o_dly_cyc);
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                end
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                assign  o_wb_stall = r_rtn_stall;
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                assign  o_wb_err   = r_rtn_err;
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        end else begin
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                initial o_dly_cyc = 1'b0;
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                initial o_dly_stb = 1'b0;
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                always @(posedge i_clk)
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                        o_dly_cyc <= i_wb_cyc;
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                // Add the i_wb_cyc criteria here, so we can simplify the
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                // o_wb_stall criteria below, which would otherwise *and*
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                // these two.
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                always @(posedge i_clk)
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                        if (~o_wb_stall)
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                                o_dly_stb <= ((i_wb_cyc)&&(i_wb_stb));
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                always @(posedge i_clk)
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                        if (~o_wb_stall)
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                                o_dly_we  <= i_wb_we;
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                always @(posedge i_clk)
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                        if (~o_wb_stall)
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                                o_dly_addr<= i_wb_addr;
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                always @(posedge i_clk)
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                        if (~o_wb_stall)
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                                o_dly_data <= i_wb_data;
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                always @(posedge i_clk)
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                        if (~o_wb_stall)
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                                o_dly_sel <= i_wb_sel;
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                always @(posedge i_clk)
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                        o_wb_ack  <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
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                always @(posedge i_clk)
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                        o_wb_data <= i_dly_data;
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                // Our only non-delayed line, yet still really delayed.  Perhaps
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                // there's a way to register this?
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                // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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                // assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc
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                assign  o_wb_stall = ((i_dly_stall)&&(o_dly_stb));//&&o_cyc
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                assign  o_wb_err   = i_dly_err;
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        end endgenerate
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endmodule

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