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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbarbiter.v] - Blame information for rev 201

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbarbiter.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     At some point in time, I might wish to have two masters connect
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//              to the same wishbone bus.  As an example, I might wish to have
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//              both the instruction fetch and the load/store operators
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//              of my Zip CPU access the the same bus.  How shall they both
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//              get access to the same resource?  This module allows the
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//              wishbone interfaces from two sources to drive the bus, while
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//              guaranteeing that only one drives the bus at a time.
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//
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//              The core logic works like this:
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//
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//              1. If 'A' or 'B' asserts the o_cyc line, a bus cycle will begin,
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//                      with acccess granted to whomever requested it.
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//              2. If both 'A' and 'B' assert o_cyc at the same time, only 'A'
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//                      will be granted the bus.  (If the alternating parameter 
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//                      is set, A and B will alternate who gets the bus in
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//                      this case.)
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//              3. The bus will remain owned by whomever the bus was granted to
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//                      until they deassert the o_cyc line.
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//              4. At the end of a bus cycle, o_cyc is guaranteed to be
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//                      deasserted (low) for one clock.
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//              5. On the next clock, bus arbitration takes place again.  If
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//                      'A' requests the bus, no matter how long 'B' was
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//                      waiting, 'A' will then be granted the bus.  (Unless
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//                      again the alternating parameter is set, then the
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//                      access is guaranteed to switch to B.)
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`define WBA_ALTERNATING
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module  wbarbiter(i_clk, i_rst,
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        // Bus A
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        i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
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        // Bus B
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        i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
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        // Both buses
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        o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
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        // 18 bits will address one GB, 4 bytes at a time.
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        // 19 bits will allow the ability to address things other than just
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        // the 1GB of memory we are expecting.
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        parameter                       DW=32, AW=19;
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        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
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        // what it would (might) do to the synchronous reset signal, i_rst.
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        input                           i_clk, i_rst;
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        input           [(AW-1):0]       i_a_adr, i_b_adr;
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        input           [(DW-1):0]       i_a_dat, i_b_dat;
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        input           [(DW/8-1):0]     i_a_sel, i_b_sel;
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        input                           i_a_we, i_a_stb, i_a_cyc;
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        input                           i_b_we, i_b_stb, i_b_cyc;
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        output  wire                    o_a_ack, o_b_ack, o_a_stall, o_b_stall,
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                                        o_a_err, o_b_err;
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        output  wire    [(AW-1):0]       o_adr;
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        output  wire    [(DW-1):0]       o_dat;
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        output  wire    [(DW/8-1):0]     o_sel;
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        output  wire                    o_we, o_stb, o_cyc;
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        input                           i_ack, i_stall, i_err;
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        // All the fancy stuff here is done with the three primary signals:
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        //      o_cyc
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        //      w_a_owner
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        //      w_b_owner
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        // These signals are helped by r_cyc, r_a_owner, and r_b_owner.
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        // If you understand these signals, all else will fall into place.
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        // r_cyc just keeps track of the last o_cyc value.  That way, on
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        // the next clock we can tell if we've had one non-cycle before
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        // starting another cycle.  Specifically, no new cycles will be
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        // allowed to begin unless r_cyc=0.
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        reg     r_cyc;
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        always @(posedge i_clk)
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                if (i_rst)
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                        r_cyc <= 1'b0;
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                else
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                        r_cyc <= o_cyc;
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        // Go high immediately (new cycle) if ...
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        //      Previous cycle was low and *someone* is requesting a bus cycle
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        // Go low immadiately if ...
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        //      We were just high and the owner no longer wants the bus
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        // WISHBONE Spec recommends no logic between a FF and the o_cyc
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        //      This violates that spec.  (Rec 3.15, p35)
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        assign o_cyc = ((~r_cyc)&&((i_a_cyc)||(i_b_cyc))) || ((r_cyc)&&((w_a_owner)||(w_b_owner)));
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        // Register keeping track of the last owner, wire keeping track of the
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        // current owner allowing us to not lose a clock in arbitrating the
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        // first clock of the bus cycle
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        reg     r_a_owner, r_b_owner;
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        wire    w_a_owner, w_b_owner;
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`ifdef  WBA_ALTERNATING
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        reg     r_a_last_owner;
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`endif
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        always @(posedge i_clk)
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                if (i_rst)
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                begin
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                        r_a_owner <= 1'b0;
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                        r_b_owner <= 1'b0;
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                end else begin
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                        r_a_owner <= w_a_owner;
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                        r_b_owner <= w_b_owner;
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`ifdef  WBA_ALTERNATING
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                        if (w_a_owner)
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                                r_a_last_owner <= 1'b1;
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                        else if (w_b_owner)
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                                r_a_last_owner <= 1'b0;
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`endif
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                end
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        //
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        // If you are the owner, retain ownership until i_x_cyc is no
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        // longer asserted.  Likewise, you cannot become owner until o_cyc
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        // is de-asserted for one cycle.
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        //
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        // 'A' is given arbitrary priority over 'B'
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        // 'A' may own the bus only if he wants it.  When 'A' drops i_a_cyc,
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        // o_cyc must drop and so must w_a_owner on the same cycle.
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        // However, when 'A' asserts i_a_cyc, he can only capture the bus if
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        // it's had an idle cycle.
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        // The same is true for 'B' with one exception: if both contend for the
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        // bus on the same cycle, 'A' arbitrarily wins.
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`ifdef  WBA_ALTERNATING
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        assign w_a_owner = (i_a_cyc)    // if A requests ownership, and either
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                        && ((r_a_owner) // A has already been recognized or
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                        || ((~r_cyc) // the bus is free and
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                                &&((~i_b_cyc) // B has not requested, or if he 
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                                ||(~r_a_last_owner)) )); // has, it's A's turn
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        assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&((~i_a_cyc)||(r_a_last_owner)) ));
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`else
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        assign w_a_owner = (i_a_cyc)&& ((r_a_owner) ||  (~r_cyc) );
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        assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&(~i_a_cyc)) );
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`endif
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        // Realistically, if neither master owns the bus, the output is a
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        // don't care.  Thus we trigger off whether or not 'A' owns the bus.
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        // If 'B' owns it all we care is that 'A' does not.  Likewise, if 
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        // neither owns the bus than the values on the various lines are
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        // irrelevant.  (This allows us to get two outputs per Xilinx 6-LUT)
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        assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb);
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        assign o_we  = (w_a_owner) ? i_a_we  : i_b_we;
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        assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr;
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        assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat;
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        assign o_sel = (w_a_owner) ? i_a_sel : i_b_sel;
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        // We cannot allow the return acknowledgement to ever go high if
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        // the master in question does not own the bus.  Hence we force it
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        // low if the particular master doesn't own the bus.
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        assign  o_a_ack   = (w_a_owner) ? i_ack   : 1'b0;
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        assign  o_b_ack   = (w_b_owner) ? i_ack   : 1'b0;
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        // Stall must be asserted on the same cycle the input master asserts
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        // the bus, if the bus isn't granted to him.
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        assign  o_a_stall = (w_a_owner) ? i_stall : 1'b1;
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        assign  o_b_stall = (w_b_owner) ? i_stall : 1'b1;
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        //
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        //
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        assign  o_a_err = (w_a_owner) ? i_err : 1'b0;
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        assign  o_b_err = (w_b_owner) ? i_err : 1'b0;
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endmodule
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