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[/] [zipcpu/] [trunk/] [rtl/] [core/] [README.md] - Blame information for rev 209

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## The Core of the ZipCPU
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Here are the core files to the ZipCPU.  In here, you'll find not only the
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[main ZipCPU core](./zipcpu.v), but also:
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- Several prefetch routines
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  o [prefetch.v](./prefetch.v) an older prefetch module that only fetched
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    one instruction at a time, and so prevented pipelining
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  o [pipefetch.v](./pipefetch.v), my first attempt at building a prefetch with
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    cache.  It took a rather unique approach to the cache, implementing it as
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    a rolling window in memory.  This file really sticks around for historical
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    reasons, but not much more.
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  o [dblfetch.v](./dbgfetch.v), fetches two instructions at once (on subsequent
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    clocks).  This is designed to increase the speed of the CPU when it isn't
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    pipelined, by exploiting the fact that many memory accesses go faster for
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    the second access.
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  o [pfcache.v](./pfcache.v), this is the current/best instruction cache
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    for the CPU.
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- [idecode.v](./idecode.v), an instruction decoder
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- Several memory access routines
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  o [memops.v](./memops.v), a typical/traditional one memory operation at a
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    time means of accessing memory.  This was my first approach to memory,
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    and the appropriate approach still when the CPU is not running in its
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    pipelind mode.
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  o [pipemem.v](./pipemem.v), a faster memory access method that groups
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    consecutive memory accesses together into a pipelined bus access.
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    This routine has so far compensated for the fact that the ZipCPU does not
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    (yet) have an integrated data cache.
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  o [dcache.v](./dcache.v), is my attempt at building a data cache.  This
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    has never been integrated with the CPU, and may not be integrated until
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    the MMU is also integrated.
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- [div.v](./div.v), the divide unit
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- [cpuops.v](./cpuops.v), the ALU unit
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The defines within [cpudefs.v](../cpudefs.v) will determine which of these
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modules gets linked into your CPU.
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