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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    cpuops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This supports the instruction set reordering of operations
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//              created by the second generation instruction set, as well as
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//      the new operations of POPC (population count) and BREV (bit reversal).
10 2 dgisselq
//
11 69 dgisselq
//
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// Creator:     Dan Gisselquist, Ph.D.
13 69 dgisselq
//              Gisselquist Technology, LLC
14 2 dgisselq
//
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///////////////////////////////////////////////////////////////////////////
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//
17 193 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
19
// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
28
//
29
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
32
//
33
///////////////////////////////////////////////////////////////////////////
34
//
35 193 dgisselq
`include "cpudefs.v"
36
//
37
module  cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
38
                        o_busy);
39
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
40 2 dgisselq
        input           i_clk, i_rst, i_ce;
41
        input           [3:0]    i_op;
42
        input           [31:0]   i_a, i_b;
43
        output  reg     [31:0]   o_c;
44
        output  wire    [3:0]    o_f;
45
        output  reg             o_valid;
46 71 dgisselq
        output  wire            o_busy;
47 2 dgisselq
 
48 62 dgisselq
        // Rotate-left pre-logic
49 2 dgisselq
        wire    [63:0]   w_rol_tmp;
50
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
51
        wire    [31:0]   w_rol_result;
52
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
53 62 dgisselq
 
54
        // Shift register pre-logic
55 175 dgisselq
        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
56
        wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
57
        assign  w_pre_asr_input = { i_a, 1'b0 };
58
        assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
59 56 dgisselq
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
60 175 dgisselq
                                : w_pre_asr_shifted;// ASR
61
        assign  w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
62
                                :((i_b[5])?{32'h0,i_a[31]}
63
 
64
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
65
        assign  w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
66
                                :((i_b[5])?{i_a[0], 32'h0}
67
                                : ({1'b0, i_a } << i_b[4:0]));   // LSL
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69 69 dgisselq
        // Bit reversal pre-logic
70
        wire    [31:0]   w_brev_result;
71
        genvar  k;
72
        generate
73
        for(k=0; k<32; k=k+1)
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        begin : bit_reversal_cpuop
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                assign w_brev_result[k] = i_b[31-k];
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        end endgenerate
77 25 dgisselq
 
78 69 dgisselq
        // Popcount pre-logic
79
        wire    [31:0]   w_popc_result;
80
        assign  w_popc_result[5:0]=
81
                 ({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
82
                +({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
83
                +({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
84
                +({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
85
                +({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
86
                +({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
87
                +({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
88
                +({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
89
        assign  w_popc_result[31:6] = 26'h00;
90
 
91
        // Prelogic for our flags registers
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        wire    z, n, v;
93
        reg     c, pre_sign, set_ovfl;
94
        always @(posedge i_clk)
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                if (i_ce) // 1 LUT
96
                        set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
97
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
98
                                ||(i_op == 4'h6) // LSL
99
                                ||(i_op == 4'h5)); // LSR
100 56 dgisselq
 
101 193 dgisselq
        wire    [63:0]   mpy_result; // Where we dump the multiply result
102
        reg     mpyhi;          // Return the high half of the multiply
103
        wire    mpybusy;        // The multiply is busy if true
104
        wire    mpydone;        // True if we'll be valid on the next clock;
105 62 dgisselq
 
106
        // A 4-way multiplexer can be done in one 6-LUT.
107
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
108
        //      the Xilinx multiplexer fabric that follows. 
109
        // Given that we wish to apply this multiplexer approach to 33-bits,
110
        // this will cost a minimum of 132 6-LUTs.
111 193 dgisselq
 
112
        wire    this_is_a_multiply_op;
113
        assign  this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8));
114
 
115 56 dgisselq
        generate
116
        if (IMPLEMENT_MPY == 0)
117 193 dgisselq
        begin // No multiply support.
118
                assign  mpy_result = 63'h00;
119
        end else if (IMPLEMENT_MPY == 1)
120
        begin // Our single clock option (no extra clocks)
121
                wire    signed  [63:0]   w_mpy_a_input, w_mpy_b_input;
122
                assign  w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
123
                assign  w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
124
                assign  mpy_result = w_mpy_a_input * w_mpy_b_input;
125
                assign  mpybusy = 1'b0;
126
                assign  mpydone = 1'b0;
127
                always @(*) mpyhi = 1'b0; // Not needed
128
        end else if (IMPLEMENT_MPY == 2)
129
        begin // Our two clock option (ALU must pause for 1 clock)
130
                reg     signed  [63:0]   r_mpy_a_input, r_mpy_b_input;
131 56 dgisselq
                always @(posedge i_clk)
132 2 dgisselq
                begin
133 193 dgisselq
                        r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
134
                        r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
135 56 dgisselq
                end
136 71 dgisselq
 
137 193 dgisselq
                assign  mpy_result = r_mpy_a_input * r_mpy_b_input;
138
                assign  mpybusy = 1'b0;
139 71 dgisselq
 
140 193 dgisselq
                initial mpypipe = 1'b0;
141
                reg     mpypipe;
142 71 dgisselq
                always @(posedge i_clk)
143 193 dgisselq
                        if (i_rst)
144
                                mpypipe <= 1'b0;
145
                        else
146
                                mpypipe <= (this_is_a_multiply_op);
147
 
148
                assign  mpydone = mpypipe; // this_is_a_multiply_op;
149
                always @(posedge i_clk)
150
                        if (this_is_a_multiply_op)
151
                                mpyhi  = i_op[1];
152
        end else if (IMPLEMENT_MPY == 3)
153
        begin // Our three clock option (ALU pauses for 2 clocks)
154
                reg     signed  [63:0]   r_smpy_result;
155
                reg             [63:0]   r_umpy_result;
156
                reg     signed  [31:0]   r_mpy_a_input, r_mpy_b_input;
157
                reg             [1:0]    mpypipe;
158
                reg             [1:0]    r_sgn;
159
 
160
                initial mpypipe = 2'b0;
161
                always @(posedge i_clk)
162
                        if (i_rst)
163
                                mpypipe <= 2'b0;
164
                        else
165
                        mpypipe <= { mpypipe[0], this_is_a_multiply_op };
166
 
167
                // First clock
168
                always @(posedge i_clk)
169
                begin
170
                        r_mpy_a_input <= i_a[31:0];
171
                        r_mpy_b_input <= i_b[31:0];
172
                        r_sgn <= { r_sgn[0], i_op[0] };
173
                end
174
 
175
                // Second clock
176
`ifdef  VERILATOR
177
                wire    signed  [63:0]   s_mpy_a_input, s_mpy_b_input;
178
                wire            [63:0]   u_mpy_a_input, u_mpy_b_input;
179
 
180
                assign  s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input};
181
                assign  s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input};
182
                assign  u_mpy_a_input = {32'h00,r_mpy_a_input};
183
                assign  u_mpy_b_input = {32'h00,r_mpy_b_input};
184
                always @(posedge i_clk)
185
                        r_smpy_result = s_mpy_a_input * s_mpy_b_input;
186
                always @(posedge i_clk)
187
                        r_umpy_result = u_mpy_a_input * u_mpy_b_input;
188
`else
189
 
190
                wire            [31:0]   u_mpy_a_input, u_mpy_b_input;
191
 
192
                assign  u_mpy_a_input = r_mpy_a_input;
193
                assign  u_mpy_b_input = r_mpy_b_input;
194
 
195
                always @(posedge i_clk)
196
                        r_smpy_result = r_mpy_a_input * r_mpy_b_input;
197
                always @(posedge i_clk)
198
                        r_umpy_result = u_mpy_a_input * u_mpy_b_input;
199 133 dgisselq
`endif
200 193 dgisselq
 
201
                always @(posedge i_clk)
202
                        if (this_is_a_multiply_op)
203
                                mpyhi  = i_op[1];
204
                assign  mpybusy = mpypipe[0];
205
                assign  mpy_result = (r_sgn[1])?r_smpy_result:r_umpy_result;
206
                assign  mpydone = mpypipe[1];
207
 
208
                // Results are then set on the third clock
209
        end else // if (IMPLEMENT_MPY <= 4)
210
        begin // The three clock option
211 133 dgisselq
                reg     [63:0]   r_mpy_result;
212 193 dgisselq
                reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
213
                reg             r_mpy_signed;
214
                reg     [2:0]    mpypipe;
215 133 dgisselq
 
216 193 dgisselq
                // First clock, latch in the inputs
217
                always @(posedge i_clk)
218
                begin
219
                        // mpypipe indicates we have a multiply in the
220
                        // pipeline.  In this case, the multiply
221
                        // pipeline is a two stage pipeline, so we need 
222
                        // two bits in the pipe.
223
                        if (i_rst)
224
                                mpypipe <= 3'h0;
225
                        else begin
226
                                mpypipe[0] <= this_is_a_multiply_op;
227 133 dgisselq
                                mpypipe[1] <= mpypipe[0];
228 193 dgisselq
                                mpypipe[2] <= mpypipe[1];
229 133 dgisselq
                        end
230
 
231 193 dgisselq
                        if (i_op[0]) // i.e. if signed multiply
232 133 dgisselq
                        begin
233 193 dgisselq
                                r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
234
                                r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
235
                        end else begin
236
                                r_mpy_a_input <= i_a[31:0];
237
                                r_mpy_b_input <= i_b[31:0];
238 133 dgisselq
                        end
239 193 dgisselq
                        // The signed bit really only matters in the
240
                        // case of 64 bit multiply.  We'll keep track
241
                        // of it, though, and pretend in all other
242
                        // cases.
243
                        r_mpy_signed  <= i_op[0];
244 133 dgisselq
 
245 193 dgisselq
                        if (this_is_a_multiply_op)
246
                                mpyhi  = i_op[1];
247
                end
248 56 dgisselq
 
249 193 dgisselq
                assign  mpybusy = |mpypipe[1:0];
250
                assign  mpydone = mpypipe[2];
251
 
252
                // Second clock, do the multiplies, get the "partial
253
                // products".  Here, we break our input up into two
254
                // halves, 
255 62 dgisselq
                //
256 193 dgisselq
                //   A  = (2^16 ah + al)
257
                //   B  = (2^16 bh + bl)
258 62 dgisselq
                //
259 193 dgisselq
                // and use these to compute partial products.
260
                //
261
                //   AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl)
262
                //
263
                // Since we're following the FOIL algorithm to get here,
264
                // we'll name these partial products according to FOIL.
265
                //
266
                // The trick is what happens if A or B is signed.  In
267
                // those cases, the real value of A will not be given by
268
                //      A = (2^16 ah + al)
269
                // but rather
270
                //      A = (2^16 ah[31^] + al) - 2^31
271
                //  (where we have flipped the sign bit of A)
272
                // and so ...
273
                //
274
                // AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31)
275
                //      = 2^32(ah*bh)
276
                //              +2^16 (ah*bl+al*bh)
277
                //              +(al*bl)
278
                //              - 2^31 (2^16 bh+bl + 2^16 ah+al)
279
                //              - 2^62
280
                //      = 2^32(ah*bh)
281
                //              +2^16 (ah*bl+al*bh)
282
                //              +(al*bl)
283
                //              - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31)
284
                //
285
                reg     [31:0]   pp_f, pp_l; // F and L from FOIL
286
                reg     [32:0]   pp_oi; // The O and I from FOIL
287
                reg     [32:0]   pp_s;
288 56 dgisselq
                always @(posedge i_clk)
289
                begin
290 193 dgisselq
                        pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16];
291
                        pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0]
292
                                + r_mpy_a_input[15: 0]*r_mpy_b_input[31:16];
293
                        pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0];
294
                        // And a special one for the sign
295
                        if (r_mpy_signed)
296
                                pp_s <= 32'h8000_0000-(
297
                                        r_mpy_a_input[31:0]
298
                                        + r_mpy_b_input[31:0]);
299
                        else
300
                                pp_s <= 33'h0;
301
                end
302 2 dgisselq
 
303 193 dgisselq
                // Third clock, add the results and produce a product
304 56 dgisselq
                always @(posedge i_clk)
305 193 dgisselq
                begin
306
                        r_mpy_result[15:0] <= pp_l[15:0];
307
                        r_mpy_result[63:16] <=
308
                                { 32'h00, pp_l[31:16] }
309
                                + { 15'h00, pp_oi }
310
                                + { pp_s, 15'h00 }
311
                                + { pp_f, 16'h00 };
312
                end
313 71 dgisselq
 
314 193 dgisselq
                assign  mpy_result = r_mpy_result;
315
                // Fourth clock -- results are clocked into writeback
316
        end
317
        endgenerate // All possible multiply results have been determined
318 71 dgisselq
 
319 193 dgisselq
        //
320
        // The master ALU case statement
321
        //
322
        always @(posedge i_clk)
323
        if (i_ce)
324
        begin
325
                pre_sign <= (i_a[31]);
326
                c <= 1'b0;
327
                casez(i_op)
328
                4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
329
                4'b0001:   o_c   <= i_a & i_b;          // BTST/And
330
                4'b0010:{c,o_c } <= i_a + i_b;          // Add
331
                4'b0011:   o_c   <= i_a | i_b;          // Or
332
                4'b0100:   o_c   <= i_a ^ i_b;          // Xor
333
                4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
334
                4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
335
                4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
336
                4'b1000:   o_c   <= mpy_result[31:0]; // MPY
337
                4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
338
                4'b1010:   o_c   <= mpy_result[63:32]; // MPYHU
339
                4'b1011:   o_c   <= mpy_result[63:32]; // MPYHS
340
                4'b1100:   o_c   <= w_brev_result;      // BREV
341
                4'b1101:   o_c   <= w_popc_result;      // POPC
342
                4'b1110:   o_c   <= w_rol_result;       // ROL
343
                default:   o_c   <= i_b;                // MOV, LDI
344
                endcase
345
        end else // if (mpydone)
346
                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
347 56 dgisselq
 
348 193 dgisselq
        reg     r_busy;
349
        initial r_busy = 1'b0;
350
        always @(posedge i_clk)
351
                if (i_rst)
352
                        r_busy <= 1'b0;
353
                else
354
                        r_busy <= ((IMPLEMENT_MPY > 1)
355
                                        &&(this_is_a_multiply_op))||mpybusy;
356
        assign  o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
357
 
358
 
359 2 dgisselq
        assign  z = (o_c == 32'h0000);
360
        assign  n = (o_c[31]);
361
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
362
 
363
        assign  o_f = { v, n, c, z };
364
 
365
        initial o_valid = 1'b0;
366
        always @(posedge i_clk)
367
                if (i_rst)
368
                        o_valid <= 1'b0;
369 193 dgisselq
                else if (IMPLEMENT_MPY <= 1)
370
                        o_valid <= (i_ce);
371 56 dgisselq
                else
372 193 dgisselq
                        o_valid <=((i_ce)&&(!this_is_a_multiply_op))||(mpydone);
373
 
374 2 dgisselq
endmodule

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